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- Committer: Bazaar Package Importer
- Author(s): Soren Hansen
- Date: 2007-10-22 17:07:29 UTC
- mto: (1.5.1) (10.1.1 squeeze) (11.1.1 experimental) (12.1.1 sid) (6.1.1 sid)
- mto: This revision was merged to the branch mainline in revision 3.
- Revision ID: james.westby@ubuntu.com-20071022170729-4ihaxntpl01xg29n
Tags: upstream-0.9.0+20070816
Import upstream version 0.9.0+20070816
- files added:
- block-parallels.c
- linux-user/alpha
- linux-user/ppc64
- linux-user/x86_64
- target-alpha
- files removed:
- linux-user/m68k-semi.c
- files modified:
- Changelog
added
removed
mips-dis.c
207
207
#define OP_OP_SDC2 0x3e
208
208
#define OP_OP_SDC3 0x3f /* a.k.a. sd */
209
209
210
/* MIPS DSP ASE */
211
#define OP_SH_DSPACC 11
212
#define OP_MASK_DSPACC 0x3
213
#define OP_SH_DSPACC_S 21
214
#define OP_MASK_DSPACC_S 0x3
215
#define OP_SH_DSPSFT 20
216
#define OP_MASK_DSPSFT 0x3f
217
#define OP_SH_DSPSFT_7 19
218
#define OP_MASK_DSPSFT_7 0x7f
219
#define OP_SH_SA3 21
220
#define OP_MASK_SA3 0x7
221
#define OP_SH_SA4 21
222
#define OP_MASK_SA4 0xf
223
#define OP_SH_IMM8 16
224
#define OP_MASK_IMM8 0xff
225
#define OP_SH_IMM10 16
226
#define OP_MASK_IMM10 0x3ff
227
#define OP_SH_WRDSP 11
228
#define OP_MASK_WRDSP 0x3f
229
#define OP_SH_RDDSP 16
230
#define OP_MASK_RDDSP 0x3f
231
#define OP_SH_BP 11
232
#define OP_MASK_BP 0x3
233
234
/* MIPS MT ASE */
235
#define OP_SH_MT_U 5
236
#define OP_MASK_MT_U 0x1
237
#define OP_SH_MT_H 4
238
#define OP_MASK_MT_H 0x1
239
#define OP_SH_MTACC_T 18
240
#define OP_MASK_MTACC_T 0x3
241
#define OP_SH_MTACC_D 13
242
#define OP_MASK_MTACC_D 0x3
243
244
#define OP_OP_COP0 0x10
245
#define OP_OP_COP1 0x11
246
#define OP_OP_COP2 0x12
247
#define OP_OP_COP3 0x13
248
#define OP_OP_LWC1 0x31
249
#define OP_OP_LWC2 0x32
250
#define OP_OP_LWC3 0x33 /* a.k.a. pref */
251
#define OP_OP_LDC1 0x35
252
#define OP_OP_LDC2 0x36
253
#define OP_OP_LDC3 0x37 /* a.k.a. ld */
254
#define OP_OP_SWC1 0x39
255
#define OP_OP_SWC2 0x3a
256
#define OP_OP_SWC3 0x3b
257
#define OP_OP_SDC1 0x3d
258
#define OP_OP_SDC2 0x3e
259
#define OP_OP_SDC3 0x3f /* a.k.a. sd */
260
210
261
/* Values in the 'VSEL' field. */
211
262
#define MDMX_FMTSEL_IMM_QH 0x1d
212
263
#define MDMX_FMTSEL_IMM_OB 0x1e
213
264
#define MDMX_FMTSEL_VEC_QH 0x15
214
265
#define MDMX_FMTSEL_VEC_OB 0x16
215
266
267
/* UDI */
268
#define OP_SH_UDI1 6
269
#define OP_MASK_UDI1 0x1f
270
#define OP_SH_UDI2 6
271
#define OP_MASK_UDI2 0x3ff
272
#define OP_SH_UDI3 6
273
#define OP_MASK_UDI3 0x7fff
274
#define OP_SH_UDI4 6
275
#define OP_MASK_UDI4 0xfffff
216
276
/* This structure holds information for a particular instruction. */
217
277
218
278
struct mips_opcode
235
295
of bits describing the instruction, notably any relevant hazard
236
296
information. */
237
297
unsigned long pinfo;
298
/* A collection of additional bits describing the instruction. */
299
unsigned long pinfo2;
238
300
/* A collection of bits describing the instruction sets of which this
239
301
instruction or macro is a member. */
240
302
unsigned long membership;
276
338
"x" accept and ignore register name
277
339
"z" must be zero register
278
340
"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
279
"+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
341
"+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
342
LSB (OP_*_SHAMT).
280
343
Enforces: 0 <= pos < 32.
281
"+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
344
"+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
282
345
Requires that "+A" or "+E" occur first to set position.
283
346
Enforces: 0 < (pos+size) <= 32.
284
"+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
347
"+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
285
348
Requires that "+A" or "+E" occur first to set position.
286
349
Enforces: 0 < (pos+size) <= 32.
287
350
(Also used by "dext" w/ different limits, but limits for
288
351
that are checked by the M_DEXT macro.)
289
"+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT).
352
"+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
290
353
Enforces: 32 <= pos < 64.
291
"+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB).
354
"+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
292
355
Requires that "+A" or "+E" occur first to set position.
293
356
Enforces: 32 < (pos+size) <= 64.
294
357
"+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
336
399
"Y" MDMX source register (OP_*_FS)
337
400
"Z" MDMX source register (OP_*_FT)
338
401
402
DSP ASE usage:
403
"2" 2 bit unsigned immediate for byte align (OP_*_BP)
404
"3" 3 bit unsigned immediate (OP_*_SA3)
405
"4" 4 bit unsigned immediate (OP_*_SA4)
406
"5" 8 bit unsigned immediate (OP_*_IMM8)
407
"6" 5 bit unsigned immediate (OP_*_RS)
408
"7" 2 bit dsp accumulator register (OP_*_DSPACC)
409
"8" 6 bit unsigned immediate (OP_*_WRDSP)
410
"9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
411
"0" 6 bit signed immediate (OP_*_DSPSFT)
412
":" 7 bit signed immediate (OP_*_DSPSFT_7)
413
"'" 6 bit unsigned immediate (OP_*_RDDSP)
414
"@" 10 bit signed immediate (OP_*_IMM10)
415
416
MT ASE usage:
417
"!" 1 bit usermode flag (OP_*_MT_U)
418
"$" 1 bit load high flag (OP_*_MT_H)
419
"*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
420
"&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
421
"g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
422
"+t" 5 bit coprocessor 0 destination register (OP_*_RT)
423
"+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
424
425
UDI immediates:
426
"+1" UDI immediate bits 6-10
427
"+2" UDI immediate bits 6-15
428
"+3" UDI immediate bits 6-20
429
"+4" UDI immediate bits 6-25
430
339
431
Other:
340
432
"()" parens surrounding optional value
341
433
"," separates operands
343
435
"+" Start of extension sequence.
344
436
345
437
Characters used so far, for quick reference when adding more:
346
"%[]<>(),+"
438
"234567890"
439
"%[]<>(),+:'@!$*&"
347
440
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
348
"abcdefhijklopqrstuvwxz"
441
"abcdefghijklopqrstuvwxz"
349
442
350
443
Extension character sequences used so far ("+" followed by the
351
444
following), for quick reference when adding more:
352
"ABCDEFGHI"
445
"1234"
446
"ABCDEFGHIT"
447
"t"
353
448
*/
354
449
355
450
/* These are the bits which may be set in the pinfo field of an
419
514
#define INSN_MULT 0x40000000
420
515
/* Instruction synchronize shared memory. */
421
516
#define INSN_SYNC 0x80000000
422
/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */
423
#define INSN_READ_MDMX_ACC 0
424
/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */
425
#define INSN_WRITE_MDMX_ACC 0
517
518
/* These are the bits which may be set in the pinfo2 field of an
519
instruction. */
520
521
/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
522
#define INSN2_ALIAS 0x00000001
523
/* Instruction reads MDMX accumulator. */
524
#define INSN2_READ_MDMX_ACC 0x00000002
525
/* Instruction writes MDMX accumulator. */
526
#define INSN2_WRITE_MDMX_ACC 0x00000004
426
527
427
528
/* Instruction is actually a macro. It should be ignored by the
428
529
disassembler, and requires special treatment by the assembler. */
447
548
/* Masks used for MIPS-defined ASEs. */
448
549
#define INSN_ASE_MASK 0x0000f000
449
550
551
/* DSP ASE */
552
#define INSN_DSP 0x00001000
553
#define INSN_DSP64 0x00002000
450
554
/* MIPS 16 ASE */
451
#define INSN_MIPS16 0x00002000
555
#define INSN_MIPS16 0x00004000
452
556
/* MIPS-3D ASE */
453
#define INSN_MIPS3D 0x00004000
454
/* MDMX ASE */
455
#define INSN_MDMX 0x00008000
557
#define INSN_MIPS3D 0x00008000
456
558
457
559
/* Chip specific instructions. These are bitmasks. */
458
560
477
579
/* NEC VR5500 instruction. */
478
580
#define INSN_5500 0x02000000
479
581
582
/* MDMX ASE */
583
#define INSN_MDMX 0x04000000
584
/* MT ASE */
585
#define INSN_MT 0x08000000
586
/* SmartMIPS ASE */
587
#define INSN_SMARTMIPS 0x10000000
588
/* DSP R2 ASE */
589
#define INSN_DSPR2 0x20000000
590
480
591
/* MIPS ISA defines, use instead of hardcoding ISA level. */
481
592
482
593
#define ISA_UNKNOWN 0 /* Gas internal use. */
533
644
(((insn)->membership & isa) != 0 \
534
645
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
535
646
|| (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
647
|| (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
536
648
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
537
649
|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
538
650
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
563
675
M_ADD_I,
564
676
M_ADDU_I,
565
677
M_AND_I,
678
M_BALIGN,
566
679
M_BEQ,
567
680
M_BEQ_I,
568
681
M_BEQL_I,
601
714
M_BNE,
602
715
M_BNE_I,
603
716
M_BNEL_I,
717
M_CACHE_AB,
604
718
M_DABS,
605
719
M_DADD_I,
606
720
M_DADDU_I,
907
1021
"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
908
1022
*/
909
1023
1024
/* Save/restore encoding for the args field when all 4 registers are
1025
either saved as arguments or saved/restored as statics. */
1026
#define MIPS16_ALL_ARGS 0xe
1027
#define MIPS16_ALL_STATICS 0xb
1028
910
1029
/* For the mips16, we use the same opcode table format and a few of
911
1030
the same flags. However, most of the flags are different. */
912
1031
1008
1127
1009
1128
#define IS_M INSN_MULT
1010
1129
1011
#define WR_MACC INSN_WRITE_MDMX_ACC
1012
#define RD_MACC INSN_READ_MDMX_ACC
1130
#define WR_MACC INSN2_WRITE_MDMX_ACC
1131
#define RD_MACC INSN2_READ_MDMX_ACC
1013
1132
1014
1133
#define I1 INSN_ISA1
1015
1134
#define I2 INSN_ISA2
1024
1143
/* MIPS64 MIPS-3D ASE support. */
1025
1144
#define I16 INSN_MIPS16
1026
1145
1146
/* MIPS32 SmartMIPS ASE support. */
1147
#define SMT INSN_SMARTMIPS
1148
1027
1149
/* MIPS64 MIPS-3D ASE support. */
1028
1150
#define M3D INSN_MIPS3D
1029
1151
1051
1173
#define G3 (I4 \
1052
1174
)
1053
1175
1176
/* MIPS DSP ASE support.
1177
NOTE:
1178
1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair
1179
of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have
1180
the same structure as $ac0 (HI + LO). For DSP instructions that write or
1181
read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
1182
(RD_HILO) attributes, such that HILO dependencies are maintained
1183
conservatively.
1184
1185
2. For some mul. instructions that use integer registers as destinations
1186
but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
1187
1188
3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
1189
(ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write
1190
certain fields of the DSP control register. For simplicity, we decide not
1191
to track dependencies of these fields.
1192
However, "bposge32" is a branch instruction that depends on the "pos"
1193
field. In order to make sure that GAS does not reorder DSP instructions
1194
that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
1195
attribute to those instructions that write the "pos" field. */
1196
1197
#define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */
1198
#define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */
1199
#define MOD_a WR_a|RD_a
1200
#define DSP_VOLA INSN_TRAP
1201
#define D32 INSN_DSP
1202
#define D33 INSN_DSPR2
1203
#define D64 INSN_DSP64
1204
1205
/* MIPS MT ASE support. */
1206
#define MT32 INSN_MT
1207
1054
1208
/* The order of overloaded instructions matters. Label arguments and
1055
1209
register arguments look the same. Instructions that can have either
1056
1210
for arguments must apear in the correct order in this table for the
1070
1224
them first. The assemblers uses a hash table based on the
1071
1225
instruction name anyhow. */
1072
1226
/* name, args, match, mask, pinfo, membership */
1073
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I4|I32|G3 },
1074
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 },
1075
{"nop", "", 0x00000000, 0xffffffff, 0, I1 }, /* sll */
1076
{"ssnop", "", 0x00000040, 0xffffffff, 0, I32|N55 }, /* sll */
1077
{"ehb", "", 0x000000c0, 0xffffffff, 0, I33 }, /* sll */
1078
{"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */
1079
{"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */
1080
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 },
1081
{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, I1 },
1082
{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */
1083
{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */
1084
{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */
1085
{"b", "p", 0x10000000, 0xffff0000, UBD, I1 },/* beq 0,0 */
1086
{"b", "p", 0x04010000, 0xffff0000, UBD, I1 },/* bgez 0 */
1087
{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, I1 },/* bgezal 0*/
1227
{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 },
1228
{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 },
1229
{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
1230
{"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32|N55 }, /* sll */
1231
{"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */
1232
{"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */
1233
{"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */
1234
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 },
1235
{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 },
1236
{"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */
1237
{"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */
1238
{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */
1239
{"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */
1240
{"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */
1241
{"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/
1088
1242
1089
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, I1 },
1090
{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, I1 },
1091
{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, I1 },
1092
{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, I5 },
1093
{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1094
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, I1 },
1095
{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
1096
{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
1097
{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1098
{"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1099
{"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1100
{"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1101
{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
1102
{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1103
{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
1104
{"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
1105
{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, I1 },
1106
{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, I1 },
1107
{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
1108
{"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
1109
{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
1110
{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1111
{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, I1 },
1112
{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1113
{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, N54 },
1114
{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, MX },
1115
{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, I5 },
1116
{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX|SB1 },
1117
{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, MX },
1118
{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1119
{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, I1 },
1120
{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1121
{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1122
{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1123
{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1124
{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1125
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, I1 },
1243
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
1244
{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1245
{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
1246
{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 },
1247
{"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
1248
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
1249
{"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
1250
{"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
1251
{"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1252
{"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1253
{"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1254
{"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1255
{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
1256
{"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1257
{"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1258
{"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1259
{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 },
1260
{"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 },
1261
{"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1262
{"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1263
{"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
1264
{"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
1265
{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 },
1266
{"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1267
{"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 },
1268
{"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1269
{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
1270
{"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 },
1271
{"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX },
1272
{"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
1273
{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 },
1274
{"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1275
{"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1276
{"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1277
{"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1278
{"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1279
{"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
1126
1280
/* b is at the top of the table. */
1127
1281
/* bal is at the top of the table. */
1128
{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, I1 },
1129
{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, I2|T3 },
1130
{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 },
1131
{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 },
1132
{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, M3D },
1133
{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, M3D },
1134
{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, M3D },
1135
{"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, M3D },
1136
{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1 },
1137
{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32 },
1138
{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
1139
{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32 },
1140
{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 },
1141
{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4|I32 },
1142
{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
1143
{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4|I32 },
1282
/* bc0[tf]l? are at the bottom of the table. */
1283
{"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1284
{"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1285
{"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1286
{"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1287
{"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
1288
{"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 },
1289
{"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 },
1290
{"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 },
1291
{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
1292
{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 },
1293
{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 },
1294
{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 },
1144
1295
/* bc2* are at the bottom of the table. */
1145
{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, I1 },
1146
{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, I2|T3 },
1147
{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 },
1148
{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, I2|T3 },
1149
{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, I1 },
1150
{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
1151
{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, I1 },
1152
{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, I1 },
1153
{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
1154
{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, I2|T3 },
1155
{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, I1 },
1156
{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, I1 },
1157
{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, I2|T3 },
1158
{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, I2|T3 },
1159
{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, I1 },
1160
{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, I1 },
1161
{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, I2|T3 },
1162
{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, I2|T3 },
1163
{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 },
1164
{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 },
1165
{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 },
1166
{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, I2|T3 },
1167
{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, I1 },
1168
{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, I1 },
1169
{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, I2|T3 },
1170
{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, I2|T3 },
1171
{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, I1 },
1172
{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, I1 },
1173
{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, I2|T3 },
1174
{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, I2|T3 },
1175
{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, I1 },
1176
{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
1177
{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, I1 },
1178
{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, I1 },
1179
{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, I2|T3 },
1180
{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, I2|T3 },
1181
{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, I1 },
1182
{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, I1 },
1183
{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, I2|T3 },
1184
{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, I2|T3 },
1185
{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, I1 },
1186
{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
1187
{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, I1 },
1188
{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, I1 },
1189
{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, I2|T3 },
1190
{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, I2|T3 },
1191
{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, I1 },
1192
{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, I1 },
1193
{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, I2|T3 },
1194
{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, I2|T3 },
1195
{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 },
1196
{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 },
1197
{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 },
1198
{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, I2|T3 },
1199
{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 },
1200
{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2|T3 },
1201
{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 },
1202
{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, I1 },
1203
{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 },
1204
{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2|T3 },
1205
{"break", "", 0x0000000d, 0xffffffff, TRAP, I1 },
1206
{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 },
1207
{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 },
1208
{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1209
{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1210
{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1211
{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1212
{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1213
{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1214
{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1215
{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1216
{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1217
{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1218
{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1219
{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1220
{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1221
{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1222
{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1223
{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1224
{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 },
1225
{"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1226
{"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 },
1227
{"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1228
{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1229
{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1230
{"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
1231
{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1232
{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1233
{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1234
{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1235
{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1236
{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1237
{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1238
{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1239
{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1240
{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1241
{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1242
{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1243
{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1244
{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1245
{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1246
{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1247
{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1248
{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1249
{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1250
{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1251
{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1252
{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1253
{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1254
{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1255
{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1256
{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1257
{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1258
{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1259
{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1260
{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1261
{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1262
{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1263
{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1264
{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1265
{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1266
{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1267
{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1268
{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1269
{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1270
{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1271
{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1272
{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1273
{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1274
{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1275
{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1276
{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1277
{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1278
{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1279
{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1280
{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1281
{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1282
{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1283
{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1284
{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1285
{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1286
{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1287
{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1288
{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1289
{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 },
1290
{"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1291
{"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 },
1292
{"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1293
{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1294
{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1295
{"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
1296
{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1297
{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1298
{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1299
{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1300
{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1301
{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1302
{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1303
{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1304
{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1305
{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1306
{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX|SB1 },
1307
{"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1308
{"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 },
1309
{"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1310
{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1311
{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1312
{"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, MX },
1313
{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
1314
{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 },
1315
{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
1316
{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 },
1317
{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1318
{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
1319
{"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1320
{"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1321
{"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1322
{"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1323
{"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1324
{"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1325
{"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1326
{"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1327
{"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1328
{"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1329
{"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1330
{"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1331
{"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1332
{"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1333
{"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1334
{"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1335
{"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1336
{"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1337
{"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1338
{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1339
{"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1340
{"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1341
{"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1342
{"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1343
{"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1344
{"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1345
{"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1346
{"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1347
{"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1348
{"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1349
{"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1350
{"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1351
{"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1352
{"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1353
{"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1354
{"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1355
{"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1356
{"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1357
{"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1358
{"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1359
{"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1360
{"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1361
{"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1362
{"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1363
{"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1364
{"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1365
{"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, M3D },
1366
{"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, M3D },
1367
{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|I32|T3},
1368
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3 },
1369
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3 },
1370
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2 },
1371
{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, I2 },
1372
{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
1373
{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
1374
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, I1 },
1296
/* bc3* are at the bottom of the table. */
1297
{"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1298
{"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1299
{"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
1300
{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 },
1301
{"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
1302
{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 },
1303
{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 },
1304
{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 },
1305
{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 },
1306
{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 },
1307
{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 },
1308
{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 },
1309
{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 },
1310
{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 },
1311
{"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1312
{"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1313
{"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 },
1314
{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 },
1315
{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 },
1316
{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 },
1317
{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 },
1318
{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 },
1319
{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 },
1320
{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 },
1321
{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 },
1322
{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 },
1323
{"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1324
{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1325
{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 },
1326
{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 },
1327
{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 },
1328
{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 },
1329
{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 },
1330
{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 },
1331
{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 },
1332
{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 },
1333
{"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1334
{"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1335
{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 },
1336
{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 },
1337
{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 },
1338
{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 },
1339
{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 },
1340
{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 },
1341
{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 },
1342
{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 },
1343
{"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1344
{"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1345
{"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 },
1346
{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 },
1347
{"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1348
{"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1349
{"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
1350
{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 },
1351
{"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
1352
{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 },
1353
{"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 },
1354
{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 },
1355
{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 },
1356
{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1357
{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1358
{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1359
{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1360
{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1361
{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1362
{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1363
{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1364
{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1365
{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1366
{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1367
{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1368
{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1369
{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1370
{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1371
{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1372
{"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
1373
{"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1374
{"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1375
{"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1376
{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1377
{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1378
{"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
1379
{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1380
{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1381
{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1382
{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1383
{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1384
{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1385
{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1386
{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1387
{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1388
{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1389
{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1390
{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1391
{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1392
{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1393
{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1394
{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1395
{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1396
{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1397
{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1398
{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1399
{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1400
{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1401
{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1402
{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1403
{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1404
{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1405
{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1406
{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1407
{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1408
{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1409
{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1410
{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1411
{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1412
{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1413
{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1414
{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1415
{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1416
{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1417
{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1418
{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1419
{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1420
{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1421
{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1422
{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1423
{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1424
{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1425
{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1426
{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1427
{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1428
{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1429
{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1430
{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1431
{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1432
{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1433
{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1434
{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1435
{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1436
{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1437
{"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
1438
{"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1439
{"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1440
{"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1441
{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1442
{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1443
{"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
1444
{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1445
{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1446
{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1447
{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1448
{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1449
{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1450
{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1451
{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1452
{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1453
{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1454
{"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
1455
{"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1456
{"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1457
{"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1458
{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1459
{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1460
{"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
1461
{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1462
{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1463
{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1464
{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1465
{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1466
{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1467
{"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1468
{"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1469
{"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1470
{"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1471
{"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1472
{"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1473
{"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1474
{"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1475
{"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1476
{"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1477
{"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1478
{"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1479
{"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1480
{"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1481
{"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1482
{"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1483
{"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1484
{"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1485
{"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1486
{"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1487
{"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1488
{"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1489
{"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1490
{"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1491
{"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1492
{"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1493
{"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1494
{"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1495
{"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1496
{"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1497
{"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1498
{"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1499
{"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1500
{"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1501
{"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1502
{"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1503
{"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1504
{"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1505
{"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1506
{"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1507
{"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1508
{"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1509
{"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1510
{"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1511
{"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1512
{"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1513
{"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1514
{"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1515
/* CW4010 instructions which are aliases for the cache instruction. */
1516
{"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 },
1517
{"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 },
1518
{"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 },
1519
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 },
1520
{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3},
1521
{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3|I32|T3},
1522
{"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1523
{"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1524
{"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
1525
{"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
1526
{"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
1527
{"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
1528
{"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
1375
1529
/* cfc2 is at the bottom of the table. */
1376
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
1377
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, I32|N55 },
1378
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, I32|N55 },
1379
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
1380
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
1381
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, I1 },
1530
/* cfc3 is at the bottom of the table. */
1531
{"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
1532
{"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
1533
{"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
1534
{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
1535
{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
1536
{"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
1537
{"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
1538
{"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
1382
1539
/* ctc2 is at the bottom of the table. */
1383
{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
1384
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, I3 },
1385
{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_D|FP_S, I1 },
1386
{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_D, I1 },
1387
{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, I3 },
1388
{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S, I3 },
1389
{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S, I3 },
1390
{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I1 },
1391
{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, I1 },
1392
{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 },
1393
{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, I5 },
1394
{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_D, I1 },
1395
{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, I1 },
1396
{"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, M3D },
1397
{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
1398
{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, M3D },
1399
{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, I3 },
1400
{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
1401
{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, I3 },
1402
{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, I3 },
1403
{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, I3 },
1404
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
1405
{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, I3 },
1406
{"dbreak", "", 0x7000003f, 0xffffffff, 0, N5 },
1407
{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, I64|N55 },
1408
{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, I64|N55 },
1540
/* ctc3 is at the bottom of the table. */
1541
{"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
1542
{"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
1543
{"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 },
1544
{"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1545
{"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1546
{"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1547
{"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1548
{"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1549
{"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1550
{"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1551
{"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1552
{"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 },
1553
{"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 },
1554
{"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1555
{"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1556
{"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
1557
{"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5|I33 },
1558
{"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
1559
{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 },
1560
{"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1561
{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
1562
{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 },
1563
{"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 },
1564
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1565
{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 },
1566
{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 },
1567
{"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
1568
{"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
1409
1569
/* dctr and dctw are used on the r5000. */
1410
{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, I3 },
1411
{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, I3 },
1412
{"deret", "", 0x4200001f, 0xffffffff, 0, I32|G2 },
1413
{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, I65 },
1414
{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, I65 },
1415
{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, I65 },
1416
{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, I65 },
1570
{"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 },
1571
{"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 },
1572
{"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 },
1573
{"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 },
1574
{"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 },
1575
{"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 },
1576
{"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 },
1417
1577
/* For ddiv, see the comments about div. */
1418
{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
1419
{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, I3 },
1420
{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, I3 },
1578
{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1579
{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 },
1580
{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 },
1421
1581
/* For ddivu, see the comments about div. */
1422
{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
1423
{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, I3 },
1424
{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, I3 },
1425
{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, I33 },
1426
{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, I33 },
1427
{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, I65 },
1428
{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, I65 },
1429
{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, I65 },
1430
{"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, I65 },
1582
{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1583
{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 },
1584
{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 },
1585
{"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 },
1586
{"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
1587
{"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
1588
{"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 },
1589
{"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 },
1590
{"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 },
1431
1591
/* The MIPS assembler treats the div opcode with two operands as
1432
1592
though the first operand appeared twice (the first operand is both
1433
1593
a source and a destination). To get the div machine instruction,
1434
1594
you must use an explicit destination of $0. */
1435
{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 },
1436
{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, I1 },
1437
{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, I1 },
1438
{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 },
1439
{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
1440
{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
1441
{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, SB1 },
1595
{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1596
{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1597
{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 },
1598
{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 },
1599
{"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
1600
{"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
1601
{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
1442
1602
/* For divu, see the comments about div. */
1443
{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 },
1444
{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, I1 },
1445
{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, I1 },
1446
{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, I1 },
1447
{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, I3 },
1448
{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, I3 },
1449
{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, I3 }, /* addiu */
1450
{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, I3 }, /* ori */
1451
{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, I3 },
1452
{"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1453
{"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1454
{"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1455
{"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1456
{"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1457
{"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1458
{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1459
{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, N412 },
1460
{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, N411 },
1461
{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, I3 },
1462
{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 },
1463
{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, I64 },
1464
{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I3 },
1465
{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 },
1466
{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I64 },
1467
{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
1468
{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I3 },
1469
{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
1470
{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I3 },
1603
{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1604
{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1605
{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 },
1606
{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 },
1607
{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 },
1608
{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 },
1609
{"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */
1610
{"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */
1611
{"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 },
1612
{"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1613
{"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1614
{"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1615
{"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1616
{"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1617
{"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1618
{"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1619
{"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1620
{"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 },
1621
{"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 },
1622
{"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
1623
{"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
1624
{"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },
1625
{"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1626
{"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 },
1627
{"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
1628
{"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
1629
{"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
1630
{"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
1631
{"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
1632
{"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
1471
1633
/* dmfc2 is at the bottom of the table. */
1472
1634
/* dmtc2 is at the bottom of the table. */
1473
{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, I3 },
1474
{"dmfc3", "t,G,H", 0x4c200000, 0xffe007f8, LCD|WR_t|RD_C3, I64 },
1475
{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I3 },
1476
{"dmtc3", "t,G,H", 0x4ca00000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I64 },
1477
{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, I3 },
1478
{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, I3 },
1479
{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, I3 },
1480
{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, I3 },
1481
{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, I3 },
1482
{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, I3 },
1483
{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
1484
{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
1485
{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, I3 }, /* dsub 0 */
1486
{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, I3 }, /* dsubu 0*/
1487
{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
1488
{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, I3 },
1489
{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, I3 },
1490
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, I3 },
1491
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, I3 },
1492
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, I3 },
1493
{"dret", "", 0x7000003e, 0xffffffff, 0, N5 },
1494
{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I3 },
1495
{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I3 },
1496
{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I3 },
1497
{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I3 },
1498
{"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, N5|I65 },
1499
{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, N5|I65 },
1500
{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, N5|I65 },
1501
{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, I65 },
1502
{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, I65 },
1503
{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, I65 },
1504
{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, I65 },
1505
{"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, I65 },
1506
{"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, I65 },
1507
{"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, I65 },
1508
{"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, I65 },
1509
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
1510
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 },
1511
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsllv */
1512
{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, I3 }, /* dsll32 */
1513
{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, I3 },
1514
{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
1515
{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 },
1516
{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrav */
1517
{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, I3 }, /* dsra32 */
1518
{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, I3 },
1519
{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 },
1520
{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 },
1521
{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, I3 }, /* dsrlv */
1522
{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, I3 }, /* dsrl32 */
1523
{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, I3 },
1524
{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
1525
{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, I3 },
1526
{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3 },
1527
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, I3 },
1528
{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, I33 },
1529
{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, I33 },
1530
{"eret", "", 0x42000018, 0xffffffff, 0, I3|I32 },
1531
{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, I33 },
1532
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3 },
1533
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3 },
1534
{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2 },
1535
{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, I2 },
1536
{"flushi", "", 0xbc010000, 0xffffffff, 0, L1 },
1537
{"flushd", "", 0xbc020000, 0xffffffff, 0, L1 },
1538
{"flushid", "", 0xbc030000, 0xffffffff, 0, L1 },
1539
{"hibernate","", 0x42000023, 0xffffffff, 0, V1 },
1540
{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, I33 },
1541
{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 },
1542
{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, I33 },
1543
{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, I1 }, /* jr */
1635
/* dmfc3 is at the bottom of the table. */
1636
/* dmtc3 is at the bottom of the table. */
1637
{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 },
1638
{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 },
1639
{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 },
1640
{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 },
1641
{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 },
1642
{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 },
1643
{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1644
{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1645
{"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */
1646
{"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/
1647
{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1648
{"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, 0, I3 },
1649
{"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, 0, I3 },
1650
{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1651
{"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 },
1652
{"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 },
1653
{"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 },
1654
{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
1655
{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },
1656
{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 },
1657
{"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 },
1658
{"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
1659
{"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65 },
1660
{"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
1661
{"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 },
1662
{"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 },
1663
{"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 },
1664
{"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 },
1665
{"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 },
1666
{"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 },
1667
{"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 },
1668
{"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 },
1669
{"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
1670
{"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 },
1671
{"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */
1672
{"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */
1673
{"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 },
1674
{"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
1675
{"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 },
1676
{"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */
1677
{"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */
1678
{"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 },
1679
{"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
1680
{"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 },
1681
{"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */
1682
{"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */
1683
{"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 },
1684
{"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1685
{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 },
1686
{"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1687
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
1688
{"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
1689
{"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1690
{"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 },
1691
{"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
1692
{"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
1693
{"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1694
{"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 },
1695
{"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
1696
{"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1697
{"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
1698
{"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1699
{"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1700
{"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
1701
{"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
1702
{"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 },
1703
{"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 },
1704
{"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 },
1705
/* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
1706
the same hazard barrier effect. */
1707
{"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 },
1708
{"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */
1544
1709
/* SVR4 PIC code requires special handling for j, so it must be a
1545
1710
macro. */
1546
{"j", "a", 0, (int) M_J_A, INSN_MACRO, I1 },
1711
{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 },
1547
1712
/* This form of j is used by the disassembler and internally by the
1548
1713
assembler, but will never match user input (because the line above
1549
1714
will match first). */
1550
{"j", "a", 0x08000000, 0xfc000000, UBD, I1 },
1551
{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, I1 },
1552
{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, I1 },
1553
{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, I33 },
1554
{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, I33 },
1715
{"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 },
1716
{"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 },
1717
{"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 },
1718
/* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
1719
with the same hazard barrier effect. */
1720
{"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 },
1721
{"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 },
1555
1722
/* SVR4 PIC code requires special handling for jal, so it must be a
1556
1723
macro. */
1557
{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, I1 },
1558
{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, I1 },
1559
{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, I1 },
1724
{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 },
1725
{"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 },
1726
{"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 },
1560
1727
/* This form of jal is used by the disassembler and internally by the
1561
1728
assembler, but will never match user input (because the line above
1562
1729
will match first). */
1563
{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 },
1564
{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I16 },
1565
{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 },
1566
{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
1567
{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, I1 },
1568
{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
1569
{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, I1 },
1570
{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, I1 },
1571
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, I3 },
1572
{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, I1 },
1573
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, I1 },
1574
{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
1575
{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 },
1576
{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 },
1577
{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, I2 },
1578
{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, I2 }, /* ldc1 */
1579
{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, I1 },
1580
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, I1 },
1581
{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
1582
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, I2 },
1583
{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, I2 },
1584
{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, I2 },
1585
{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
1586
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, I3 },
1587
{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, I3 },
1588
{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, I3 },
1589
{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
1590
{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
1591
{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, I1 },
1592
{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
1593
{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, I1 },
1730
{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 },
1731
{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 },
1732
{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 },
1733
{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1734
{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 },
1735
{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1736
{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 },
1737
{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
1738
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
1739
{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
1740
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
1741
{"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
1742
{"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
1743
{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
1744
{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
1745
{"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
1746
{"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 },
1747
{"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 },
1748
{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
1749
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 },
1750
{"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
1751
{"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 },
1752
{"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
1753
{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
1754
{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
1755
{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 },
1756
{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 },
1757
{"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1758
{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 },
1759
{"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1760
{"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 },
1594
1761
/* li is at the start of the table. */
1595
{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, I1 },
1596
{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, I1 },
1597
{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, I1 },
1598
{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, I1 },
1599
{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, I2 },
1600
{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, I2 },
1601
{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
1602
{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, I3 },
1603
{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, I1 },
1604
{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I5|N55 },
1605
{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
1606
{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, I1 },
1607
{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
1608
{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, I1 },
1609
{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
1610
{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 },
1611
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
1612
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
1613
{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, I1 }, /* lwc1 */
1614
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, I1 },
1615
{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
1616
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, I1 },
1617
{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, I1 },
1618
{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, I1 },
1619
{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
1620
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I1 },
1621
{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
1622
{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, I2 }, /* as lwl */
1623
{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I1 },
1624
{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I1 },
1625
{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, I2 }, /* same */
1626
{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, I2 }, /* as lwr */
1627
{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, I3 },
1628
{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, I3 },
1629
{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b, I4 },
1630
{"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1631
{"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1632
{"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1633
{"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1634
{"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1635
{"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1636
{"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1637
{"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1638
{"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1639
{"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1640
{"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1641
{"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N412 },
1642
{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, P3 },
1643
{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, P3 },
1644
{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
1645
{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
1646
{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
1647
{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
1648
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55},
1649
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 },
1650
{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
1651
{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
1652
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55},
1653
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 },
1654
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
1655
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, N411 },
1656
{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1657
{"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1658
{"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1659
{"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1660
{"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1661
{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, M1|N5 },
1662
{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, M1|N5 },
1663
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
1664
{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 },
1665
{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 },
1666
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
1667
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 },
1668
{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I33 },
1669
{"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I33 },
1762
{"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1 },
1763
{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1 },
1764
{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1 },
1765
{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1 },
1766
{"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 },
1767
{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 },
1768
{"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
1769
{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 },
1770
{"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 },
1771
{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5|I33|N55},
1772
{"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1773
{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 },
1774
{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
1775
{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 },
1776
{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
1777
{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
1778
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
1779
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
1780
{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
1781
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
1782
{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
1783
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
1784
{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
1785
{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 },
1786
{"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1787
{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
1788
{"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
1789
{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */
1790
{"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1791
{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
1792
{"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
1793
{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */
1794
{"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 },
1795
{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
1796
{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 },
1797
{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 },
1798
{"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT },
1799
{"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1800
{"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1801
{"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1802
{"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1803
{"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1804
{"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1805
{"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1806
{"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1807
{"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1808
{"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1809
{"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1810
{"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1811
{"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 },
1812
{"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 },
1813
{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
1814
{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
1815
{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
1816
{"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
1817
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
1818
{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
1819
{"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
1820
{"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
1821
{"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
1822
{"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
1823
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
1824
{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
1825
{"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
1826
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
1827
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 },
1828
{"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1829
{"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1830
{"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1831
{"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1832
{"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1833
{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },
1834
{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },
1835
{"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
1836
{"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
1837
{"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
1838
{"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
1839
{"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
1840
{"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
1841
{"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
1842
{"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
1843
{"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 },
1844
{"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
1845
{"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
1846
{"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
1847
{"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
1848
{"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
1849
{"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
1850
{"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
1851
{"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
1852
{"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },
1853
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
1854
{"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
1855
{"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
1856
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
1857
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
1858
{"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
1859
{"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
1670
1860
/* mfc2 is at the bottom of the table. */
1671
1861
/* mfhc2 is at the bottom of the table. */
1672
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
1673
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, I32 },
1674
{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, N5 },
1675
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },
1676
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, I1 },
1677
{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1678
{"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1679
{"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1680
{"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1681
{"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1682
{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1 },
1683
{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1 },
1684
{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, I5 },
1685
{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|I32},
1686
{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 },
1687
{"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 },
1688
{"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 },
1689
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 },
1690
{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
1691
{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 },
1692
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, L1 },
1693
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 },
1694
{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 },
1695
{"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 },
1696
{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 },
1697
{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 },
1698
{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC, I4|I32 },
1699
{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I4|I32 },
1700
{"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 },
1701
{"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, MX|SB1 },
1702
{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, I4|I32 },
1703
{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, I5 },
1704
{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|I32 },
1705
{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, L1 },
1706
{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I4|I32 },
1707
{"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 },
1708
{"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, MX|SB1 },
1709
{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, I4|I32 },
1710
{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, I5 },
1711
{"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1712
{"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1713
{"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1714
{"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1862
/* mfc3 is at the bottom of the table. */
1863
{"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 },
1864
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 },
1865
{"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 },
1866
{"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 },
1867
{"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 },
1868
{"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT },
1869
{"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1870
{"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1871
{"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1872
{"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1873
{"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1874
{"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
1875
{"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1876
{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 },
1877
{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 },
1878
{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 },
1879
{"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
1880
{"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
1881
{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 },
1882
{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 },
1883
{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 },
1884
{"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
1885
{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 },
1886
{"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
1887
{"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
1888
{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 },
1889
{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 },
1890
{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 },
1891
{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 },
1892
{"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
1893
{"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
1894
{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 },
1895
{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 },
1896
{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 },
1897
{"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
1898
{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 },
1899
{"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
1900
{"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
1901
{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 },
1902
{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 },
1903
{"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1904
{"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1905
{"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1906
{"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1715
1907
/* move is at the top of the table. */
1716
{"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1717
{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
1718
{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
1719
{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
1720
{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
1721
{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55 },
1722
{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 },
1723
{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32|N55 },
1724
{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, M1|N5 },
1725
{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, M1|N5 },
1726
{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 },
1727
{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 },
1728
{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 },
1729
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
1730
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 },
1731
{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I33 },
1732
{"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I33 },
1908
{"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1909
{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
1910
{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
1911
{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
1912
{"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
1913
{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
1914
{"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
1915
{"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
1916
{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
1917
{"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
1918
{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
1919
{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
1920
{"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 },
1921
{"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
1922
{"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
1923
{"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
1924
{"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
1925
{"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
1926
{"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
1733
1927
/* mtc2 is at the bottom of the table. */
1734
1928
/* mthc2 is at the bottom of the table. */
1735
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, I1 },
1736
{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, I32 },
1737
{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, N5 },
1738
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, I1 },
1739
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, I1 },
1740
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
1741
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
1742
{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1743
{"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1744
{"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1745
{"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1746
{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
1747
{"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1748
{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, I32|P3|N55},
1749
{"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N54 },
1750
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, I1 },
1751
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, I1 },
1752
{"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
1753
{"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1754
{"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 },
1755
{"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1756
{"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
1757
{"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1758
{"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1759
{"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
1760
{"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1761
{"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 },
1762
{"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1763
{"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
1764
{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, I1 },
1765
{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, I1 },
1766
{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, I1 },
1767
{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, I1 },
1768
{"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
1769
{"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1770
{"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1771
{"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1772
{"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1773
{"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
1774
{"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1775
{"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 },
1776
{"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1777
{"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
1778
{"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
1779
{"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1780
{"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, N54 },
1781
{"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, N54 },
1782
{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
1783
{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 },
1784
{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
1785
{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, I1 },
1786
{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 },
1787
{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, N5 },
1788
{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, I1 }, /* sub 0 */
1789
{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, I1 }, /* subu 0 */
1790
{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, I1 },
1791
{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, I1 },
1792
{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, I5 },
1793
{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
1794
{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
1795
{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
1796
{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I4 },
1797
{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, I4 },
1798
{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, I5 },
1929
/* mtc3 is at the bottom of the table. */
1930
{"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 },
1931
{"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 },
1932
{"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 },
1933
{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
1934
{"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 },
1935
{"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT },
1936
{"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
1937
{"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
1938
{"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
1939
{"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
1940
{"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
1941
{"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
1942
{"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
1943
{"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
1944
{"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 },
1945
{"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
1946
{"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
1947
{"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
1948
{"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
1949
{"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
1950
{"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
1951
{"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
1952
{"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
1953
{"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 },
1954
{"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
1955
{"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
1956
{"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1957
{"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1958
{"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1959
{"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1960
{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
1961
{"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1962
{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55},
1963
{"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 },
1964
{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 },
1965
{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 },
1966
{"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1967
{"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1968
{"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1969
{"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1970
{"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1971
{"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1972
{"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1973
{"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1974
{"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1975
{"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1976
{"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1977
{"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1978
{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 },
1979
{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 },
1980
{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 },
1981
{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 },
1982
{"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
1983
{"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1984
{"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1985
{"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1986
{"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1987
{"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1988
{"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1989
{"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1990
{"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1991
{"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1992
{"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1993
{"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1994
{"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1995
{"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1996
{"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1997
{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
1998
{"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 },
1999
{"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
2000
{"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
2001
{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
2002
{"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 },
2003
{"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
2004
{"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2005
{"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */
2006
{"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */
2007
{"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
2008
{"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
2009
{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 },
2010
{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
2011
{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
2012
{"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
2013
{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
2014
{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
2015
{"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
1799
2016
/* nop is at the start of the table. */
1800
{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1801
{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, I1 },
1802
{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1803
{"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1804
{"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1805
{"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1806
{"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1807
{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, I1 },/*nor d,s,0*/
1808
{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1809
{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, I1 },
1810
{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1811
{"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1812
{"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1813
{"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1814
{"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1815
{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, I1 },
1816
{"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, SB1 },
1817
{"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, SB1 },
1818
{"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, SB1 },
1819
{"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1820
{"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1821
{"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1822
{"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1823
{"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1824
{"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1825
{"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1826
{"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1827
{"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1828
{"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1829
{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
1830
{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
2017
{"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2018
{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 },
2019
{"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2020
{"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2021
{"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2022
{"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2023
{"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2024
{"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/
2025
{"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2026
{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 },
2027
{"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2028
{"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2029
{"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2030
{"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2031
{"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2032
{"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2033
{"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
2034
{"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 },
2035
{"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
2036
{"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2037
{"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2038
{"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2039
{"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2040
{"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2041
{"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2042
{"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2043
{"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2044
{"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2045
{"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2046
{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2047
{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
1831
2048
/* pref and prefx are at the start of the table. */
1832
{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
1833
{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
1834
{"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX|SB1 },
1835
{"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, N54 },
1836
{"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
1837
{"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX|SB1 },
1838
{"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, N54 },
1839
{"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
1840
{"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX|SB1 },
1841
{"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, N54 },
1842
{"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|RD_MACC|FP_D, MX },
1843
{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 },
1844
{"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, SB1 },
1845
{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 },
1846
{"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, M3D },
1847
{"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, M3D },
1848
{"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, M3D },
1849
{"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
1850
{"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
1851
{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
1852
{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 },
1853
{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 },
1854
{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 },
1855
{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 },
1856
{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, I1 },
1857
{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, I1 },
1858
{"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, I33 },
1859
{"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, I33 },
1860
{"rfe", "", 0x42000010, 0xffffffff, 0, I1|T3 },
1861
{"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
1862
{"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 },
1863
{"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
1864
{"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
1865
{"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 },
1866
{"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
1867
{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I1 },
1868
{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I1 },
1869
{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I1 },
1870
{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I1 },
1871
{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, N5|I33 },
1872
{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, N5|I33 },
1873
{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, I33 },
1874
{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, I33 },
1875
{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, I33 },
1876
{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, I33 },
1877
{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, I33 },
1878
{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, I3 },
1879
{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S, I3 },
1880
{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_D, I2 },
1881
{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 },
1882
{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 },
1883
{"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, SB1 },
1884
{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 },
1885
{"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, M3D },
1886
{"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, M3D },
1887
{"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, M3D },
1888
{"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, M3D },
1889
{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
1890
{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, M3D },
1891
{"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
1892
{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX|SB1 },
1893
{"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, N54 },
1894
{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_MACC|RD_T|FP_D, MX },
1895
{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 },
1896
{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 },
1897
{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 },
1898
{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, I2 },
1899
{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I3 },
1900
{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, I3 },
1901
{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, I3 },
1902
{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, I1 },
1903
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, I1 },
1904
{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, G2 },
1905
{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, G2 },
1906
{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, G2 },
1907
{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, I32 },
1908
{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, I32 },
1909
{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
1910
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
1911
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
1912
{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, I2 },
1913
{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, I2 },
1914
{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, I2 },
1915
{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, I2 },
1916
{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, I2 },
1917
{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, I2 },
1918
{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, I1 },
1919
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, I1 },
1920
{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, I3 },
1921
{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, I3 },
1922
{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, I3 },
1923
{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, I3 },
1924
{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 },
1925
{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, I33 },
1926
{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, I33 },
1927
{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, L1 },
1928
{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, L1 },
1929
{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, I1 },
1930
{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, I1 },
1931
{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, I1 },
1932
{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, I1 },
1933
{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, I1 },
1934
{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, I1 },
1935
{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, I1 },
1936
{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, I1 },
1937
{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, I1 },
1938
{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, I1 },
1939
{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, I1 },
1940
{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, I1 },
1941
{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
1942
{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1943
{"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1944
{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
1945
{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1946
{"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1947
{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
1948
{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1949
{"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1950
{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
1951
{"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1952
{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
1953
{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX },
1954
{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1955
{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, I1 },
1956
{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, I1 },
1957
{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, I1 },
1958
{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, I1 },
1959
{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
1960
{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* sllv */
1961
{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, I1 },
1962
{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1963
{"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1964
{"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1965
{"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1966
{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1967
{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, I1 },
1968
{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, I1 },
1969
{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, I1 },
1970
{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1971
{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, I1 },
1972
{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, I1 },
1973
{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, I1 },
1974
{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2 },
1975
{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2 },
1976
{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, SB1 },
1977
{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
1978
{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */
1979
{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 },
1980
{"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
1981
{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 },
1982
{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srlv */
1983
{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, I1 },
1984
{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1985
{"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1986
{"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1987
{"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
2049
{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2050
{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2051
{"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT },
2052
{"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
2053
{"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 },
2054
{"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
2055
{"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
2056
{"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 },
2057
{"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
2058
{"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
2059
{"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 },
2060
{"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
2061
{"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 },
2062
{"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
2063
{"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 },
2064
{"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D },
2065
{"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2066
{"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2067
{"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
2068
{"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2069
{"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2070
{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
2071
{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 },
2072
{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 },
2073
{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
2074
{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 },
2075
{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 },
2076
{"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 },
2077
{"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 },
2078
{"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 },
2079
{"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2080
{"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
2081
{"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2082
{"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2083
{"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
2084
{"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2085
{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 },
2086
{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
2087
{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
2088
{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 },
2089
{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT },
2090
{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT },
2091
{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT },
2092
{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT },
2093
{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT },
2094
{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT },
2095
{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT },
2096
{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
2097
{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
2098
{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
2099
{"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2100
{"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 },
2101
{"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
2102
{"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 },
2103
{"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D },
2104
{"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2105
{"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2106
{"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
2107
{"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2108
{"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2109
{"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2110
{"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
2111
{"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 },
2112
{"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2113
{"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2114
{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 },
2115
{"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 },
2116
{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 },
2117
{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 },
2118
{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 },
2119
{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
2120
{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 },
2121
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 },
2122
{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 },
2123
{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 },
2124
{"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 },
2125
{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 },
2126
{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 },
2127
{"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
2128
{"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
2129
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
2130
{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
2131
{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 },
2132
{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 },
2133
{"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 },
2134
{"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 },
2135
{"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
2136
{"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 },
2137
{"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 },
2138
{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
2139
{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
2140
{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
2141
{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 },
2142
{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4|I33 },
2143
{"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 },
2144
{"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 },
2145
{"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
2146
{"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
2147
{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 },
2148
{"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 },
2149
{"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 },
2150
{"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 },
2151
{"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 },
2152
{"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 },
2153
{"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 },
2154
{"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 },
2155
{"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 },
2156
{"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 },
2157
{"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2158
{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 },
2159
{"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2160
{"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2161
{"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2162
{"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2163
{"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2164
{"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2165
{"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2166
{"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2167
{"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2168
{"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2169
{"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2170
{"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2171
{"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2172
{"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2173
{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 },
2174
{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 },
2175
{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 },
2176
{"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 },
2177
{"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2178
{"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */
2179
{"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 },
2180
{"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2181
{"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2182
{"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2183
{"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2184
{"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2185
{"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 },
2186
{"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2187
{"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2188
{"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2189
{"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 },
2190
{"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 },
2191
{"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 },
2192
{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 },
2193
{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2194
{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
2195
{"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2196
{"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */
2197
{"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 },
2198
{"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2199
{"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2200
{"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */
2201
{"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 },
2202
{"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2203
{"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2204
{"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2205
{"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1988
2206
/* ssnop is at the start of the table. */
1989
{"standby", "", 0x42000021, 0xffffffff, 0, V1 },
1990
{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
1991
{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 },
1992
{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 },
1993
{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 },
1994
{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
1995
{"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1996
{"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
1997
{"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
1998
{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 },
1999
{"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
2000
{"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
2001
{"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
2002
{"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
2003
{"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
2004
{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
2005
{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, I1 },
2006
{"suspend", "", 0x42000022, 0xffffffff, 0, V1 },
2007
{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I5|N55 },
2008
{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, I1 },
2009
{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, I1 },
2010
{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, I1 },
2011
{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, I1 },
2012
{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 },
2013
{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 },
2014
{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 },
2015
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 },
2016
{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, I1 }, /* swc1 */
2017
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, I1 },
2018
{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, I1 },
2019
{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, I1 },
2020
{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, I1 },
2021
{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, I1 },
2022
{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, I1 },
2023
{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I1 },
2024
{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */
2025
{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, I2 }, /* as swl */
2026
{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, I1 },
2027
{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, I1 },
2028
{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, I2 }, /* same */
2029
{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, I2 }, /* as swr */
2030
{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b, I4 },
2031
{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2|G1 },
2032
{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, I2 },
2033
{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, I2 },
2034
{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, I33 },
2035
{"syscall", "", 0x0000000c, 0xffffffff, TRAP, I1 },
2036
{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, I1 },
2037
{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 },
2038
{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
2039
{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
2040
{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* teqi */
2041
{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, I2 },
2042
{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 },
2043
{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
2044
{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
2045
{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgei */
2046
{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, I2 },
2047
{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 },
2048
{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
2049
{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
2050
{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tgeiu */
2051
{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, I2 },
2052
{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, I1 },
2053
{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, I1 },
2054
{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, I1 },
2055
{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, I1 },
2056
{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 },
2057
{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
2058
{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
2059
{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tlti */
2060
{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, I2 },
2061
{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 },
2062
{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
2063
{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
2064
{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tltiu */
2065
{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, I2 },
2066
{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 },
2067
{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, I2 },
2068
{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, I2 },
2069
{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, I2 }, /* tnei */
2070
{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, I2 },
2071
{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, I3 },
2072
{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S, I3 },
2073
{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 },
2074
{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_D, I2 },
2075
{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, I1 },
2076
{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 },
2077
{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, I2 },
2078
{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, I1 },
2079
{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, I3 },
2080
{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, I3 },
2081
{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, I1 },
2082
{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, I1 },
2083
{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, I1 },
2084
{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, I1 },
2085
{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, I1 },
2086
{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, I1 },
2087
{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, I3 },
2088
{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, I3 },
2089
{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, I1 },
2090
{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, I1 },
2091
{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, I1 },
2092
{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, I1 },
2093
{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX|SB1 },
2094
{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, N54 },
2095
{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, WR_MACC|RD_S|FP_D, MX },
2096
{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX|SB1 },
2097
{"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, N54 },
2098
{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, WR_MACC|RD_S|RD_T|FP_D, MX },
2099
{"wait", "", 0x42000020, 0xffffffff, TRAP, I3|I32 },
2100
{"wait", "J", 0x42000020, 0xfe00003f, TRAP, I32|N55 },
2101
{"waiti", "", 0x42000020, 0xffffffff, TRAP, L1 },
2102
{"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, L1 },
2103
{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, I33 },
2104
{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, I33 },
2105
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1 },
2106
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, I1 },
2107
{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX|SB1 },
2108
{"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
2109
{"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, N54 },
2110
{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, N54 },
2111
{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, MX },
2112
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, I1 },
2207
{"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 },
2208
{"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2209
{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 },
2210
{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
2211
{"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
2212
{"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2213
{"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2214
{"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2215
{"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2216
{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2217
{"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2218
{"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2219
{"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2220
{"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2221
{"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2222
{"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2223
{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 },
2224
{"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 },
2225
{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|I33|N55},
2226
{"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2227
{"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 },
2228
{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 },
2229
{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 },
2230
{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
2231
{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
2232
{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
2233
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
2234
{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
2235
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
2236
{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
2237
{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
2238
{"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
2239
{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 },
2240
{"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2241
{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
2242
{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
2243
{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */
2244
{"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2245
{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
2246
{"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
2247
{"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */
2248
{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4|I33 },
2249
{"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 },
2250
{"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 },
2251
{"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 },
2252
{"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 },
2253
{"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 },
2254
{"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 },
2255
{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2256
{"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2257
{"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2258
{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */
2259
{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 },
2260
{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2261
{"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2262
{"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2263
{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */
2264
{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 },
2265
{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2266
{"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2267
{"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2268
{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */
2269
{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 },
2270
{"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 },
2271
{"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 },
2272
{"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 },
2273
{"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 },
2274
{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2275
{"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2276
{"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2277
{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */
2278
{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 },
2279
{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2280
{"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2281
{"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2282
{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */
2283
{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 },
2284
{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2285
{"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2286
{"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2287
{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */
2288
{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 },
2289
{"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
2290
{"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
2291
{"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
2292
{"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
2293
{"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1 },
2294
{"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2295
{"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2296
{"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1 },
2297
{"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 },
2298
{"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 },
2299
{"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 },
2300
{"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 },
2301
{"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 },
2302
{"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 },
2303
{"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 },
2304
{"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 },
2305
{"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 },
2306
{"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 },
2307
{"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 },
2308
{"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
2309
{"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
2310
{"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
2311
{"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 },
2312
{"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 },
2313
{"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX },
2314
{"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2315
{"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 },
2316
{"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2317
{"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3|I32 },
2318
{"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 },
2319
{"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 },
2320
{"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 },
2321
{"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 },
2322
{"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2323
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
2324
{"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2325
{"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2326
{"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2327
{"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2328
{"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2329
{"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2330
{"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 },
2331
{"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 },
2332
2333
/* User Defined Instruction. */
2334
{"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2335
{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2336
{"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2337
{"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2338
{"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2339
{"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2340
{"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2341
{"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2342
{"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2343
{"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2344
{"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2345
{"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2346
{"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2347
{"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2348
{"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2349
{"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2350
{"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2351
{"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2352
{"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2353
{"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2354
{"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2355
{"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2356
{"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2357
{"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2358
{"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2359
{"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2360
{"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2361
{"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2362
{"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2363
{"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2364
{"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2365
{"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2366
{"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2367
{"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2368
{"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2369
{"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2370
{"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2371
{"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2372
{"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2373
{"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2374
{"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2375
{"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2376
{"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2377
{"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2378
{"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2379
{"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2380
{"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2381
{"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2382
{"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2383
{"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2384
{"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2385
{"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2386
{"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2387
{"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2388
{"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2389
{"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2390
{"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2391
{"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2392
{"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2393
{"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2394
{"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2395
{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2396
{"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2397
{"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2113
2398
2114
2399
/* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
2115
2400
instructions so they are here for the latters to take precedence. */
2116
{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, I1 },
2117
{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, I2|T3 },
2118
{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 },
2119
{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 },
2120
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
2121
{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, I1 },
2122
{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, I3 },
2123
{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, I64 },
2124
{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I3 },
2125
{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I64 },
2126
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
2127
{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, I32 },
2128
{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, I33 },
2129
{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, I1 },
2130
{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, I32 },
2131
{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, I33 },
2401
{"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 },
2402
{"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 },
2403
{"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2404
{"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 },
2405
{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 },
2406
{"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 },
2407
{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2408
{"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 },
2409
{"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
2410
{"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
2411
{"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 },
2412
{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 },
2413
{"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 },
2414
{"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
2415
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
2416
{"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 },
2417
{"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 },
2418
{"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 },
2419
{"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 },
2420
{"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 },
2421
{"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 },
2422
{"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 },
2423
{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 },
2424
{"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 },
2425
2426
/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
2427
instructions, so they are here for the latters to take precedence. */
2428
{"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 },
2429
{"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2430
{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 },
2431
{"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2432
{"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
2433
{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
2434
{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 },
2435
{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 },
2436
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
2437
{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 },
2438
{"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
2439
{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
2132
2440
2133
2441
/* No hazard protection on coprocessor instructions--they shouldn't
2134
2442
change the state of the processor and if they do it's up to the
2135
2443
user to put in nops as necessary. These are at the end so that the
2136
2444
disassembler recognizes more specific versions first. */
2137
{"c0", "C", 0x42000000, 0xfe000000, 0, I1 },
2138
{"c1", "C", 0x46000000, 0xfe000000, 0, I1 },
2139
{"c2", "C", 0x4a000000, 0xfe000000, 0, I1 },
2140
{"c3", "C", 0x4e000000, 0xfe000000, 0, I1 },
2141
{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, I1 },
2142
{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, I1 },
2143
{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, I1 },
2144
{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, I1 },
2145
2445
{"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 },
2446
{"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1 },
2447
{"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 },
2448
{"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 },
2449
{"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 },
2450
{"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 },
2451
{"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 },
2452
{"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 },
2146
2453
/* Conflicts with the 4650's "mul" instruction. Nobody's using the
2147
2454
4010 any more, so move this insn out of the way. If the object
2148
2455
format gave us more info, we could do this right. */
2149
{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, L1 },
2456
{"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 },
2457
/* MIPS DSP ASE */
2458
{"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 },
2459
{"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 },
2460
{"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 },
2461
{"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 },
2462
{"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2463
{"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2464
{"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2465
{"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2466
{"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2467
{"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2468
{"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2469
{"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2470
{"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2471
{"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2472
{"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2473
{"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2474
{"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2475
{"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2476
{"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 },
2477
{"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 },
2478
{"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2479
{"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2480
{"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2481
{"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2482
{"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2483
{"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2484
{"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2485
{"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2486
{"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2487
{"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2488
{"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2489
{"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2490
{"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2491
{"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2492
{"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2493
{"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2494
{"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2495
{"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2496
{"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2497
{"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2498
{"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2499
{"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 },
2500
{"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 },
2501
{"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2502
{"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2503
{"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2504
{"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2505
{"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2506
{"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2507
{"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2508
{"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2509
{"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2510
{"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2511
{"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2512
{"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2513
{"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2514
{"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2515
{"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2516
{"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2517
{"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 },
2518
{"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2519
{"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2520
{"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2521
{"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2522
{"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 },
2523
{"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2524
{"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2525
{"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2526
{"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2527
{"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2528
{"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2529
{"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2530
{"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2531
{"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2532
{"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2533
{"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2534
{"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2535
{"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2536
{"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2537
{"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2538
{"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2539
{"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 },
2540
{"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 },
2541
{"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 },
2542
{"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 },
2543
{"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2544
{"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2545
{"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2546
{"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2547
{"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2548
{"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2549
{"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2550
{"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2551
{"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2552
{"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2553
{"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
2554
{"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
2555
{"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 },
2556
{"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
2557
{"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
2558
{"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2559
{"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2560
{"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2561
{"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2562
{"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2563
{"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2564
{"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2565
{"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2566
{"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2567
{"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2568
{"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2569
{"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2570
{"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2571
{"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2572
{"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2573
{"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 },
2574
{"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2575
{"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2576
{"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2577
{"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2578
{"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2579
{"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2580
{"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2581
{"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2582
{"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2583
{"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2584
{"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2585
{"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2586
{"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2587
{"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2588
{"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2589
{"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2590
{"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2591
{"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2592
{"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2593
{"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2594
{"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 },
2595
{"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 },
2596
{"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2597
{"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 },
2598
{"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 },
2599
{"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 },
2600
{"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 },
2601
{"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 },
2602
{"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2603
{"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 },
2604
{"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 },
2605
{"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 },
2606
{"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2607
{"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 },
2608
{"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 },
2609
{"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 },
2610
{"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 },
2611
{"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 },
2612
{"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2613
{"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 },
2614
{"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 },
2615
{"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 },
2616
{"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2617
{"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 },
2618
{"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2619
{"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2620
{"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2621
{"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2622
{"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2623
{"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2624
{"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2625
{"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2626
{"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2627
{"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 },
2628
{"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 },
2629
{"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 },
2630
{"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 },
2631
{"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 },
2632
{"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 },
2633
{"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 },
2634
{"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 },
2635
{"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 },
2636
{"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2637
{"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2638
{"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2639
{"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2640
{"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2641
{"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 },
2642
{"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 },
2643
{"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 },
2644
{"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2645
{"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2646
{"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 },
2647
{"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2648
{"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2649
{"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2650
{"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2651
{"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 },
2652
{"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2653
{"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2654
{"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2655
{"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2656
{"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2657
{"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2658
{"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2659
{"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2660
{"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2661
{"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2662
{"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2663
{"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2664
{"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2665
{"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2666
{"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2667
{"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 },
2668
{"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2669
{"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2670
{"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2671
{"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2672
{"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2673
{"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2674
{"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2675
{"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 },
2676
{"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 },
2677
{"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2678
{"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2679
{"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2680
{"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2681
{"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2682
{"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2683
{"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2684
{"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2685
{"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2686
{"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2687
{"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2688
{"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2689
{"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2690
{"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 },
2691
{"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 },
2692
/* MIPS DSP ASE Rev2 */
2693
{"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 },
2694
{"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2695
{"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2696
{"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2697
{"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2698
{"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2699
{"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 },
2700
{"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 },
2701
{"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2702
{"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2703
{"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2704
{"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2705
{"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2706
{"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2707
{"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2708
{"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2709
{"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2710
{"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2711
{"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2712
{"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2713
{"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2714
{"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2715
{"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2716
{"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 },
2717
{"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 },
2718
{"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2719
{"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2720
{"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 },
2721
{"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2722
{"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2723
{"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2724
{"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2725
{"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2726
{"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2727
{"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2728
{"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2729
{"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2730
{"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2731
{"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2732
{"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2733
{"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2734
{"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2735
{"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2736
{"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2737
{"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2738
{"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2739
{"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2740
/* Move bc0* after mftr and mttr to avoid opcode collision. */
2741
{"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
2742
{"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2743
{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
2744
{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2150
2745
};
2151
2746
2152
2747
#define MIPS_NUM_OPCODES \
2163
2758
/* Mips instructions are at maximum this many bytes long. */
2164
2759
#define INSNLEN 4
2165
2760
2166
static void set_default_mips_dis_options
2167
PARAMS ((struct disassemble_info *));
2168
static void parse_mips_dis_option
2169
PARAMS ((const char *, unsigned int));
2170
static void parse_mips_dis_options
2171
PARAMS ((const char *));
2172
static int _print_insn_mips
2173
PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian));
2174
static int print_insn_mips
2175
PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *));
2176
static void print_insn_args
2177
PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *));
2178
#if 0
2179
static int print_insn_mips16
2180
PARAMS ((bfd_vma, struct disassemble_info *));
2181
#endif
2182
#if 0
2183
static int is_newabi
2184
PARAMS ((Elf32_Ehdr *));
2185
#endif
2186
#if 0
2187
static void print_mips16_insn_arg
2188
PARAMS ((int, const struct mips_opcode *, int, bfd_boolean, int, bfd_vma,
2189
struct disassemble_info *));
2190
#endif
2191
2761
2192
2762
/* FIXME: These should be shared with gdb somehow. */
2193
2763
2194
struct mips_cp0sel_name {
2195
unsigned int cp0reg;
2196
unsigned int sel;
2197
const char * const name;
2198
};
2199
2200
/* The mips16 register names. */
2201
static const char * const mips16_reg_names[] = {
2202
"s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3"
2203
};
2204
2205
static const char * const mips_gpr_names_numeric[32] = {
2764
struct mips_cp0sel_name
2765
{
2766
unsigned int cp0reg;
2767
unsigned int sel;
2768
const char * const name;
2769
};
2770
2771
/* The mips16 registers. */
2772
static const unsigned int mips16_to_32_reg_map[] =
2773
{
2774
16, 17, 2, 3, 4, 5, 6, 7
2775
};
2776
2777
#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
2778
2779
2780
static const char * const mips_gpr_names_numeric[32] =
2781
{
2206
2782
"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
2207
2783
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
2208
2784
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
2209
2785
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
2210
2786
};
2211
2787
2212
static const char * const mips_gpr_names_oldabi[32] = {
2788
static const char * const mips_gpr_names_oldabi[32] =
2789
{
2213
2790
"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
2214
2791
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
2215
2792
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2216
2793
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
2217
2794
};
2218
2795
2219
static const char * const mips_gpr_names_newabi[32] = {
2796
static const char * const mips_gpr_names_newabi[32] =
2797
{
2220
2798
"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
2221
2799
"a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
2222
2800
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2223
2801
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
2224
2802
};
2225
2803
2226
static const char * const mips_fpr_names_numeric[32] = {
2804
static const char * const mips_fpr_names_numeric[32] =
2805
{
2227
2806
"$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
2228
2807
"$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
2229
2808
"$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
2230
2809
"$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
2231
2810
};
2232
2811
2233
static const char * const mips_fpr_names_32[32] = {
2812
static const char * const mips_fpr_names_32[32] =
2813
{
2234
2814
"fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
2235
2815
"ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
2236
2816
"ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
2237
2817
"fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
2238
2818
};
2239
2819
2240
static const char * const mips_fpr_names_n32[32] = {
2820
static const char * const mips_fpr_names_n32[32] =
2821
{
2241
2822
"fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
2242
2823
"ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
2243
2824
"fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
2244
2825
"fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
2245
2826
};
2246
2827
2247
static const char * const mips_fpr_names_64[32] = {
2828
static const char * const mips_fpr_names_64[32] =
2829
{
2248
2830
"fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
2249
2831
"ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
2250
2832
"fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
2251
2833
"fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
2252
2834
};
2253
2835
2254
static const char * const mips_cp0_names_numeric[32] = {
2836
static const char * const mips_cp0_names_numeric[32] =
2837
{
2255
2838
"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
2256
2839
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
2257
2840
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
2258
2841
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
2259
2842
};
2260
2843
2261
static const char * const mips_cp0_names_mips3264[32] = {
2844
static const char * const mips_cp0_names_mips3264[32] =
2845
{
2262
2846
"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
2263
2847
"c0_context", "c0_pagemask", "c0_wired", "$7",
2264
2848
"c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
2269
2853
"c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
2270
2854
};
2271
2855
2272
static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = {
2856
static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
2857
{
2858
{ 4, 1, "c0_contextconfig" },
2859
{ 0, 1, "c0_mvpcontrol" },
2860
{ 0, 2, "c0_mvpconf0" },
2861
{ 0, 3, "c0_mvpconf1" },
2862
{ 1, 1, "c0_vpecontrol" },
2863
{ 1, 2, "c0_vpeconf0" },
2864
{ 1, 3, "c0_vpeconf1" },
2865
{ 1, 4, "c0_yqmask" },
2866
{ 1, 5, "c0_vpeschedule" },
2867
{ 1, 6, "c0_vpeschefback" },
2868
{ 2, 1, "c0_tcstatus" },
2869
{ 2, 2, "c0_tcbind" },
2870
{ 2, 3, "c0_tcrestart" },
2871
{ 2, 4, "c0_tchalt" },
2872
{ 2, 5, "c0_tccontext" },
2873
{ 2, 6, "c0_tcschedule" },
2874
{ 2, 7, "c0_tcschefback" },
2875
{ 5, 1, "c0_pagegrain" },
2876
{ 6, 1, "c0_srsconf0" },
2877
{ 6, 2, "c0_srsconf1" },
2878
{ 6, 3, "c0_srsconf2" },
2879
{ 6, 4, "c0_srsconf3" },
2880
{ 6, 5, "c0_srsconf4" },
2881
{ 12, 1, "c0_intctl" },
2882
{ 12, 2, "c0_srsctl" },
2883
{ 12, 3, "c0_srsmap" },
2884
{ 15, 1, "c0_ebase" },
2273
2885
{ 16, 1, "c0_config1" },
2274
2886
{ 16, 2, "c0_config2" },
2275
2887
{ 16, 3, "c0_config3" },
2287
2899
{ 19, 5, "c0_watchhi,5" },
2288
2900
{ 19, 6, "c0_watchhi,6" },
2289
2901
{ 19, 7, "c0_watchhi,7" },
2902
{ 23, 1, "c0_tracecontrol" },
2903
{ 23, 2, "c0_tracecontrol2" },
2904
{ 23, 3, "c0_usertracedata" },
2905
{ 23, 4, "c0_tracebpc" },
2290
2906
{ 25, 1, "c0_perfcnt,1" },
2291
2907
{ 25, 2, "c0_perfcnt,2" },
2292
2908
{ 25, 3, "c0_perfcnt,3" },
2298
2914
{ 27, 2, "c0_cacheerr,2" },
2299
2915
{ 27, 3, "c0_cacheerr,3" },
2300
2916
{ 28, 1, "c0_datalo" },
2301
{ 29, 1, "c0_datahi" }
2917
{ 28, 2, "c0_taglo1" },
2918
{ 28, 3, "c0_datalo1" },
2919
{ 28, 4, "c0_taglo2" },
2920
{ 28, 5, "c0_datalo2" },
2921
{ 28, 6, "c0_taglo3" },
2922
{ 28, 7, "c0_datalo3" },
2923
{ 29, 1, "c0_datahi" },
2924
{ 29, 2, "c0_taghi1" },
2925
{ 29, 3, "c0_datahi1" },
2926
{ 29, 4, "c0_taghi2" },
2927
{ 29, 5, "c0_datahi2" },
2928
{ 29, 6, "c0_taghi3" },
2929
{ 29, 7, "c0_datahi3" },
2302
2930
};
2303
2931
2304
static const char * const mips_cp0_names_mips3264r2[32] = {
2932
static const char * const mips_cp0_names_mips3264r2[32] =
2933
{
2305
2934
"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
2306
2935
"c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
2307
2936
"c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
2312
2941
"c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
2313
2942
};
2314
2943
2315
static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = {
2944
static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
2945
{
2316
2946
{ 4, 1, "c0_contextconfig" },
2317
2947
{ 5, 1, "c0_pagegrain" },
2318
2948
{ 12, 1, "c0_intctl" },
2367
2997
};
2368
2998
2369
2999
/* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
2370
static const char * const mips_cp0_names_sb1[32] = {
3000
static const char * const mips_cp0_names_sb1[32] =
3001
{
2371
3002
"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
2372
3003
"c0_context", "c0_pagemask", "c0_wired", "$7",
2373
3004
"c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
2378
3009
"c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
2379
3010
};
2380
3011
2381
static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] = {
3012
static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
3013
{
2382
3014
{ 16, 1, "c0_config1" },
2383
3015
{ 18, 1, "c0_watchlo,1" },
2384
3016
{ 19, 1, "c0_watchhi,1" },
2402
3034
{ 29, 3, "c0_datahi_d" },
2403
3035
};
2404
3036
2405
static const char * const mips_hwr_names_numeric[32] = {
3037
static const char * const mips_hwr_names_numeric[32] =
3038
{
2406
3039
"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
2407
3040
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
2408
3041
"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
2409
3042
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
2410
3043
};
2411
3044
2412
static const char * const mips_hwr_names_mips3264r2[32] = {
3045
static const char * const mips_hwr_names_mips3264r2[32] =
3046
{
2413
3047
"hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
2414
3048
"$4", "$5", "$6", "$7",
2415
3049
"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
2417
3051
"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
2418
3052
};
2419
3053
2420
struct mips_abi_choice {
3054
struct mips_abi_choice
3055
{
2421
3056
const char *name;
2422
3057
const char * const *gpr_names;
2423
3058
const char * const *fpr_names;
2424
3059
};
2425
3060
2426
struct mips_abi_choice mips_abi_choices[] = {
3061
struct mips_abi_choice mips_abi_choices[] =
3062
{
2427
3063
{ "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
2428
3064
{ "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
2429
3065
{ "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
2430
3066
{ "64", mips_gpr_names_newabi, mips_fpr_names_64 },
2431
3067
};
2432
3068
2433
struct mips_arch_choice {
3069
struct mips_arch_choice
3070
{
2434
3071
const char *name;
2435
3072
int bfd_mach_valid;
2436
3073
unsigned long bfd_mach;
2459
3096
#define bfd_mach_mips6000 6000
2460
3097
#define bfd_mach_mips7000 7000
2461
3098
#define bfd_mach_mips8000 8000
3099
#define bfd_mach_mips9000 9000
2462
3100
#define bfd_mach_mips10000 10000
2463
3101
#define bfd_mach_mips12000 12000
2464
3102
#define bfd_mach_mips16 16
2471
3109
2472
3110
#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
2473
3111
2474
const struct mips_arch_choice mips_arch_choices[] = {
3112
const struct mips_arch_choice mips_arch_choices[] =
3113
{
2475
3114
{ "numeric", 0, 0, 0, 0,
2476
3115
mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
2477
3116
2524
3163
MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
2525
3164
page 1. */
2526
3165
{ "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
2527
ISA_MIPS32 | INSN_MIPS16,
3166
ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
2528
3167
mips_cp0_names_mips3264,
2529
3168
mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
2530
3169
mips_hwr_names_numeric },
2531
3170
2532
3171
{ "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
2533
ISA_MIPS32R2 | INSN_MIPS16,
3172
(ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
3173
| INSN_MIPS3D | INSN_MT),
2534
3174
mips_cp0_names_mips3264r2,
2535
3175
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
2536
3176
mips_hwr_names_mips3264r2 },
2543
3183
mips_hwr_names_numeric },
2544
3184
2545
3185
{ "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
2546
ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
3186
(ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
3187
| INSN_DSP64 | INSN_MT | INSN_MDMX),
2547
3188
mips_cp0_names_mips3264r2,
2548
3189
mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
2549
3190
mips_hwr_names_mips3264r2 },
2572
3213
static int mips_cp0sel_names_len;
2573
3214
static const char * const *mips_hwr_names;
2574
3215
2575
static const struct mips_abi_choice *choose_abi_by_name
2576
PARAMS ((const char *, unsigned int));
2577
static const struct mips_arch_choice *choose_arch_by_name
2578
PARAMS ((const char *, unsigned int));
2579
static const struct mips_arch_choice *choose_arch_by_number
2580
PARAMS ((unsigned long));
2581
static const struct mips_cp0sel_name *lookup_mips_cp0sel_name
2582
PARAMS ((const struct mips_cp0sel_name *, unsigned int, unsigned int,
2583
unsigned int));
3216
/* Other options */
3217
static int no_aliases; /* If set disassemble as most general inst. */
2584
3218
2585
3219
static const struct mips_abi_choice *
2586
choose_abi_by_name (name, namelen)
2587
const char *name;
2588
unsigned int namelen;
3220
choose_abi_by_name (const char *name, unsigned int namelen)
2589
3221
{
2590
3222
const struct mips_abi_choice *c;
2591
3223
unsigned int i;
2592
3224
2593
3225
for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
2594
{
2595
if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
2596
&& strlen (mips_abi_choices[i].name) == namelen)
2597
c = &mips_abi_choices[i];
2598
}
3226
if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
3227
&& strlen (mips_abi_choices[i].name) == namelen)
3228
c = &mips_abi_choices[i];
3229
2599
3230
return c;
2600
3231
}
2601
3232
2602
3233
static const struct mips_arch_choice *
2603
choose_arch_by_name (name, namelen)
2604
const char *name;
2605
unsigned int namelen;
3234
choose_arch_by_name (const char *name, unsigned int namelen)
2606
3235
{
2607
3236
const struct mips_arch_choice *c = NULL;
2608
3237
unsigned int i;
2609
3238
2610
3239
for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
2611
{
2612
if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
2613
&& strlen (mips_arch_choices[i].name) == namelen)
2614
c = &mips_arch_choices[i];
2615
}
3240
if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
3241
&& strlen (mips_arch_choices[i].name) == namelen)
3242
c = &mips_arch_choices[i];
3243
2616
3244
return c;
2617
3245
}
2618
3246
2619
3247
static const struct mips_arch_choice *
2620
choose_arch_by_number (mach)
2621
unsigned long mach;
3248
choose_arch_by_number (unsigned long mach)
2622
3249
{
2623
3250
static unsigned long hint_bfd_mach;
2624
3251
static const struct mips_arch_choice *hint_arch_choice;
2646
3273
}
2647
3274
2648
3275
void
2649
set_default_mips_dis_options (info)
2650
struct disassemble_info *info;
3276
set_default_mips_dis_options (struct disassemble_info *info)
2651
3277
{
2652
3278
const struct mips_arch_choice *chosen_arch;
2653
3279
2661
3287
mips_cp0sel_names = NULL;
2662
3288
mips_cp0sel_names_len = 0;
2663
3289
mips_hwr_names = mips_hwr_names_numeric;
3290
no_aliases = 0;
2664
3291
2665
3292
/* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
2666
3293
#if 0
2788
3415
/* Invalid option. */
2789
3416
}
2790
3417
2791
void
2792
parse_mips_dis_options (options)
2793
const char *options;
3418
static void
3419
parse_mips_dis_options (const char *options)
2794
3420
{
2795
3421
const char *option_end;
2796
3422
2820
3446
}
2821
3447
2822
3448
static const struct mips_cp0sel_name *
2823
lookup_mips_cp0sel_name(names, len, cp0reg, sel)
2824
const struct mips_cp0sel_name *names;
2825
unsigned int len, cp0reg, sel;
3449
lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
3450
unsigned int len,
3451
unsigned int cp0reg,
3452
unsigned int sel)
2826
3453
{
2827
3454
unsigned int i;
2828
3455
2835
3462
/* Print insn arguments for 32/64-bit code. */
2836
3463
2837
3464
static void
2838
print_insn_args (d, l, pc, info)
2839
const char *d;
2840
register unsigned long int l;
2841
bfd_vma pc;
2842
struct disassemble_info *info;
3465
print_insn_args (const char *d,
3466
register unsigned long int l,
3467
bfd_vma pc,
3468
struct disassemble_info *info,
3469
const struct mips_opcode *opp)
2843
3470
{
2844
3471
int op, delta;
2845
3472
unsigned int lsb, msb, msbd;
2873
3500
lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
2874
3501
(*info->fprintf_func) (info->stream, "0x%x", lsb);
2875
3502
break;
2876
3503
2877
3504
case 'B':
2878
3505
msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
2879
3506
(*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
2880
3507
break;
2881
3508
3509
case '1':
3510
(*info->fprintf_func) (info->stream, "0x%lx",
3511
(l >> OP_SH_UDI1) & OP_MASK_UDI1);
3512
break;
3513
3514
case '2':
3515
(*info->fprintf_func) (info->stream, "0x%lx",
3516
(l >> OP_SH_UDI2) & OP_MASK_UDI2);
3517
break;
3518
3519
case '3':
3520
(*info->fprintf_func) (info->stream, "0x%lx",
3521
(l >> OP_SH_UDI3) & OP_MASK_UDI3);
3522
break;
3523
3524
case '4':
3525
(*info->fprintf_func) (info->stream, "0x%lx",
3526
(l >> OP_SH_UDI4) & OP_MASK_UDI4);
3527
break;
3528
2882
3529
case 'C':
2883
3530
case 'H':
2884
3531
msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
2922
3569
(*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
2923
3570
break;
2924
3571
3572
case 't': /* Coprocessor 0 reg name */
3573
(*info->fprintf_func) (info->stream, "%s",
3574
mips_cp0_names[(l >> OP_SH_RT) &
3575
OP_MASK_RT]);
3576
break;
3577
3578
case 'T': /* Coprocessor 0 reg name */
3579
{
3580
const struct mips_cp0sel_name *n;
3581
unsigned int cp0reg, sel;
3582
3583
cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
3584
sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
3585
3586
/* CP0 register including 'sel' code for mftc0, to be
3587
printed textually if known. If not known, print both
3588
CP0 register name and sel numerically since CP0 register
3589
with sel 0 may have a name unrelated to register being
3590
printed. */
3591
n = lookup_mips_cp0sel_name(mips_cp0sel_names,
3592
mips_cp0sel_names_len, cp0reg, sel);
3593
if (n != NULL)
3594
(*info->fprintf_func) (info->stream, "%s", n->name);
3595
else
3596
(*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
3597
break;
3598
}
3599
2925
3600
default:
2926
3601
/* xgettext:c-format */
2927
3602
(*info->fprintf_func) (info->stream,
2931
3606
}
2932
3607
break;
2933
3608
3609
case '2':
3610
(*info->fprintf_func) (info->stream, "0x%lx",
3611
(l >> OP_SH_BP) & OP_MASK_BP);
3612
break;
3613
3614
case '3':
3615
(*info->fprintf_func) (info->stream, "0x%lx",
3616
(l >> OP_SH_SA3) & OP_MASK_SA3);
3617
break;
3618
3619
case '4':
3620
(*info->fprintf_func) (info->stream, "0x%lx",
3621
(l >> OP_SH_SA4) & OP_MASK_SA4);
3622
break;
3623
3624
case '5':
3625
(*info->fprintf_func) (info->stream, "0x%lx",
3626
(l >> OP_SH_IMM8) & OP_MASK_IMM8);
3627
break;
3628
3629
case '6':
3630
(*info->fprintf_func) (info->stream, "0x%lx",
3631
(l >> OP_SH_RS) & OP_MASK_RS);
3632
break;
3633
3634
case '7':
3635
(*info->fprintf_func) (info->stream, "$ac%ld",
3636
(l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
3637
break;
3638
3639
case '8':
3640
(*info->fprintf_func) (info->stream, "0x%lx",
3641
(l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
3642
break;
3643
3644
case '9':
3645
(*info->fprintf_func) (info->stream, "$ac%ld",
3646
(l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
3647
break;
3648
3649
case '0': /* dsp 6-bit signed immediate in bit 20 */
3650
delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
3651
if (delta & 0x20) /* test sign bit */
3652
delta |= ~OP_MASK_DSPSFT;
3653
(*info->fprintf_func) (info->stream, "%d", delta);
3654
break;
3655
3656
case ':': /* dsp 7-bit signed immediate in bit 19 */
3657
delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
3658
if (delta & 0x40) /* test sign bit */
3659
delta |= ~OP_MASK_DSPSFT_7;
3660
(*info->fprintf_func) (info->stream, "%d", delta);
3661
break;
3662
3663
case '\'':
3664
(*info->fprintf_func) (info->stream, "0x%lx",
3665
(l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
3666
break;
3667
3668
case '@': /* dsp 10-bit signed immediate in bit 16 */
3669
delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
3670
if (delta & 0x200) /* test sign bit */
3671
delta |= ~OP_MASK_IMM10;
3672
(*info->fprintf_func) (info->stream, "%d", delta);
3673
break;
3674
3675
case '!':
3676
(*info->fprintf_func) (info->stream, "%ld",
3677
(l >> OP_SH_MT_U) & OP_MASK_MT_U);
3678
break;
3679
3680
case '$':
3681
(*info->fprintf_func) (info->stream, "%ld",
3682
(l >> OP_SH_MT_H) & OP_MASK_MT_H);
3683
break;
3684
3685
case '*':
3686
(*info->fprintf_func) (info->stream, "$ac%ld",
3687
(l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
3688
break;
3689
3690
case '&':
3691
(*info->fprintf_func) (info->stream, "$ac%ld",
3692
(l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
3693
break;
3694
3695
case 'g':
3696
/* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
3697
(*info->fprintf_func) (info->stream, "$%ld",
3698
(l >> OP_SH_RD) & OP_MASK_RD);
3699
break;
3700
2934
3701
case 's':
2935
3702
case 'b':
2936
3703
case 'r':
2947
3714
2948
3715
case 'i':
2949
3716
case 'u':
2950
(*info->fprintf_func) (info->stream, "0x%x",
3717
(*info->fprintf_func) (info->stream, "0x%lx",
2951
3718
(l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
2952
3719
break;
2953
3720
2975
3742
case 'a':
2976
3743
info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
2977
3744
| (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
3745
/* For gdb disassembler, force odd address on jalx. */
3746
if (info->flavour == bfd_target_unknown_flavour
3747
&& strcmp (opp->name, "jalx") == 0)
3748
info->target |= 1;
2978
3749
(*info->print_address_func) (info->target, info);
2979
3750
break;
2980
3751
3021
3792
break;
3022
3793
3023
3794
case '<':
3024
(*info->fprintf_func) (info->stream, "0x%x",
3795
(*info->fprintf_func) (info->stream, "0x%lx",
3025
3796
(l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
3026
3797
break;
3027
3798
3028
3799
case 'c':
3029
(*info->fprintf_func) (info->stream, "0x%x",
3800
(*info->fprintf_func) (info->stream, "0x%lx",
3030
3801
(l >> OP_SH_CODE) & OP_MASK_CODE);
3031
3802
break;
3032
3803
3033
3804
case 'q':
3034
(*info->fprintf_func) (info->stream, "0x%x",
3805
(*info->fprintf_func) (info->stream, "0x%lx",
3035
3806
(l >> OP_SH_CODE2) & OP_MASK_CODE2);
3036
3807
break;
3037
3808
3038
3809
case 'C':
3039
(*info->fprintf_func) (info->stream, "0x%x",
3810
(*info->fprintf_func) (info->stream, "0x%lx",
3040
3811
(l >> OP_SH_COPZ) & OP_MASK_COPZ);
3041
3812
break;
3042
3813
3043
3814
case 'B':
3044
(*info->fprintf_func) (info->stream, "0x%x",
3815
(*info->fprintf_func) (info->stream, "0x%lx",
3816
3045
3817
(l >> OP_SH_CODE20) & OP_MASK_CODE20);
3046
3818
break;
3047
3819
3048
3820
case 'J':
3049
(*info->fprintf_func) (info->stream, "0x%x",
3821
(*info->fprintf_func) (info->stream, "0x%lx",
3050
3822
(l >> OP_SH_CODE19) & OP_MASK_CODE19);
3051
3823
break;
3052
3824
3080
3852
'T' format. Therefore, until we gain understanding of
3081
3853
cp2 register names, we can simply print the register
3082
3854
numbers. */
3083
(*info->fprintf_func) (info->stream, "$%d",
3855
(*info->fprintf_func) (info->stream, "$%ld",
3084
3856
(l >> OP_SH_RT) & OP_MASK_RT);
3085
3857
break;
3086
3858
3094
3866
(*info->fprintf_func) (info->stream, "%s",
3095
3867
mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3096
3868
else
3097
(*info->fprintf_func) (info->stream, "$%d",
3869
(*info->fprintf_func) (info->stream, "$%ld",
3098
3870
(l >> OP_SH_RD) & OP_MASK_RD);
3099
3871
break;
3100
3872
3104
3876
break;
3105
3877
3106
3878
case 'N':
3107
(*info->fprintf_func) (info->stream, "$fcc%d",
3879
(*info->fprintf_func) (info->stream,
3880
((opp->pinfo & (FP_D | FP_S)) != 0
3881
? "$fcc%ld" : "$cc%ld"),
3108
3882
(l >> OP_SH_BCC) & OP_MASK_BCC);
3109
3883
break;
3110
3884
3111
3885
case 'M':
3112
(*info->fprintf_func) (info->stream, "$fcc%d",
3886
(*info->fprintf_func) (info->stream, "$fcc%ld",
3113
3887
(l >> OP_SH_CCC) & OP_MASK_CCC);
3114
3888
break;
3115
3889
3116
3890
case 'P':
3117
(*info->fprintf_func) (info->stream, "%d",
3891
(*info->fprintf_func) (info->stream, "%ld",
3118
3892
(l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
3119
3893
break;
3120
3894
3121
3895
case 'e':
3122
(*info->fprintf_func) (info->stream, "%d",
3896
(*info->fprintf_func) (info->stream, "%ld",
3123
3897
(l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
3124
3898
break;
3125
3899
3126
3900
case '%':
3127
(*info->fprintf_func) (info->stream, "%d",
3901
(*info->fprintf_func) (info->stream, "%ld",
3128
3902
(l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
3129
3903
break;
3130
3904
3131
3905
case 'H':
3132
(*info->fprintf_func) (info->stream, "%d",
3906
(*info->fprintf_func) (info->stream, "%ld",
3133
3907
(l >> OP_SH_SEL) & OP_MASK_SEL);
3134
3908
break;
3135
3909
3136
3910
case 'O':
3137
(*info->fprintf_func) (info->stream, "%d",
3911
(*info->fprintf_func) (info->stream, "%ld",
3138
3912
(l >> OP_SH_ALN) & OP_MASK_ALN);
3139
3913
break;
3140
3914
3141
3915
case 'Q':
3142
3916
{
3143
3917
unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
3918
3144
3919
if ((vsel & 0x10) == 0)
3145
3920
{
3146
3921
int fmt;
3922
3147
3923
vsel &= 0x0f;
3148
3924
for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
3149
3925
if ((vsel & 1) == 0)
3150
3926
break;
3151
(*info->fprintf_func) (info->stream, "$v%d[%d]",
3927
(*info->fprintf_func) (info->stream, "$v%ld[%d]",
3152
3928
(l >> OP_SH_FT) & OP_MASK_FT,
3153
3929
vsel >> 1);
3154
3930
}
3155
3931
else if ((vsel & 0x08) == 0)
3156
3932
{
3157
(*info->fprintf_func) (info->stream, "$v%d",
3933
(*info->fprintf_func) (info->stream, "$v%ld",
3158
3934
(l >> OP_SH_FT) & OP_MASK_FT);
3159
3935
}
3160
3936
else
3161
3937
{
3162
(*info->fprintf_func) (info->stream, "0x%x",
3938
(*info->fprintf_func) (info->stream, "0x%lx",
3163
3939
(l >> OP_SH_FT) & OP_MASK_FT);
3164
3940
}
3165
3941
}
3166
3942
break;
3167
3943
3168
3944
case 'X':
3169
(*info->fprintf_func) (info->stream, "$v%d",
3945
(*info->fprintf_func) (info->stream, "$v%ld",
3170
3946
(l >> OP_SH_FD) & OP_MASK_FD);
3171
3947
break;
3172
3948
3173
3949
case 'Y':
3174
(*info->fprintf_func) (info->stream, "$v%d",
3950
(*info->fprintf_func) (info->stream, "$v%ld",
3175
3951
(l >> OP_SH_FS) & OP_MASK_FS);
3176
3952
break;
3177
3953
3178
3954
case 'Z':
3179
(*info->fprintf_func) (info->stream, "$v%d",
3955
(*info->fprintf_func) (info->stream, "$v%ld",
3180
3956
(l >> OP_SH_FT) & OP_MASK_FT);
3181
3957
break;
3182
3958
3214
3990
this is little-endian code. */
3215
3991
3216
3992
static int
3217
print_insn_mips (memaddr, word, info)
3218
bfd_vma memaddr;
3219
unsigned long int word;
3220
struct disassemble_info *info;
3993
print_insn_mips (bfd_vma memaddr,
3994
unsigned long int word,
3995
struct disassemble_info *info)
3221
3996
{
3222
register const struct mips_opcode *op;
3997
const struct mips_opcode *op;
3223
3998
static bfd_boolean init = 0;
3224
3999
static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
3225
4000
3232
4007
{
3233
4008
for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
3234
4009
{
3235
if (op->pinfo == INSN_MACRO)
4010
if (op->pinfo == INSN_MACRO
4011
|| (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
3236
4012
continue;
3237
4013
if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
3238
4014
{
3259
4035
{
3260
4036
for (; op < &mips_opcodes[NUMOPCODES]; op++)
3261
4037
{
3262
if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match)
4038
if (op->pinfo != INSN_MACRO
4039
&& !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4040
&& (word & op->mask) == op->match)
3263
4041
{
3264
register const char *d;
4042
const char *d;
3265
4043
3266
4044
/* We always allow to disassemble the jalx instruction. */
3267
4045
if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
3296
4074
if (d != NULL && *d != '\0')
3297
4075
{
3298
4076
(*info->fprintf_func) (info->stream, "\t");
3299
print_insn_args (d, word, memaddr, info);
4077
print_insn_args (d, word, memaddr, info, op);
3300
4078
}
3301
4079
3302
4080
return INSNLEN;
3306
4084
3307
4085
/* Handle undefined instructions. */
3308
4086
info->insn_type = dis_noninsn;
3309
(*info->fprintf_func) (info->stream, "0x%x", word);
4087
(*info->fprintf_func) (info->stream, "0x%lx", word);
3310
4088
return INSNLEN;
3311
4089
}
3312
4090
3317
4095
this works. Otherwise, we need a clue. Sometimes. */
3318
4096
3319
4097
static int
3320
_print_insn_mips (memaddr, info, endianness)
3321
bfd_vma memaddr;
3322
struct disassemble_info *info;
3323
enum bfd_endian endianness;
4098
_print_insn_mips (bfd_vma memaddr,
4099
struct disassemble_info *info,
4100
enum bfd_endian endianness)
3324
4101
{
3325
4102
bfd_byte buffer[INSNLEN];
3326
4103
int status;
3366
4143
}
3367
4144
3368
4145
int
3369
print_insn_big_mips (memaddr, info)
3370
bfd_vma memaddr;
3371
struct disassemble_info *info;
4146
print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
3372
4147
{
3373
4148
return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
3374
4149
}
3375
4150
3376
4151
int
3377
print_insn_little_mips (memaddr, info)
3378
bfd_vma memaddr;
3379
struct disassemble_info *info;
4152
print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
3380
4153
{
3381
4154
return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
3382
4155
}
3384
4157
/* Disassemble mips16 instructions. */
3385
4158
#if 0
3386
4159
static int
3387
print_insn_mips16 (memaddr, info)
3388
bfd_vma memaddr;
3389
struct disassemble_info *info;
4160
print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
3390
4161
{
3391
4162
int status;
3392
4163
bfd_byte buffer[2];
3459
4230
opend = mips16_opcodes + bfd_mips16_num_opcodes;
3460
4231
for (op = mips16_opcodes; op < opend; op++)
3461
4232
{
3462
if (op->pinfo != INSN_MACRO && (insn & op->mask) == op->match)
4233
if (op->pinfo != INSN_MACRO
4234
&& !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4235
&& (insn & op->mask) == op->match)
3463
4236
{
3464
4237
const char *s;
3465
4238
3540
4313
/* Disassemble an operand for a mips16 instruction. */
3541
4314
3542
4315
static void
3543
print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info)
3544
char type;
3545
const struct mips_opcode *op;
3546
int l;
3547
bfd_boolean use_extend;
3548
int extend;
3549
bfd_vma memaddr;
3550
struct disassemble_info *info;
4316
print_mips16_insn_arg (char type,
4317
const struct mips_opcode *op,
4318
int l,
4319
bfd_boolean use_extend,
4320
int extend,
4321
bfd_vma memaddr,
4322
struct disassemble_info *info)
3551
4323
{
3552
4324
switch (type)
3553
4325
{
3560
4332
case 'y':
3561
4333
case 'w':
3562
4334
(*info->fprintf_func) (info->stream, "%s",
3563
mips16_reg_names[((l >> MIPS16OP_SH_RY)
3564
& MIPS16OP_MASK_RY)]);
4335
mips16_reg_names(((l >> MIPS16OP_SH_RY)
4336
& MIPS16OP_MASK_RY)));
3565
4337
break;
3566
4338
3567
4339
case 'x':
3568
4340
case 'v':
3569
4341
(*info->fprintf_func) (info->stream, "%s",
3570
mips16_reg_names[((l >> MIPS16OP_SH_RX)
3571
& MIPS16OP_MASK_RX)]);
4342
mips16_reg_names(((l >> MIPS16OP_SH_RX)
4343
& MIPS16OP_MASK_RX)));
3572
4344
break;
3573
4345
3574
4346
case 'z':
3575
4347
(*info->fprintf_func) (info->stream, "%s",
3576
mips16_reg_names[((l >> MIPS16OP_SH_RZ)
3577
& MIPS16OP_MASK_RZ)]);
4348
mips16_reg_names(((l >> MIPS16OP_SH_RZ)
4349
& MIPS16OP_MASK_RZ)));
3578
4350
break;
3579
4351
3580
4352
case 'Z':
3581
4353
(*info->fprintf_func) (info->stream, "%s",
3582
mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z)
3583
& MIPS16OP_MASK_MOVE32Z)]);
4354
mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
4355
& MIPS16OP_MASK_MOVE32Z)));
3584
4356
break;
3585
4357
3586
4358
case '0':
3862
4634
}
3863
4635
}
3864
4636
info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
4637
if (pcrel && branch
4638
&& info->flavour == bfd_target_unknown_flavour)
4639
/* For gdb disassembler, maintain odd address. */
4640
info->target |= 1;
3865
4641
(*info->print_address_func) (info->target, info);
3866
4642
}
3867
4643
}
3868
4644
break;
3869
4645
3870
4646
case 'a':
3871
if (! use_extend)
3872
extend = 0;
3873
l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
4647
{
4648
int jalx = l & 0x400;
4649
4650
if (! use_extend)
4651
extend = 0;
4652
l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
4653
if (!jalx && info->flavour == bfd_target_unknown_flavour)
4654
/* For gdb disassembler, maintain odd address. */
4655
l |= 1;
4656
}
3874
4657
info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
3875
4658
(*info->print_address_func) (info->target, info);
3876
4659
info->insn_type = dis_jsr;
3933
4716
}
3934
4717
break;
3935
4718
4719
case 'm':
4720
case 'M':
4721
/* MIPS16e save/restore. */
4722
{
4723
int need_comma = 0;
4724
int amask, args, statics;
4725
int nsreg, smask;
4726
int framesz;
4727
int i, j;
4728
4729
l = l & 0x7f;
4730
if (use_extend)
4731
l |= extend << 16;
4732
4733
amask = (l >> 16) & 0xf;
4734
if (amask == MIPS16_ALL_ARGS)
4735
{
4736
args = 4;
4737
statics = 0;
4738
}
4739
else if (amask == MIPS16_ALL_STATICS)
4740
{
4741
args = 0;
4742
statics = 4;
4743
}
4744
else
4745
{
4746
args = amask >> 2;
4747
statics = amask & 3;
4748
}
4749
4750
if (args > 0) {
4751
(*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
4752
if (args > 1)
4753
(*info->fprintf_func) (info->stream, "-%s",
4754
mips_gpr_names[4 + args - 1]);
4755
need_comma = 1;
4756
}
4757
4758
framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
4759
if (framesz == 0 && !use_extend)
4760
framesz = 128;
4761
4762
(*info->fprintf_func) (info->stream, "%s%d",
4763
need_comma ? "," : "",
4764
framesz);
4765
4766
if (l & 0x40) /* $ra */
4767
(*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
4768
4769
nsreg = (l >> 24) & 0x7;
4770
smask = 0;
4771
if (l & 0x20) /* $s0 */
4772
smask |= 1 << 0;
4773
if (l & 0x10) /* $s1 */
4774
smask |= 1 << 1;
4775
if (nsreg > 0) /* $s2-$s8 */
4776
smask |= ((1 << nsreg) - 1) << 2;
4777
4778
/* Find first set static reg bit. */
4779
for (i = 0; i < 9; i++)
4780
{
4781
if (smask & (1 << i))
4782
{
4783
(*info->fprintf_func) (info->stream, ",%s",
4784
mips_gpr_names[i == 8 ? 30 : (16 + i)]);
4785
/* Skip over string of set bits. */
4786
for (j = i; smask & (2 << j); j++)
4787
continue;
4788
if (j > i)
4789
(*info->fprintf_func) (info->stream, "-%s",
4790
mips_gpr_names[j == 8 ? 30 : (16 + j)]);
4791
i = j + 1;
4792
}
4793
}
4794
4795
/* Statics $ax - $a3. */
4796
if (statics == 1)
4797
(*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
4798
else if (statics > 0)
4799
(*info->fprintf_func) (info->stream, ",%s-%s",
4800
mips_gpr_names[7 - statics + 1],
4801
mips_gpr_names[7]);
4802
}
4803
break;
4804
3936
4805
default:
3937
4806
/* xgettext:c-format */
3938
4807
(*info->fprintf_func)
3945
4814
#endif
3946
4815
3947
4816
void
3948
print_mips_disassembler_options (stream)
3949
FILE *stream;
4817
print_mips_disassembler_options (FILE *stream)
3950
4818
{
3951
4819
unsigned int i;
3952
4820
Loggerhead is a web-based interface for Breezy
Version: 2.0.1