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typedef struct SLAVIO_TIMERState {
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uint32_t limit, count, counthigh;
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int64_t count_load_time;
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int64_t stop_time, tick_offset;
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uint32_t count, counthigh, reached;
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int mode; // 0 = processor, 1 = user, 2 = system
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} SLAVIO_TIMERState;
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#define TIMER_MAXADDR 0x1f
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#define CNT_FREQ 2000000
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#define TIMER_SIZE (TIMER_MAXADDR + 1)
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// Update count, set irq, update expire_time
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// Convert from ptimer countdown units
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static void slavio_timer_get_out(SLAVIO_TIMERState *s)
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int64_t diff, ticks, count;
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// There are three clock tick units: CPU ticks, register units
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// (nanoseconds), and counter ticks (500 ns).
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if (s->mode == 1 && s->stopped)
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ticks = qemu_get_clock(vm_clock) - s->tick_offset;
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out = (ticks > s->expire_time);
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s->reached = 0x80000000;
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// Convert register units to counter ticks
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// Convert cpu ticks to counter ticks
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diff = muldiv64(ticks - s->count_load_time, CNT_FREQ, ticks_per_sec);
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// Calculate what the counter should be, convert to register
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s->count = count << 9;
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s->counthigh = count >> 22;
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// Expire time: CPU ticks left to next interrupt
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// Convert remaining counter ticks to CPU ticks
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s->expire_time = ticks + muldiv64(limit - count, ticks_per_sec, CNT_FREQ);
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DPRINTF("irq %d limit %d reached %d d %" PRId64 " count %d s->c %x diff %" PRId64 " stopped %d mode %d\n", s->irq, limit, s->reached?1:0, (ticks-s->count_load_time), count, s->count, s->expire_time - ticks, s->stopped, s->mode);
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pic_set_irq_cpu(s->irq, out, s->cpu);
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count = s->limit - (ptimer_get_count(s->timer) << 9);
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DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, s->counthigh,
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s->count = count & 0xfffffe00;
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s->counthigh = count >> 32;
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SLAVIO_TIMERState *s = opaque;
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slavio_timer_get_out(s);
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DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
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s->reached = 0x80000000;
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qemu_mod_timer(s->irq_timer, s->expire_time);
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qemu_irq_raise(s->irq);
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static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
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SLAVIO_TIMERState *s = opaque;
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saddr = (addr & TIMER_MAXADDR) >> 2;
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// part of counter (user mode)
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if (s->mode != 1) {
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pic_set_irq_cpu(s->irq, 0, s->cpu);
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s->count_load_time = qemu_get_clock(vm_clock);
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qemu_irq_lower(s->irq);
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ret = s->limit & 0x7fffffff;
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slavio_timer_get_out(s);
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return s->counthigh & 0x7fffffff;
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ret = s->counthigh & 0x7fffffff;
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// read counter and reached bit (system mode) or read lsbits
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// of counter (user mode)
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slavio_timer_get_out(s);
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if (s->mode != 1)
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return (s->count & 0x7fffffff) | s->reached;
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ret = (s->count & 0x7fffffff) | s->reached;
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// read start/stop status
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// read user/system mode
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DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
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static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
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SLAVIO_TIMERState *s = opaque;
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DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
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saddr = (addr & TIMER_MAXADDR) >> 2;
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// set limit, reset counter
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s->count_load_time = qemu_get_clock(vm_clock);
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qemu_irq_lower(s->irq);
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// set limit without resetting counter
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s->limit = 0x7fffffff;
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s->limit = val & 0x7fffffff;
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s->limit = val & 0x7ffffe00ULL;
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s->limit = 0x7ffffe00ULL;
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ptimer_set_limit(s->timer, s->limit >> 9, reload);
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// start/stop user counter
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if (s->mode == 1) {
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s->stop_time = qemu_get_clock(vm_clock);
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ptimer_stop(s->timer);
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s->tick_offset += qemu_get_clock(vm_clock) - s->stop_time;
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ptimer_run(s->timer, 0);
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SLAVIO_TIMERState *s = opaque;
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qemu_put_be32s(f, &s->limit);
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qemu_put_be64s(f, &s->limit);
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qemu_put_be32s(f, &s->count);
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qemu_put_be32s(f, &s->counthigh);
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qemu_put_be64s(f, &s->count_load_time);
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qemu_put_be64s(f, &s->expire_time);
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qemu_put_be64s(f, &s->stop_time);
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qemu_put_be64s(f, &s->tick_offset);
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qemu_put_be32s(f, &s->irq);
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qemu_put_be32(f, 0); // Was irq
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qemu_put_be32s(f, &s->reached);
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qemu_put_be32s(f, &s->stopped);
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qemu_put_be32s(f, &s->mode);
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qemu_put_ptimer(f, s->timer);
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static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
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SLAVIO_TIMERState *s = opaque;
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qemu_get_be32s(f, &s->limit);
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qemu_get_be64s(f, &s->limit);
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qemu_get_be32s(f, &s->count);
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qemu_get_be32s(f, &s->counthigh);
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qemu_get_be64s(f, &s->count_load_time);
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qemu_get_be64s(f, &s->expire_time);
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qemu_get_be64s(f, &s->stop_time);
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qemu_get_be64s(f, &s->tick_offset);
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qemu_get_be32s(f, &s->irq);
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qemu_get_be32s(f, &tmp); // Was irq
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qemu_get_be32s(f, &s->reached);
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qemu_get_be32s(f, &s->stopped);
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qemu_get_be32s(f, &s->mode);
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qemu_get_ptimer(f, s->timer);
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SLAVIO_TIMERState *s = opaque;
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s->limit = 0x7ffffe00ULL;
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s->count_load_time = qemu_get_clock(vm_clock);;
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s->stop_time = s->count_load_time;
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ptimer_set_limit(s->timer, s->limit >> 9, 1);
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ptimer_run(s->timer, 0);
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slavio_timer_get_out(s);
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qemu_irq_lower(s->irq);
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void slavio_timer_init(uint32_t addr, int irq, int mode, unsigned int cpu)
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void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode)
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int slavio_timer_io_memory;
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SLAVIO_TIMERState *s;
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s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
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s->irq_timer = qemu_new_timer(vm_clock, slavio_timer_irq, s);
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bh = qemu_bh_new(slavio_timer_irq, s);
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s->timer = ptimer_init(bh);
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ptimer_set_period(s->timer, 500ULL);
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slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
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slavio_timer_mem_write, s);
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cpu_register_physical_memory(addr, TIMER_MAXADDR, slavio_timer_io_memory);
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register_savevm("slavio_timer", addr, 1, slavio_timer_save, slavio_timer_load, s);
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cpu_register_physical_memory(addr, TIMER_SIZE, slavio_timer_io_memory);
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register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s);
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qemu_register_reset(slavio_timer_reset, s);
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slavio_timer_reset(s);