29
29
#define INITRD_LOAD_ADDR 0x00300000
30
30
#define PROM_SIZE_MAX (512 * 1024)
31
31
#define PROM_ADDR 0x1fff0000000ULL
32
#define PROM_VADDR 0x000ffd00000ULL
32
33
#define APB_SPECIAL_BASE 0x1fe00000000ULL
33
34
#define APB_MEM_BASE 0x1ff00000000ULL
34
35
#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
174
static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
175
const unsigned char *str)
179
len = strlen(str) + 1;
180
NVRAM_set_string(nvram, addr, str, len);
185
static void nvram_finish_partition (m48t59_t *nvram, uint32_t start,
190
// Length divided by 16
191
m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff);
192
m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff);
194
sum = m48t59_read(nvram, start);
195
for (i = 0; i < 14; i++) {
196
sum += m48t59_read(nvram, start + 2 + i);
197
sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
199
m48t59_write(nvram, start + 1, sum & 0xff);
173
202
extern int nographic;
175
204
int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
182
211
int width, int height, int depth)
186
217
/* Set parameters for Open Hack'Ware BIOS */
187
218
NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
212
243
crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
213
244
NVRAM_set_word(nvram, 0xFC, crc);
246
// OpenBIOS nvram variables
247
// Variable partition
249
m48t59_write(nvram, start, 0x70);
250
NVRAM_set_string(nvram, start + 4, "system", 12);
253
for (i = 0; i < nb_prom_envs; i++)
254
end = nvram_set_var(nvram, end, prom_envs[i]);
256
m48t59_write(nvram, end++ , 0);
257
end = start + ((end - start + 15) & ~15);
258
nvram_finish_partition(nvram, start, end);
262
m48t59_write(nvram, start, 0x7f);
263
NVRAM_set_string(nvram, start + 4, "free", 12);
266
nvram_finish_partition(nvram, start, end);
226
void pic_set_irq(int irq, int level)
230
void pic_set_irq_new(void *opaque, int irq, int level)
234
279
void qemu_system_powerdown(void)
238
283
static void main_cpu_reset(void *opaque)
240
285
CPUState *env = opaque;
288
ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
289
ptimer_run(env->tick, 0);
290
ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
291
ptimer_run(env->stick, 0);
292
ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
293
ptimer_run(env->hstick, 0);
296
void tick_irq(void *opaque)
298
CPUState *env = opaque;
300
cpu_interrupt(env, CPU_INTERRUPT_TIMER);
303
void stick_irq(void *opaque)
305
CPUState *env = opaque;
307
cpu_interrupt(env, CPU_INTERRUPT_TIMER);
310
void hstick_irq(void *opaque)
312
CPUState *env = opaque;
314
cpu_interrupt(env, CPU_INTERRUPT_TIMER);
317
static void dummy_cpu_set_irq(void *opaque, int irq, int level)
244
321
static const int ide_iobase[2] = { 0x1f0, 0x170 };
257
334
static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
258
335
DisplayState *ds, const char **fd_filename, int snapshot,
259
336
const char *kernel_filename, const char *kernel_cmdline,
260
const char *initrd_filename)
337
const char *initrd_filename, const char *cpu_model)
267
344
long prom_offset, initrd_size, kernel_size;
346
const sparc_def_t *def;
270
350
linux_boot = (kernel_filename != NULL);
353
if (cpu_model == NULL)
354
cpu_model = "TI UltraSparc II";
355
sparc_find_by_name(cpu_model, &def);
357
fprintf(stderr, "Unable to find Sparc CPU definition\n");
272
360
env = cpu_init();
361
cpu_sparc_register(env, def);
362
bh = qemu_bh_new(tick_irq, env);
363
env->tick = ptimer_init(bh);
364
ptimer_set_period(env->tick, 1ULL);
366
bh = qemu_bh_new(stick_irq, env);
367
env->stick = ptimer_init(bh);
368
ptimer_set_period(env->stick, 1ULL);
370
bh = qemu_bh_new(hstick_irq, env);
371
env->hstick = ptimer_init(bh);
372
ptimer_set_period(env->hstick, 1ULL);
273
373
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
274
374
qemu_register_reset(main_cpu_reset, env);
276
377
/* allocate RAM */
277
378
cpu_register_physical_memory(0, ram_size, 0);
282
383
prom_offset | IO_MEM_ROM);
284
385
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
285
ret = load_elf(buf, 0, NULL);
386
ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
287
388
fprintf(stderr, "qemu: could not load prom '%s'\n",
294
395
if (linux_boot) {
295
396
/* XXX: put correct offset */
296
kernel_size = load_elf(kernel_filename, 0, NULL);
397
kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
297
398
if (kernel_size < 0)
298
399
kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
299
400
if (kernel_size < 0)
331
432
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
332
433
if (serial_hds[i]) {
333
serial_init(&pic_set_irq_new, NULL,
334
serial_io[i], serial_irq[i], serial_hds[i]);
434
serial_init(serial_io[i], NULL/*serial_irq[i]*/, serial_hds[i]);
338
438
for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
339
439
if (parallel_hds[i]) {
340
parallel_init(parallel_io[i], parallel_irq[i], parallel_hds[i]);
440
parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]);
347
447
pci_nic_init(pci_bus, &nd_table[i], -1);
350
pci_cmd646_ide_init(pci_bus, bs_table, 1);
352
floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table);
353
nvram = m48t59_init(8, 0, 0x0074, NVRAM_SIZE, 59);
450
irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
451
// XXX pci_cmd646_ide_init(pci_bus, bs_table, 1);
452
pci_piix3_ide_init(pci_bus, bs_table, -1, irq);
453
/* FIXME: wire up interrupts. */
454
i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
455
floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd_table);
456
nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
354
457
sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device,
355
458
KERNEL_LOAD_ADDR, kernel_size,