46
49
static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
48
printf("%s: 0x%08x <= 0x%08x\n", __func__, addr, value);
51
printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value);
51
54
static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
258
261
/* R6 = x, R7 = y, R8 = visible, R9 = data */
261
fprintf(stderr, "unsupported OSI call R5=%08x\n", env->gpr[5]);
264
fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
264
267
return 1; /* osi_call handled */
267
/* XXX: suppress that */
268
static void pic_irq_request(void *opaque, int level)
272
270
static uint8_t nvram_chksum(const uint8_t *buf, int n)
294
292
/* PowerPC CHRP hardware initialisation */
295
static void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
296
DisplayState *ds, const char **fd_filename,
298
const char *kernel_filename,
299
const char *kernel_cmdline,
300
const char *initrd_filename,
293
static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
294
DisplayState *ds, const char **fd_filename,
296
const char *kernel_filename,
297
const char *kernel_cmdline,
298
const char *initrd_filename,
299
const char *cpu_model,
302
CPUState *env, *envs[MAX_CPUS];
304
qemu_irq *pic, **openpic_irqs;
309
307
int linux_boot, i;
314
312
const char *arch_name;
315
313
int vga_bios_size, bios_size;
317
316
linux_boot = (kernel_filename != NULL);
320
319
env = cpu_init();
320
qemu_register_reset(&cpu_ppc_reset, env);
321
321
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
323
/* Register CPU as a 74x/75x */
323
/* Default CPU is a generic 74x/75x */
324
if (cpu_model == NULL)
324
326
/* XXX: CPU model (or PVR) should be provided on command line */
325
327
// ppc_find_by_name("750gx", &def); // Linux boot OK
326
328
// ppc_find_by_name("750fx", &def); // Linux boot OK
327
329
/* Linux does not boot on 750cxe (and probably other 750cx based)
328
330
* because it assumes it has 8 IBAT & DBAT pairs as it only have 4.
330
// ppc_find_by_name("750cxe", &def);
331
// ppc_find_by_name("750p", &def);
332
// ppc_find_by_name("740p", &def);
333
ppc_find_by_name("750", &def);
334
// ppc_find_by_name("740", &def);
335
// ppc_find_by_name("G3", &def);
336
// ppc_find_by_name("604r", &def);
337
// ppc_find_by_name("604e", &def);
338
// ppc_find_by_name("604", &def);
332
ppc_find_by_name(cpu_model, &def);
339
333
if (def == NULL) {
340
334
cpu_abort(env, "Unable to find PowerPC CPU definition\n");
342
cpu_ppc_register(env, def);
344
/* Set time-base frequency to 100 Mhz */
345
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
347
env->osi_call = vga_osi_call;
336
for (i = 0; i < smp_cpus; i++) {
337
cpu_ppc_register(env, def);
338
/* Set time-base frequency to 100 Mhz */
339
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
340
env->osi_call = vga_osi_call;
349
344
/* allocate RAM */
350
345
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
354
349
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
355
350
bios_size = load_image(buf, phys_ram_base + bios_offset);
356
351
if (bios_size < 0 || bios_size > BIOS_SIZE) {
357
fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
352
cpu_abort(env, "qemu: could not load PowerPC bios '%s'\n", buf);
360
355
bios_size = (bios_size + 0xfff) & ~0xfff;
361
cpu_register_physical_memory((uint32_t)(-bios_size),
356
cpu_register_physical_memory((uint32_t)(-bios_size),
362
357
bios_size, bios_offset | IO_MEM_ROM);
364
359
/* allocate and load VGA BIOS */
416
411
if (is_heathrow) {
417
412
isa_mem_base = 0x80000000;
419
414
/* Register 2 MB of ISA IO space */
420
415
isa_mmio_init(0xfe000000, 0x00200000);
422
417
/* init basic PC hardware */
418
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
419
cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
423
422
pic = heathrow_pic_init(&heathrow_pic_mem_index);
424
set_irq = heathrow_pic_set_irq;
425
423
pci_bus = pci_grackle_init(0xfec00000, pic);
426
pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
424
pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
427
425
ram_size, vga_ram_size,
428
426
vga_bios_offset, vga_bios_size);
430
428
/* XXX: suppress that */
431
isa_pic = pic_init(pic_irq_request, NULL);
429
dummy_irq = i8259_init(NULL);
433
431
/* XXX: use Mac Serial port */
434
serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
432
serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
436
434
for(i = 0; i < nb_nics; i++) {
437
435
if (!nd_table[i].model)
456
454
macio_init(pci_bus, 0x0017);
458
nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
456
nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
460
458
arch_name = "HEATHROW";
462
460
isa_mem_base = 0x80000000;
464
462
/* Register 8 MB of ISA IO space */
465
463
isa_mmio_init(0xf2000000, 0x00800000);
468
466
unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
469
467
cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
471
pic = openpic_init(NULL, &openpic_mem_index, 1, &env);
472
set_irq = openpic_set_irq;
469
openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
471
qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
472
for (i = 0; i < smp_cpus; i++) {
473
/* Mac99 IRQ connection between OpenPIC outputs pins
474
* and PowerPC input pins
476
switch (PPC_INPUT(env)) {
477
case PPC_FLAGS_INPUT_6xx:
478
openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
479
openpic_irqs[i][OPENPIC_OUTPUT_INT] =
480
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
481
openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
482
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
483
openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
484
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
485
/* Not connected ? */
486
openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
488
openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
489
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
491
case PPC_FLAGS_INPUT_970:
492
openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
493
openpic_irqs[i][OPENPIC_OUTPUT_INT] =
494
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
495
openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
496
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
497
openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
498
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
499
/* Not connected ? */
500
openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
502
openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
503
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
507
"Only bus model not supported on mac99 machine\n");
511
pic = openpic_init(NULL, &openpic_mem_index, smp_cpus,
473
513
pci_bus = pci_pmac_init(pic);
474
514
/* init basic PC hardware */
475
515
pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
477
517
vga_bios_offset, vga_bios_size);
479
519
/* XXX: suppress that */
480
isa_pic = pic_init(pic_irq_request, NULL);
520
dummy_irq = i8259_init(NULL);
482
522
/* XXX: use Mac Serial port */
483
serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
523
serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
485
524
for(i = 0; i < nb_nics; i++) {
486
pci_ne2000_init(pci_bus, &nd_table[i], -1);
525
if (!nd_table[i].model)
526
nd_table[i].model = "ne2k_pci";
527
pci_nic_init(pci_bus, &nd_table[i], -1);
490
ide0_mem_index = pmac_ide_init(&bs_table[0], set_irq, pic, 0x13);
491
ide1_mem_index = pmac_ide_init(&bs_table[2], set_irq, pic, 0x14);
530
ide0_mem_index = pmac_ide_init(&bs_table[0], pic[0x13]);
531
ide1_mem_index = pmac_ide_init(&bs_table[2], pic[0x14]);
493
533
pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
495
535
/* cuda also initialize ADB */
496
cuda_mem_index = cuda_init(set_irq, pic, 0x19);
536
cuda_mem_index = cuda_init(pic[0x19]);
498
538
adb_kbd_init(&adb_bus);
499
539
adb_mouse_init(&adb_bus);
501
541
macio_init(pci_bus, 0x0022);
503
nvram = m48t59_init(8, 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
543
nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
505
545
arch_name = "MAC99";
508
548
if (usb_enabled) {
509
usb_ohci_init(pci_bus, 3, -1);
549
usb_ohci_init_pci(pci_bus, 3, -1);
512
552
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
525
565
register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
528
static void ppc_core99_init(int ram_size, int vga_ram_size, int boot_device,
529
DisplayState *ds, const char **fd_filename,
531
const char *kernel_filename,
532
const char *kernel_cmdline,
533
const char *initrd_filename)
568
static void ppc_core99_init (int ram_size, int vga_ram_size, int boot_device,
569
DisplayState *ds, const char **fd_filename,
571
const char *kernel_filename,
572
const char *kernel_cmdline,
573
const char *initrd_filename,
574
const char *cpu_model)
535
576
ppc_chrp_init(ram_size, vga_ram_size, boot_device,
536
577
ds, fd_filename, snapshot,
537
578
kernel_filename, kernel_cmdline,
579
initrd_filename, cpu_model, 0);
541
static void ppc_heathrow_init(int ram_size, int vga_ram_size, int boot_device,
542
DisplayState *ds, const char **fd_filename,
544
const char *kernel_filename,
545
const char *kernel_cmdline,
546
const char *initrd_filename)
582
static void ppc_heathrow_init (int ram_size, int vga_ram_size, int boot_device,
583
DisplayState *ds, const char **fd_filename,
585
const char *kernel_filename,
586
const char *kernel_cmdline,
587
const char *initrd_filename,
588
const char *cpu_model)
548
590
ppc_chrp_init(ram_size, vga_ram_size, boot_device,
549
591
ds, fd_filename, snapshot,
550
592
kernel_filename, kernel_cmdline,
593
initrd_filename, cpu_model, 1);
554
596
QEMUMachine core99_machine = {