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/*****************************************************************************
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* 6502 opcode functions and function pointer table
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* Copyright Juergen Buchmueller, all rights reserved.
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* - This source code is released as freeware for non-commercial purposes.
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* - You are free to use and redistribute this code in modified or
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* unmodified form, provided you list me in the credits.
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* - If you modify this source code, you must add a notice to each modified
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* source file that it has been changed. If you're a nice person, you
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* will clearly mark each change too. :)
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* - If you wish to use this for commercial purposes, please contact me at
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* pullmoll@t-online.de
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* - The author of this copywritten work reserves the right to change the
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* terms of its usage and license at any time, including retroactively
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* - This entire notice must remain in the source code.
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* 2003-05-26 Fixed PHP, PLP, PHA, PLA cycle counts. [SJ]
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* 2004-04-30 Fixed STX (abs) cycle count. [SJ]
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*****************************************************************************/
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#define OP(nn) INLINE void m6502_##nn(m6502_Regs *cpustate)
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/*****************************************************************************
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*****************************************************************************
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* plain vanilla 6502 opcodes
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*****************************************************************************
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* op temp cycles rdmem opc wrmem ********************/
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OP(00) { BRK; } /* 7 BRK */
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OP(20) { JSR; } /* 6 JSR */
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OP(40) { RTI; } /* 6 RTI */
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OP(60) { RTS; } /* 6 RTS */
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OP(80) { RDOPARG(); NOP; } /* 2 NOP IMM */
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OP(a0) { int tmp; RD_IMM; LDY; } /* 2 LDY IMM */
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OP(c0) { int tmp; RD_IMM; CPY; } /* 2 CPY IMM */
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OP(e0) { int tmp; RD_IMM; CPX; } /* 2 CPX IMM */
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OP(10) { BPL; } /* 2-4 BPL REL */
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OP(30) { BMI; } /* 2-4 BMI REL */
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OP(50) { BVC; } /* 2-4 BVC REL */
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OP(70) { BVS; } /* 2-4 BVS REL */
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OP(90) { BCC; } /* 2-4 BCC REL */
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OP(b0) { BCS; } /* 2-4 BCS REL */
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OP(d0) { BNE; } /* 2-4 BNE REL */
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OP(f0) { BEQ; } /* 2-4 BEQ REL */
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OP(01) { int tmp; RD_IDX; ORA; } /* 6 ORA IDX */
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OP(21) { int tmp; RD_IDX; AND; } /* 6 AND IDX */
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OP(41) { int tmp; RD_IDX; EOR; } /* 6 EOR IDX */
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OP(61) { int tmp; RD_IDX; ADC; } /* 6 ADC IDX */
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OP(81) { int tmp; STA; WR_IDX; } /* 6 STA IDX */
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OP(a1) { int tmp; RD_IDX; LDA; } /* 6 LDA IDX */
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OP(c1) { int tmp; RD_IDX; CMP; } /* 6 CMP IDX */
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OP(e1) { int tmp; RD_IDX; SBC; } /* 6 SBC IDX */
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OP(11) { int tmp; RD_IDY_P; ORA; } /* 5 ORA IDY page penalty */
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OP(31) { int tmp; RD_IDY_P; AND; } /* 5 AND IDY page penalty */
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OP(51) { int tmp; RD_IDY_P; EOR; } /* 5 EOR IDY page penalty */
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OP(71) { int tmp; RD_IDY_P; ADC; } /* 5 ADC IDY page penalty */
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OP(91) { int tmp; STA; WR_IDY_NP; } /* 6 STA IDY */
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OP(b1) { int tmp; RD_IDY_P; LDA; } /* 5 LDA IDY page penalty */
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OP(d1) { int tmp; RD_IDY_P; CMP; } /* 5 CMP IDY page penalty */
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OP(f1) { int tmp; RD_IDY_P; SBC; } /* 5 SBC IDY page penalty */
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OP(02) { KIL; } /* 1 KIL */
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OP(22) { KIL; } /* 1 KIL */
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OP(42) { KIL; } /* 1 KIL */
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OP(62) { KIL; } /* 1 KIL */
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OP(82) { RDOPARG(); NOP; } /* 2 NOP IMM */
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OP(a2) { int tmp; RD_IMM; LDX; } /* 2 LDX IMM */
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OP(c2) { RDOPARG(); NOP; } /* 2 NOP IMM */
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OP(e2) { RDOPARG(); NOP; } /* 2 NOP IMM */
81
OP(12) { KIL; } /* 1 KIL */
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OP(32) { KIL; } /* 1 KIL */
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OP(52) { KIL; } /* 1 KIL */
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OP(72) { KIL; } /* 1 KIL */
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OP(92) { KIL; } /* 1 KIL */
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OP(b2) { KIL; } /* 1 KIL */
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OP(d2) { KIL; } /* 1 KIL */
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OP(f2) { KIL; } /* 1 KIL */
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OP(03) { int tmp; RD_IDX; WB_EA; SLO; WB_EA; } /* 7 SLO IDX */
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OP(23) { int tmp; RD_IDX; WB_EA; RLA; WB_EA; } /* 7 RLA IDX */
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OP(43) { int tmp; RD_IDX; WB_EA; SRE; WB_EA; } /* 7 SRE IDX */
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OP(63) { int tmp; RD_IDX; WB_EA; RRA; WB_EA; } /* 7 RRA IDX */
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OP(83) { int tmp; SAX; WR_IDX; } /* 6 SAX IDX */
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OP(a3) { int tmp; RD_IDX; LAX; } /* 6 LAX IDX */
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OP(c3) { int tmp; RD_IDX; WB_EA; DCP; WB_EA; } /* 7 DCP IDX */
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OP(e3) { int tmp; RD_IDX; WB_EA; ISB; WB_EA; } /* 7 ISB IDX */
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OP(13) { int tmp; RD_IDY_NP; WB_EA; SLO; WB_EA; } /* 7 SLO IDY */
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OP(33) { int tmp; RD_IDY_NP; WB_EA; RLA; WB_EA; } /* 7 RLA IDY */
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OP(53) { int tmp; RD_IDY_NP; WB_EA; SRE; WB_EA; } /* 7 SRE IDY */
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OP(73) { int tmp; RD_IDY_NP; WB_EA; RRA; WB_EA; } /* 7 RRA IDY */
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OP(93) { int tmp; EA_IDY_NP; SAH; WB_EA; } /* 5 SAH IDY */
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OP(b3) { int tmp; RD_IDY_P; LAX; } /* 5 LAX IDY page penalty */
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OP(d3) { int tmp; RD_IDY_NP; WB_EA; DCP; WB_EA; } /* 7 DCP IDY */
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OP(f3) { int tmp; RD_IDY_NP; WB_EA; ISB; WB_EA; } /* 7 ISB IDY */
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OP(04) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */
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OP(24) { int tmp; RD_ZPG; BIT; } /* 3 BIT ZPG */
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OP(44) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */
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OP(64) { RD_ZPG_DISCARD; NOP; } /* 3 NOP ZPG */
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OP(84) { int tmp; STY; WR_ZPG; } /* 3 STY ZPG */
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OP(a4) { int tmp; RD_ZPG; LDY; } /* 3 LDY ZPG */
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OP(c4) { int tmp; RD_ZPG; CPY; } /* 3 CPY ZPG */
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OP(e4) { int tmp; RD_ZPG; CPX; } /* 3 CPX ZPG */
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OP(14) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
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OP(34) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
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OP(54) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
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OP(74) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
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OP(94) { int tmp; STY; WR_ZPX; } /* 4 STY ZPX */
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OP(b4) { int tmp; RD_ZPX; LDY; } /* 4 LDY ZPX */
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OP(d4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
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OP(f4) { RD_ZPX_DISCARD; NOP; } /* 4 NOP ZPX */
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OP(05) { int tmp; RD_ZPG; ORA; } /* 3 ORA ZPG */
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OP(25) { int tmp; RD_ZPG; AND; } /* 3 AND ZPG */
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OP(45) { int tmp; RD_ZPG; EOR; } /* 3 EOR ZPG */
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OP(65) { int tmp; RD_ZPG; ADC; } /* 3 ADC ZPG */
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OP(85) { int tmp; STA; WR_ZPG; } /* 3 STA ZPG */
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OP(a5) { int tmp; RD_ZPG; LDA; } /* 3 LDA ZPG */
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OP(c5) { int tmp; RD_ZPG; CMP; } /* 3 CMP ZPG */
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OP(e5) { int tmp; RD_ZPG; SBC; } /* 3 SBC ZPG */
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OP(15) { int tmp; RD_ZPX; ORA; } /* 4 ORA ZPX */
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OP(35) { int tmp; RD_ZPX; AND; } /* 4 AND ZPX */
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OP(55) { int tmp; RD_ZPX; EOR; } /* 4 EOR ZPX */
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OP(75) { int tmp; RD_ZPX; ADC; } /* 4 ADC ZPX */
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OP(95) { int tmp; STA; WR_ZPX; } /* 4 STA ZPX */
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OP(b5) { int tmp; RD_ZPX; LDA; } /* 4 LDA ZPX */
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OP(d5) { int tmp; RD_ZPX; CMP; } /* 4 CMP ZPX */
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OP(f5) { int tmp; RD_ZPX; SBC; } /* 4 SBC ZPX */
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OP(06) { int tmp; RD_ZPG; WB_EA; ASL; WB_EA; } /* 5 ASL ZPG */
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OP(26) { int tmp; RD_ZPG; WB_EA; ROL; WB_EA; } /* 5 ROL ZPG */
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OP(46) { int tmp; RD_ZPG; WB_EA; LSR; WB_EA; } /* 5 LSR ZPG */
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OP(66) { int tmp; RD_ZPG; WB_EA; ROR; WB_EA; } /* 5 ROR ZPG */
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OP(86) { int tmp; STX; WR_ZPG; } /* 3 STX ZPG */
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OP(a6) { int tmp; RD_ZPG; LDX; } /* 3 LDX ZPG */
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OP(c6) { int tmp; RD_ZPG; WB_EA; DEC; WB_EA; } /* 5 DEC ZPG */
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OP(e6) { int tmp; RD_ZPG; WB_EA; INC; WB_EA; } /* 5 INC ZPG */
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OP(16) { int tmp; RD_ZPX; WB_EA; ASL; WB_EA; } /* 6 ASL ZPX */
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OP(36) { int tmp; RD_ZPX; WB_EA; ROL; WB_EA; } /* 6 ROL ZPX */
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OP(56) { int tmp; RD_ZPX; WB_EA; LSR; WB_EA; } /* 6 LSR ZPX */
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OP(76) { int tmp; RD_ZPX; WB_EA; ROR; WB_EA; } /* 6 ROR ZPX */
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OP(96) { int tmp; STX; WR_ZPY; } /* 4 STX ZPY */
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OP(b6) { int tmp; RD_ZPY; LDX; } /* 4 LDX ZPY */
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OP(d6) { int tmp; RD_ZPX; WB_EA; DEC; WB_EA; } /* 6 DEC ZPX */
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OP(f6) { int tmp; RD_ZPX; WB_EA; INC; WB_EA; } /* 6 INC ZPX */
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OP(07) { int tmp; RD_ZPG; WB_EA; SLO; WB_EA; } /* 5 SLO ZPG */
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OP(27) { int tmp; RD_ZPG; WB_EA; RLA; WB_EA; } /* 5 RLA ZPG */
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OP(47) { int tmp; RD_ZPG; WB_EA; SRE; WB_EA; } /* 5 SRE ZPG */
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OP(67) { int tmp; RD_ZPG; WB_EA; RRA; WB_EA; } /* 5 RRA ZPG */
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OP(87) { int tmp; SAX; WR_ZPG; } /* 3 SAX ZPG */
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OP(a7) { int tmp; RD_ZPG; LAX; } /* 3 LAX ZPG */
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OP(c7) { int tmp; RD_ZPG; WB_EA; DCP; WB_EA; } /* 5 DCP ZPG */
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OP(e7) { int tmp; RD_ZPG; WB_EA; ISB; WB_EA; } /* 5 ISB ZPG */
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OP(17) { int tmp; RD_ZPX; WB_EA; SLO; WB_EA; } /* 6 SLO ZPX */
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OP(37) { int tmp; RD_ZPX; WB_EA; RLA; WB_EA; } /* 6 RLA ZPX */
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OP(57) { int tmp; RD_ZPX; WB_EA; SRE; WB_EA; } /* 6 SRE ZPX */
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OP(77) { int tmp; RD_ZPX; WB_EA; RRA; WB_EA; } /* 6 RRA ZPX */
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OP(97) { int tmp; SAX; WR_ZPY; } /* 4 SAX ZPY */
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OP(b7) { int tmp; RD_ZPY; LAX; } /* 4 LAX ZPY */
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OP(d7) { int tmp; RD_ZPX; WB_EA; DCP; WB_EA; } /* 6 DCP ZPX */
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OP(f7) { int tmp; RD_ZPX; WB_EA; ISB; WB_EA; } /* 6 ISB ZPX */
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OP(08) { RD_DUM; PHP; } /* 3 PHP */
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OP(28) { RD_DUM; PLP; } /* 4 PLP */
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OP(48) { RD_DUM; PHA; } /* 3 PHA */
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OP(68) { RD_DUM; PLA; } /* 4 PLA */
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OP(88) { RD_DUM; DEY; } /* 2 DEY */
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OP(a8) { RD_DUM; TAY; } /* 2 TAY */
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OP(c8) { RD_DUM; INY; } /* 2 INY */
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OP(e8) { RD_DUM; INX; } /* 2 INX */
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OP(18) { RD_DUM; CLC; } /* 2 CLC */
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OP(38) { RD_DUM; SEC; } /* 2 SEC */
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OP(58) { RD_DUM; CLI; } /* 2 CLI */
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OP(78) { RD_DUM; SEI; } /* 2 SEI */
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OP(98) { RD_DUM; TYA; } /* 2 TYA */
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OP(b8) { RD_DUM; CLV; } /* 2 CLV */
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OP(d8) { RD_DUM; CLD; } /* 2 CLD */
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OP(f8) { RD_DUM; SED; } /* 2 SED */
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OP(09) { int tmp; RD_IMM; ORA; } /* 2 ORA IMM */
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OP(29) { int tmp; RD_IMM; AND; } /* 2 AND IMM */
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OP(49) { int tmp; RD_IMM; EOR; } /* 2 EOR IMM */
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OP(69) { int tmp; RD_IMM; ADC; } /* 2 ADC IMM */
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OP(89) { RD_IMM_DISCARD; NOP; } /* 2 NOP IMM */
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OP(a9) { int tmp; RD_IMM; LDA; } /* 2 LDA IMM */
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OP(c9) { int tmp; RD_IMM; CMP; } /* 2 CMP IMM */
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OP(e9) { int tmp; RD_IMM; SBC; } /* 2 SBC IMM */
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OP(19) { int tmp; RD_ABY_P; ORA; } /* 4 ORA ABY page penalty */
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OP(39) { int tmp; RD_ABY_P; AND; } /* 4 AND ABY page penalty */
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OP(59) { int tmp; RD_ABY_P; EOR; } /* 4 EOR ABY page penalty */
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OP(79) { int tmp; RD_ABY_P; ADC; } /* 4 ADC ABY page penalty */
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OP(99) { int tmp; STA; WR_ABY_NP; } /* 5 STA ABY */
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OP(b9) { int tmp; RD_ABY_P; LDA; } /* 4 LDA ABY page penalty */
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OP(d9) { int tmp; RD_ABY_P; CMP; } /* 4 CMP ABY page penalty */
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OP(f9) { int tmp; RD_ABY_P; SBC; } /* 4 SBC ABY page penalty */
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OP(0a) { int tmp; RD_DUM; RD_ACC; ASL; WB_ACC; } /* 2 ASL A */
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OP(2a) { int tmp; RD_DUM; RD_ACC; ROL; WB_ACC; } /* 2 ROL A */
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OP(4a) { int tmp; RD_DUM; RD_ACC; LSR; WB_ACC; } /* 2 LSR A */
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OP(6a) { int tmp; RD_DUM; RD_ACC; ROR; WB_ACC; } /* 2 ROR A */
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OP(8a) { RD_DUM; TXA; } /* 2 TXA */
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OP(aa) { RD_DUM; TAX; } /* 2 TAX */
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OP(ca) { RD_DUM; DEX; } /* 2 DEX */
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OP(ea) { RD_DUM; NOP; } /* 2 NOP */
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OP(1a) { RD_DUM; NOP; } /* 2 NOP */
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OP(3a) { RD_DUM; NOP; } /* 2 NOP */
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OP(5a) { RD_DUM; NOP; } /* 2 NOP */
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OP(7a) { RD_DUM; NOP; } /* 2 NOP */
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OP(9a) { RD_DUM; TXS; } /* 2 TXS */
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OP(ba) { RD_DUM; TSX; } /* 2 TSX */
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OP(da) { RD_DUM; NOP; } /* 2 NOP */
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OP(fa) { RD_DUM; NOP; } /* 2 NOP */
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OP(0b) { int tmp; RD_IMM; ANC; } /* 2 ANC IMM */
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OP(2b) { int tmp; RD_IMM; ANC; } /* 2 ANC IMM */
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OP(4b) { int tmp; RD_IMM; ASR; WB_ACC; } /* 2 ASR IMM */
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OP(6b) { int tmp; RD_IMM; ARR; WB_ACC; } /* 2 ARR IMM */
238
OP(8b) { int tmp; RD_IMM; AXA; } /* 2 AXA IMM */
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OP(ab) { int tmp; RD_IMM; OAL; } /* 2 OAL IMM */
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OP(cb) { int tmp; RD_IMM; ASX; } /* 2 ASX IMM */
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OP(eb) { int tmp; RD_IMM; SBC; } /* 2 SBC IMM */
243
OP(1b) { int tmp; RD_ABY_NP; WB_EA; SLO; WB_EA; } /* 7 SLO ABY */
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OP(3b) { int tmp; RD_ABY_NP; WB_EA; RLA; WB_EA; } /* 7 RLA ABY */
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OP(5b) { int tmp; RD_ABY_NP; WB_EA; SRE; WB_EA; } /* 7 SRE ABY */
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OP(7b) { int tmp; RD_ABY_NP; WB_EA; RRA; WB_EA; } /* 7 RRA ABY */
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OP(9b) { int tmp; EA_ABY_NP; SSH; WB_EA; } /* 5 SSH ABY */
248
OP(bb) { int tmp; RD_ABY_P; AST; } /* 4 AST ABY page penalty */
249
OP(db) { int tmp; RD_ABY_NP; WB_EA; DCP; WB_EA; } /* 7 DCP ABY */
250
OP(fb) { int tmp; RD_ABY_NP; WB_EA; ISB; WB_EA; } /* 7 ISB ABY */
252
OP(0c) { RD_ABS_DISCARD; NOP; } /* 4 NOP ABS */
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OP(2c) { int tmp; RD_ABS; BIT; } /* 4 BIT ABS */
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OP(4c) { EA_ABS; JMP; } /* 3 JMP ABS */
255
OP(6c) { int tmp; EA_IND; JMP; } /* 5 JMP IND */
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OP(8c) { int tmp; STY; WR_ABS; } /* 4 STY ABS */
257
OP(ac) { int tmp; RD_ABS; LDY; } /* 4 LDY ABS */
258
OP(cc) { int tmp; RD_ABS; CPY; } /* 4 CPY ABS */
259
OP(ec) { int tmp; RD_ABS; CPX; } /* 4 CPX ABS */
261
OP(1c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
262
OP(3c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
263
OP(5c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
264
OP(7c) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
265
OP(9c) { int tmp; EA_ABX_NP; SYH; WB_EA; } /* 5 SYH ABX */
266
OP(bc) { int tmp; RD_ABX_P; LDY; } /* 4 LDY ABX page penalty */
267
OP(dc) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
268
OP(fc) { RD_ABX_P_DISCARD; NOP; } /* 4 NOP ABX page penalty */
270
OP(0d) { int tmp; RD_ABS; ORA; } /* 4 ORA ABS */
271
OP(2d) { int tmp; RD_ABS; AND; } /* 4 AND ABS */
272
OP(4d) { int tmp; RD_ABS; EOR; } /* 4 EOR ABS */
273
OP(6d) { int tmp; RD_ABS; ADC; } /* 4 ADC ABS */
274
OP(8d) { int tmp; STA; WR_ABS; } /* 4 STA ABS */
275
OP(ad) { int tmp; RD_ABS; LDA; } /* 4 LDA ABS */
276
OP(cd) { int tmp; RD_ABS; CMP; } /* 4 CMP ABS */
277
OP(ed) { int tmp; RD_ABS; SBC; } /* 4 SBC ABS */
279
OP(1d) { int tmp; RD_ABX_P; ORA; } /* 4 ORA ABX page penalty */
280
OP(3d) { int tmp; RD_ABX_P; AND; } /* 4 AND ABX page penalty */
281
OP(5d) { int tmp; RD_ABX_P; EOR; } /* 4 EOR ABX page penalty */
282
OP(7d) { int tmp; RD_ABX_P; ADC; } /* 4 ADC ABX page penalty */
283
OP(9d) { int tmp; STA; WR_ABX_NP; } /* 5 STA ABX */
284
OP(bd) { int tmp; RD_ABX_P; LDA; } /* 4 LDA ABX page penalty */
285
OP(dd) { int tmp; RD_ABX_P; CMP; } /* 4 CMP ABX page penalty */
286
OP(fd) { int tmp; RD_ABX_P; SBC; } /* 4 SBC ABX page penalty */
288
OP(0e) { int tmp; RD_ABS; WB_EA; ASL; WB_EA; } /* 6 ASL ABS */
289
OP(2e) { int tmp; RD_ABS; WB_EA; ROL; WB_EA; } /* 6 ROL ABS */
290
OP(4e) { int tmp; RD_ABS; WB_EA; LSR; WB_EA; } /* 6 LSR ABS */
291
OP(6e) { int tmp; RD_ABS; WB_EA; ROR; WB_EA; } /* 6 ROR ABS */
292
OP(8e) { int tmp; STX; WR_ABS; } /* 4 STX ABS */
293
OP(ae) { int tmp; RD_ABS; LDX; } /* 4 LDX ABS */
294
OP(ce) { int tmp; RD_ABS; WB_EA; DEC; WB_EA; } /* 6 DEC ABS */
295
OP(ee) { int tmp; RD_ABS; WB_EA; INC; WB_EA; } /* 6 INC ABS */
297
OP(1e) { int tmp; RD_ABX_NP; WB_EA; ASL; WB_EA; } /* 7 ASL ABX */
298
OP(3e) { int tmp; RD_ABX_NP; WB_EA; ROL; WB_EA; } /* 7 ROL ABX */
299
OP(5e) { int tmp; RD_ABX_NP; WB_EA; LSR; WB_EA; } /* 7 LSR ABX */
300
OP(7e) { int tmp; RD_ABX_NP; WB_EA; ROR; WB_EA; } /* 7 ROR ABX */
301
OP(9e) { int tmp; EA_ABY_NP; SXH; WB_EA; } /* 5 SXH ABY */
302
OP(be) { int tmp; RD_ABY_P; LDX; } /* 4 LDX ABY page penalty */
303
OP(de) { int tmp; RD_ABX_NP; WB_EA; DEC; WB_EA; } /* 7 DEC ABX */
304
OP(fe) { int tmp; RD_ABX_NP; WB_EA; INC; WB_EA; } /* 7 INC ABX */
306
OP(0f) { int tmp; RD_ABS; WB_EA; SLO; WB_EA; } /* 6 SLO ABS */
307
OP(2f) { int tmp; RD_ABS; WB_EA; RLA; WB_EA; } /* 6 RLA ABS */
308
OP(4f) { int tmp; RD_ABS; WB_EA; SRE; WB_EA; } /* 6 SRE ABS */
309
OP(6f) { int tmp; RD_ABS; WB_EA; RRA; WB_EA; } /* 6 RRA ABS */
310
OP(8f) { int tmp; SAX; WR_ABS; } /* 4 SAX ABS */
311
OP(af) { int tmp; RD_ABS; LAX; } /* 4 LAX ABS */
312
OP(cf) { int tmp; RD_ABS; WB_EA; DCP; WB_EA; } /* 6 DCP ABS */
313
OP(ef) { int tmp; RD_ABS; WB_EA; ISB; WB_EA; } /* 6 ISB ABS */
315
OP(1f) { int tmp; RD_ABX_NP; WB_EA; SLO; WB_EA; } /* 7 SLO ABX */
316
OP(3f) { int tmp; RD_ABX_NP; WB_EA; RLA; WB_EA; } /* 7 RLA ABX */
317
OP(5f) { int tmp; RD_ABX_NP; WB_EA; SRE; WB_EA; } /* 7 SRE ABX */
318
OP(7f) { int tmp; RD_ABX_NP; WB_EA; RRA; WB_EA; } /* 7 RRA ABX */
319
OP(9f) { int tmp; EA_ABY_NP; SAH; WB_EA; } /* 5 SAH ABY */
320
OP(bf) { int tmp; RD_ABY_P; LAX; } /* 4 LAX ABY page penalty */
321
OP(df) { int tmp; RD_ABX_NP; WB_EA; DCP; WB_EA; } /* 7 DCP ABX */
322
OP(ff) { int tmp; RD_ABX_NP; WB_EA; ISB; WB_EA; } /* 7 ISB ABX */
324
/* and here's the array of function pointers */
326
static void (*const insn6502[0x100])(m6502_Regs *cpustate) = {
327
m6502_00,m6502_01,m6502_02,m6502_03,m6502_04,m6502_05,m6502_06,m6502_07,
328
m6502_08,m6502_09,m6502_0a,m6502_0b,m6502_0c,m6502_0d,m6502_0e,m6502_0f,
329
m6502_10,m6502_11,m6502_12,m6502_13,m6502_14,m6502_15,m6502_16,m6502_17,
330
m6502_18,m6502_19,m6502_1a,m6502_1b,m6502_1c,m6502_1d,m6502_1e,m6502_1f,
331
m6502_20,m6502_21,m6502_22,m6502_23,m6502_24,m6502_25,m6502_26,m6502_27,
332
m6502_28,m6502_29,m6502_2a,m6502_2b,m6502_2c,m6502_2d,m6502_2e,m6502_2f,
333
m6502_30,m6502_31,m6502_32,m6502_33,m6502_34,m6502_35,m6502_36,m6502_37,
334
m6502_38,m6502_39,m6502_3a,m6502_3b,m6502_3c,m6502_3d,m6502_3e,m6502_3f,
335
m6502_40,m6502_41,m6502_42,m6502_43,m6502_44,m6502_45,m6502_46,m6502_47,
336
m6502_48,m6502_49,m6502_4a,m6502_4b,m6502_4c,m6502_4d,m6502_4e,m6502_4f,
337
m6502_50,m6502_51,m6502_52,m6502_53,m6502_54,m6502_55,m6502_56,m6502_57,
338
m6502_58,m6502_59,m6502_5a,m6502_5b,m6502_5c,m6502_5d,m6502_5e,m6502_5f,
339
m6502_60,m6502_61,m6502_62,m6502_63,m6502_64,m6502_65,m6502_66,m6502_67,
340
m6502_68,m6502_69,m6502_6a,m6502_6b,m6502_6c,m6502_6d,m6502_6e,m6502_6f,
341
m6502_70,m6502_71,m6502_72,m6502_73,m6502_74,m6502_75,m6502_76,m6502_77,
342
m6502_78,m6502_79,m6502_7a,m6502_7b,m6502_7c,m6502_7d,m6502_7e,m6502_7f,
343
m6502_80,m6502_81,m6502_82,m6502_83,m6502_84,m6502_85,m6502_86,m6502_87,
344
m6502_88,m6502_89,m6502_8a,m6502_8b,m6502_8c,m6502_8d,m6502_8e,m6502_8f,
345
m6502_90,m6502_91,m6502_92,m6502_93,m6502_94,m6502_95,m6502_96,m6502_97,
346
m6502_98,m6502_99,m6502_9a,m6502_9b,m6502_9c,m6502_9d,m6502_9e,m6502_9f,
347
m6502_a0,m6502_a1,m6502_a2,m6502_a3,m6502_a4,m6502_a5,m6502_a6,m6502_a7,
348
m6502_a8,m6502_a9,m6502_aa,m6502_ab,m6502_ac,m6502_ad,m6502_ae,m6502_af,
349
m6502_b0,m6502_b1,m6502_b2,m6502_b3,m6502_b4,m6502_b5,m6502_b6,m6502_b7,
350
m6502_b8,m6502_b9,m6502_ba,m6502_bb,m6502_bc,m6502_bd,m6502_be,m6502_bf,
351
m6502_c0,m6502_c1,m6502_c2,m6502_c3,m6502_c4,m6502_c5,m6502_c6,m6502_c7,
352
m6502_c8,m6502_c9,m6502_ca,m6502_cb,m6502_cc,m6502_cd,m6502_ce,m6502_cf,
353
m6502_d0,m6502_d1,m6502_d2,m6502_d3,m6502_d4,m6502_d5,m6502_d6,m6502_d7,
354
m6502_d8,m6502_d9,m6502_da,m6502_db,m6502_dc,m6502_dd,m6502_de,m6502_df,
355
m6502_e0,m6502_e1,m6502_e2,m6502_e3,m6502_e4,m6502_e5,m6502_e6,m6502_e7,
356
m6502_e8,m6502_e9,m6502_ea,m6502_eb,m6502_ec,m6502_ed,m6502_ee,m6502_ef,
357
m6502_f0,m6502_f1,m6502_f2,m6502_f3,m6502_f4,m6502_f5,m6502_f6,m6502_f7,
358
m6502_f8,m6502_f9,m6502_fa,m6502_fb,m6502_fc,m6502_fd,m6502_fe,m6502_ff