3
Morrow MPZ80 "Decision"
25
- Mult I/O (8259A PIC, 3x 8250 ACE, uPD1990C RTC, 4K ROM/RAM)
27
- DJ/DMA controller (Z80, 1K RAM, 2/4K ROM, TTL floppy control logic) for 5.25" floppy drives
28
- DJ2D/B controller for 8" floppy drives
30
- HDC/DMA controller (Seagate ST-506/Shugart SA1000)
31
- HDCA controller (Shugart SA4000/Fujitsu M2301B/Winchester M2320B)
34
- Decision I Desk Top Model D1 (MPZ80, MM65KS, Wunderbus)
35
- Decision I Desk Top Model D2 (MPZ80, MM65KS, Wunderbus, DJDMA, 2x DSDD 5.25")
36
- Decision I Desk Top Model D2A (MPZ80, MM65KS, Wunderbus, DJDMA, 2x DSDD 5.25", HDCDMA, 5 or 16 MB hard disk?)
37
- Decision I Desk Top Model D3A (MPZ80, MM65KS, Wunderbus, DJDMA, 2x DSDD 5.25", HDCDMA, 5 or 16 MB hard disk?)
38
- Decision I Desk Top Model D3C (MPZ80, MM65KS, Wunderbus, DJDMA, 2x DSDD 5.25", HDCDMA, 5 or 16 MB hard disk?)
42
#include "includes/mpz80.h"
45
//**************************************************************************
47
//**************************************************************************
57
#define TASK0 ((m_task & 0x0f) == 0)
63
#define MASK_STOP_ENBL 0x01
64
#define MASK_AUX_ENBL 0x02
65
#define MASK_TINT_ENBL 0x04
66
#define MASK_RUN_ENBL 0x08
67
#define MASK_HALT_ENBL 0x10
68
#define MASK_SINT_ENBL 0x20
69
#define MASK_IOENBL 0x40
70
#define MASK_ZIO_MODE 0x80
74
//**************************************************************************
76
//**************************************************************************
78
//-------------------------------------------------
80
//-------------------------------------------------
82
inline void mpz80_state::check_traps()
84
m_pretrap = !(m_trap_int & m_trap_halt & m_trap_stop & m_trap_aux);
88
// latch trap condition
89
m_status = m_trap_void;
90
m_status |= m_trap_halt << 2;
91
m_status |= m_trap_int << 3;
92
m_status |= m_trap_stop << 4;
93
m_status |= m_trap_aux << 5;
96
m_pretrap_addr = ((m_addr >> 8) & 0xf0) | (m_pretrap_addr >> 4);
98
// set M1 trap region start address
99
m_trap_start = m_addr;
104
//-------------------------------------------------
106
//-------------------------------------------------
108
inline void mpz80_state::check_interrupt()
110
int tint_enbl = (m_mask & MASK_TINT_ENBL) ? 1 : 0;
111
int sint_enbl = (m_mask & MASK_SINT_ENBL) ? 0 : 1;
113
m_int_pend = !(m_nmi & m_pint);
114
m_trap_int = !(m_int_pend & tint_enbl);
116
int z80irq = CLEAR_LINE;
117
int z80nmi = CLEAR_LINE;
121
if (!m_pint && !sint_enbl) z80irq = ASSERT_LINE;
122
if (!m_nmi && !sint_enbl) z80nmi = ASSERT_LINE;
126
if (!m_pint && !tint_enbl) z80irq = ASSERT_LINE;
127
if (!m_nmi && !tint_enbl) z80nmi = ASSERT_LINE;
130
m_maincpu->set_input_line(INPUT_LINE_IRQ0, z80irq);
131
m_maincpu->set_input_line(INPUT_LINE_NMI, z80nmi);
138
//**************************************************************************
140
//**************************************************************************
142
//-------------------------------------------------
144
//-------------------------------------------------
146
inline offs_t mpz80_state::get_address(offs_t offset)
148
UINT16 map_addr = ((m_task & 0x0f) << 5) | ((offset & 0xf000) >> 11);
149
UINT8 map = m_map_ram[map_addr];
150
//UINT8 attr = m_map_ram[map_addr + 1];
152
//logerror("task %02x map_addr %03x map %02x attr %02x address %06x\n", m_task, map_addr, map, attr, offset);
154
// T7 T6 T5 T4 M7 M6 M5 M4 M3 M2 M1 M0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
155
return ((m_task & 0xf0) << 16) | (map << 12) | (offset & 0xfff);
159
//-------------------------------------------------
161
//-------------------------------------------------
163
READ8_MEMBER( mpz80_state::mmu_r )
165
m_addr = get_address(offset);
166
UINT8 *rom = machine().region(Z80_TAG)->base();
174
// latch trap address
175
m_pretrap_addr = ((m_addr >> 8) & 0xf0) | (m_pretrap_addr >> 4);
176
m_trap_addr = m_pretrap_addr;
179
if (TASK0 && (offset < 0x1000))
183
UINT8 *ram = ram_get_ptr(m_ram);
184
data = ram[offset & 0x3ff];
186
else if (offset == 0x400)
188
data = trap_addr_r(space, 0);
190
else if (offset == 0x401)
192
data = keyboard_r(space, 0);
194
else if (offset == 0x402)
196
data = switch_r(space, 0);
198
else if (offset == 0x403)
200
data = status_r(space, 0);
202
else if (offset >= 0x600 && offset < 0x800)
204
// TODO this might change the map RAM contents
206
else if (offset < 0xc00)
208
UINT16 rom_addr = (m_trap_reset << 10) | (offset & 0x3ff);
209
data = rom[rom_addr];
213
logerror("Unmapped LOCAL read at %06x\n", offset);
218
data = m_s100->smemr_r(space, m_addr);
225
//-------------------------------------------------
227
//-------------------------------------------------
229
WRITE8_MEMBER( mpz80_state::mmu_w )
231
m_addr = get_address(offset);
233
if (TASK0 && (offset < 0x1000))
237
UINT8 *ram = ram_get_ptr(m_ram);
238
ram[offset & 0x3ff] = data;
240
else if (offset == 0x400)
242
disp_seg_w(space, 0, data);
244
else if (offset == 0x401)
246
disp_col_w(space, 0, data);
248
else if (offset == 0x402)
250
task_w(space, 0, data);
252
else if (offset == 0x403)
254
mask_w(space, 0, data);
256
else if (offset >= 0x600 && offset < 0x800)
258
m_map_ram[offset - 0x600] = data;
262
logerror("Unmapped LOCAL write at %06x\n", offset);
267
m_s100->mwrt_w(space, m_addr, data);
272
//-------------------------------------------------
274
//-------------------------------------------------
276
inline offs_t mpz80_state::get_io_address(offs_t offset)
278
if (m_mask & MASK_ZIO_MODE)
280
// echo port address onto upper address lines (8080 emulation)
281
offset = ((offset << 8) & 0xff00) | (offset & 0xff);
288
//-------------------------------------------------
290
//-------------------------------------------------
292
READ8_MEMBER( mpz80_state::mmu_io_r )
294
return m_s100->sinp_r(space, get_io_address(offset));
298
//-------------------------------------------------
300
//-------------------------------------------------
302
WRITE8_MEMBER( mpz80_state::mmu_io_w )
304
m_s100->sout_w(space, get_io_address(offset), data);
308
//-------------------------------------------------
309
// trap_addr_r - trap address register
310
//-------------------------------------------------
312
READ8_MEMBER( mpz80_state::trap_addr_r )
333
//-------------------------------------------------
334
// status_r - trap status register
335
//-------------------------------------------------
337
READ8_MEMBER( mpz80_state::status_r )
358
//-------------------------------------------------
359
// task_w - task register
360
//-------------------------------------------------
362
WRITE8_MEMBER( mpz80_state::task_w )
386
//-------------------------------------------------
387
// mask_w - mask register
388
//-------------------------------------------------
390
WRITE8_MEMBER( mpz80_state::mask_w )
412
//**************************************************************************
414
//**************************************************************************
416
//-------------------------------------------------
417
// keyboard_r - front panel keyboard
418
//-------------------------------------------------
420
READ8_MEMBER( mpz80_state::keyboard_r )
441
//-------------------------------------------------
442
// switch_r - switch register
443
//-------------------------------------------------
445
READ8_MEMBER( mpz80_state::switch_r )
465
data |= m_trap_reset;
468
data |= m_int_pend << 1;
471
data |= input_port_read(machine(), "16C") & 0xfc;
477
//-------------------------------------------------
478
// disp_seg_w - front panel segment
479
//-------------------------------------------------
481
WRITE8_MEMBER( mpz80_state::disp_seg_w )
500
//-------------------------------------------------
501
// disp_col_w - front panel column
502
//-------------------------------------------------
504
WRITE8_MEMBER( mpz80_state::disp_col_w )
524
//**************************************************************************
526
//**************************************************************************
528
//-------------------------------------------------
529
// ADDRESS_MAP( mpz80_mem )
530
//-------------------------------------------------
532
static ADDRESS_MAP_START( mpz80_mem, AS_PROGRAM, 8, mpz80_state )
533
AM_RANGE(0x0000, 0xffff) AM_READWRITE(mmu_r, mmu_w)
535
Task 0 Segment 0 map:
537
AM_RANGE(0x0000, 0x03ff) AM_RAM
538
AM_RANGE(0x0400, 0x0400) AM_READWRITE(trap_addr_r, disp_seg_w)
539
AM_RANGE(0x0401, 0x0401) AM_READWRITE(keyboard_r, disp_col_w)
540
AM_RANGE(0x0402, 0x0402) AM_READWRITE(switch_r, task_w)
541
AM_RANGE(0x0403, 0x0403) AM_READWRITE(status_r, mask_w)
542
AM_RANGE(0x0600, 0x07ff) AM_RAM AM_BASE(m_map_ram)
543
AM_RANGE(0x0800, 0x0bff) AM_ROM AM_REGION(Z80_TAG, 0)
544
AM_RANGE(0x0c00, 0x0c00) AM_DEVREADWRITE(AM9512_TAG, am9512_device, read, write)
549
//-------------------------------------------------
550
// ADDRESS_MAP( mpz80_io )
551
//-------------------------------------------------
553
static ADDRESS_MAP_START( mpz80_io, AS_IO, 8, mpz80_state )
554
AM_RANGE(0x0000, 0xffff) AM_READWRITE(mmu_io_r, mmu_io_w)
559
//**************************************************************************
561
//**************************************************************************
563
//-------------------------------------------------
564
// INPUT_PORTS( mpz80 )
565
//-------------------------------------------------
567
static INPUT_PORTS_START( mpz80 )
569
PORT_DIPNAME( 0xf8, 0xf8, "Power-On-Jump Address" ) PORT_DIPLOCATION("16C:1,2,3,4,5") PORT_CONDITION("12C", 0x02, PORTCOND_EQUALS, 0x02)
570
PORT_DIPSETTING( 0xf8, "F800H" )
571
PORT_DIPSETTING( 0xf0, "F000H" )
572
PORT_DIPSETTING( 0xe8, "E800H" )
573
PORT_DIPSETTING( 0xe0, "E000H" )
574
PORT_DIPSETTING( 0xd8, "D800H" )
575
PORT_DIPSETTING( 0xd0, "D000H" )
576
PORT_DIPSETTING( 0xc8, "C800H" )
577
PORT_DIPSETTING( 0xc0, "C000H" )
578
PORT_DIPSETTING( 0xb8, "B800H" )
579
PORT_DIPSETTING( 0xb0, "B000H" )
580
PORT_DIPSETTING( 0xa8, "A800H" )
581
PORT_DIPSETTING( 0xa0, "A000H" )
582
PORT_DIPSETTING( 0x98, "9800H" )
583
PORT_DIPSETTING( 0x90, "9000H" )
584
PORT_DIPSETTING( 0x88, "8800H" )
585
PORT_DIPSETTING( 0x80, "8000H" )
586
PORT_DIPSETTING( 0x78, "7800H" )
587
PORT_DIPSETTING( 0x70, "7000H" )
588
PORT_DIPSETTING( 0x68, "6800H" )
589
PORT_DIPSETTING( 0x60, "6000H" )
590
PORT_DIPSETTING( 0x58, "5800H" )
591
PORT_DIPSETTING( 0x50, "5000H" )
592
PORT_DIPSETTING( 0x48, "4800H" )
593
PORT_DIPSETTING( 0x40, "4000H" )
594
PORT_DIPSETTING( 0x38, "3800H" )
595
PORT_DIPSETTING( 0x30, "3000H" )
596
PORT_DIPSETTING( 0x28, "2800H" )
597
PORT_DIPSETTING( 0x20, "2000H" )
598
PORT_DIPSETTING( 0x18, "1800H" )
599
PORT_DIPSETTING( 0x10, "Boot DJ/DMA" )
600
PORT_DIPSETTING( 0x08, "Boot HD/DMA" )
601
PORT_DIPSETTING( 0x00, "Boot HDCA" )
602
PORT_DIPNAME( 0x70, 0x00, "Diagnostics" ) PORT_DIPLOCATION("16C:2,3,4") PORT_CONDITION("12C", 0x02, PORTCOND_EQUALS, 0x00)
603
PORT_DIPSETTING( 0x00, "Read Registers" )
604
PORT_DIPSETTING( 0x10, "Write Registers" )
605
PORT_DIPSETTING( 0x20, "Write Map RAMs" )
606
PORT_DIPSETTING( 0x30, "Write R/W RAMs" )
607
PORT_DIPSETTING( 0x40, "R/W FPP" )
608
PORT_DIPSETTING( 0x50, "R/W S-100 Bus (High/Low)" )
609
PORT_DIPSETTING( 0x60, "R/W S-100 Bus (Alternating)" )
610
PORT_DIPSETTING( 0x70, "Read Switches" )
611
PORT_DIPNAME( 0x04, 0x00, "Power Up" ) PORT_DIPLOCATION("16C:6")
612
PORT_DIPSETTING( 0x04, "Boot Address" )
613
PORT_DIPSETTING( 0x00, "Monitor" )
614
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unused ) ) PORT_DIPLOCATION("16C:7")
615
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
616
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
617
PORT_DIPNAME( 0x01, 0x00, "S-100 MWRITE" ) PORT_DIPLOCATION("16C:8")
618
PORT_DIPSETTING( 0x01, "Disabled" )
619
PORT_DIPSETTING( 0x00, "Enabled" )
622
PORT_DIPNAME( 0x02, 0x02, "Operation Mode" )
623
PORT_DIPSETTING( 0x02, "Monitor" )
624
PORT_DIPSETTING( 0x00, "Diagnostic" )
625
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
630
//**************************************************************************
631
// DEVICE CONFIGURATION
632
//**************************************************************************
634
//-------------------------------------------------
635
// floppy_interface floppy_intf
636
//-------------------------------------------------
638
static const floppy_interface floppy_intf =
645
FLOPPY_STANDARD_8_DSDD,
646
FLOPPY_OPTIONS_NAME(default),
651
//-------------------------------------------------
652
// GENERIC_TERMINAL_INTERFACE( terminal_intf )
653
//-------------------------------------------------
655
static GENERIC_TERMINAL_INTERFACE( terminal_intf )
657
DEVCB_DEVICE_MEMBER(S100_TAG, s100_device, terminal_receive_w)
661
//-------------------------------------------------
662
// S100_INTERFACE( s100_intf )
663
//-------------------------------------------------
665
WRITE_LINE_MEMBER( mpz80_state::s100_pint_w )
667
m_pint = (state == ASSERT_LINE) ? 0 : 1;
672
WRITE_LINE_MEMBER( mpz80_state::s100_nmi_w )
674
if (state == ASSERT_LINE)
682
static S100_INTERFACE( s100_intf )
684
DEVCB_DRIVER_LINE_MEMBER(mpz80_state, s100_pint_w),
685
DEVCB_DRIVER_LINE_MEMBER(mpz80_state, s100_nmi_w),
701
DEVCB_DEVICE_HANDLER(TERMINAL_TAG, terminal_write)
704
static SLOT_INTERFACE_START( mpz80_s100_cards )
705
SLOT_INTERFACE("mm65k16s", S100_MM65K16S)
706
SLOT_INTERFACE("wunderbus", S100_WUNDERBUS)
707
SLOT_INTERFACE("dj2db", S100_DJ2DB)
708
SLOT_INTERFACE("djdma", S100_DJDMA)
709
// SLOT_INTERFACE("multio", S100_MULTIO)
710
// SLOT_INTERFACE("hdcdma", S100_HDCDMA)
711
// SLOT_INTERFACE("hdca", S100_HDCA)
716
//**************************************************************************
717
// MACHINE INITIALIZATION
718
//**************************************************************************
720
//-------------------------------------------------
721
// MACHINE_START( mpz80 )
722
//-------------------------------------------------
724
void mpz80_state::machine_start()
726
m_map_ram = auto_alloc_array_clear(machine(), UINT8, 0x200);
730
//-------------------------------------------------
731
// MACHINE_RESET( mpz80 )
732
//-------------------------------------------------
734
void mpz80_state::machine_reset()
747
//**************************************************************************
749
//**************************************************************************
751
//-------------------------------------------------
752
// MACHINE_CONFIG( mpz80 )
753
//-------------------------------------------------
755
static MACHINE_CONFIG_START( mpz80, mpz80_state )
756
// basic machine hardware
757
MCFG_CPU_ADD(Z80_TAG, Z80, XTAL_4MHz)
758
MCFG_CPU_PROGRAM_MAP(mpz80_mem)
759
MCFG_CPU_IO_MAP(mpz80_io)
762
MCFG_FRAGMENT_ADD( generic_terminal )
765
MCFG_S100_BUS_ADD(Z80_TAG, s100_intf)
766
MCFG_S100_SLOT_ADD( 1, "s100_1", mpz80_s100_cards, "mm65k16s")
767
MCFG_S100_SLOT_ADD( 2, "s100_2", mpz80_s100_cards, "wunderbus")
768
MCFG_S100_SLOT_ADD( 3, "s100_3", mpz80_s100_cards, "dj2db")
769
MCFG_S100_SLOT_ADD( 4, "s100_4", mpz80_s100_cards, NULL)//"hdcdma")
770
MCFG_S100_SLOT_ADD( 5, "s100_5", mpz80_s100_cards, NULL)
771
MCFG_S100_SLOT_ADD( 6, "s100_6", mpz80_s100_cards, NULL)
772
MCFG_S100_SLOT_ADD( 7, "s100_7", mpz80_s100_cards, NULL)
773
MCFG_S100_SLOT_ADD( 8, "s100_8", mpz80_s100_cards, NULL)
774
MCFG_S100_SLOT_ADD( 9, "s100_9", mpz80_s100_cards, NULL)
775
MCFG_S100_SLOT_ADD(10, "s100_10", mpz80_s100_cards, NULL)
776
MCFG_S100_SLOT_ADD(11, "s100_11", mpz80_s100_cards, NULL)
777
MCFG_S100_SLOT_ADD(12, "s100_12", mpz80_s100_cards, NULL)
778
MCFG_S100_SLOT_ADD(13, "s100_13", mpz80_s100_cards, NULL)
779
MCFG_S100_SLOT_ADD(14, "s100_14", mpz80_s100_cards, NULL)
782
MCFG_FLOPPY_2_DRIVES_ADD(floppy_intf)
783
MCFG_GENERIC_TERMINAL_ADD(TERMINAL_TAG, terminal_intf)
786
MCFG_RAM_ADD(RAM_TAG)
787
MCFG_RAM_DEFAULT_SIZE("65K")
790
MCFG_SOFTWARE_LIST_ADD("flop_list", "mpz80")
795
//**************************************************************************
797
//**************************************************************************
799
//-------------------------------------------------
801
//-------------------------------------------------
804
ROM_REGION( 0x1000, Z80_TAG, 0 )
805
ROM_DEFAULT_BIOS("447")
806
ROM_SYSTEM_BIOS( 0, "373", "3.73" )
807
ROMX_LOAD( "mpz80 mon3.73 fb34.17c", 0x0000, 0x1000, CRC(0bbffaec) SHA1(005ba726fc071f06cb1c969d170960438a3fc1a8), ROM_BIOS(1) )
808
ROM_SYSTEM_BIOS( 1, "375", "3.75" )
809
ROMX_LOAD( "mpz80 mon3.75 0706.17c", 0x0000, 0x1000, CRC(1118a592) SHA1(d70f94c09602cd0bdc4fbaeb14989e8cc1540960), ROM_BIOS(2) )
810
ROM_SYSTEM_BIOS( 2, "447", "4.47" )
811
ROMX_LOAD( "mon 4.47 f4f6.17c", 0x0000, 0x1000, CRC(b99c5d7f) SHA1(11181432ee524c7e5a68ead0671fc945256f5d1b), ROM_BIOS(3) )
813
ROM_REGION( 0x20, "proms", 0 )
814
ROM_LOAD( "z80-2 15a.15a", 0x00, 0x20, CRC(8a84249d) SHA1(dfbc49c5944f110f48419fd893fa84f4f0e113b8) ) // this is actually the 6331 PROM?
816
ROM_REGION( 0x20, "plds", 0 )
817
ROM_LOAD( "z80-2 5c.5c", 0x00, 0x20, NO_DUMP )
822
//**************************************************************************
823
// DRIVER INITIALIZATION
824
//**************************************************************************
826
//-------------------------------------------------
827
// DRIVER_INIT( abc800c )
828
//-------------------------------------------------
830
DIRECT_UPDATE_HANDLER( mpz80_direct_update_handler )
832
mpz80_state *state = machine.driver_data<mpz80_state>();
834
if (state->m_trap && address >= state->m_trap_start && address <= state->m_trap_start + 0xf)
836
direct.explicit_configure(state->m_trap_start, state->m_trap_start + 0xf, 0xf, machine.region(Z80_TAG)->base() + ((state->m_trap_reset << 10) | 0x3f0));
843
static DRIVER_INIT( mpz80 )
845
address_space *program = machine.device<cpu_device>(Z80_TAG)->space(AS_PROGRAM);
846
program->set_direct_update_handler(direct_update_delegate(FUNC(mpz80_direct_update_handler), &machine));
851
//**************************************************************************
853
//**************************************************************************
855
// YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS
856
COMP( 1980, mpz80, 0, 0, mpz80, mpz80, mpz80, "Morrow Designs", "MPZ80", GAME_NOT_WORKING | GAME_NO_SOUND_HW )