1
/**************************************************************************\
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* Texas Instruments TMS320x25 DSP Emulator *
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* Copyright Tony La Porta *
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* Written for the MAME project. *
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* Three versions of the chip are available, and they are: *
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* TMS320C25 Internal ROM one time programmed at TI *
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* TMS320E25 Internal ROM programmable as a normal EPROM *
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* TMS320P25 Internal ROM programmable once as a normal EPROM only *
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* These devices can also be used as a MicroController with external ROM *
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* Notes : The term 'DMA' within this document, is in reference *
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* to Direct Memory Addressing, and NOT the usual term *
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* of Direct Memory Access. *
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* This is a word based microcontroller, with addressing *
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* architecture based on the Harvard addressing scheme. *
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* **** Change Log **** *
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* - Work began on this emulator *
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* - First private release *
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* TLP (xx-Dec-2001) Ver 0.11 *
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* - Various undocumented fixes *
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* TLP (13-Jul-2002) Ver 0.12 *
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* - Corrected IRQ2 vector pointer *
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* - Fixed the signedness in many equation based instructions *
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* - Adjusted the level sensing for the Signal inputs *
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* - Added the ability to view the CPU in the debugger when it's halted *
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* - First public release after nearly 1.5 years! *
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* - Adjusted more signedness instructions (ADDH, SUBC, SUBH, etc) *
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* - Added memory banking for the CNFD, CNFP and CONF instructions *
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* - Corrected IRQ masking checks *
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* TLP (25-Dec-2002) Ver 1.10 *
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* - Added internal timer *
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\**************************************************************************/
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/*****************************************************************************
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To fix, or currently lacking from this emulator are:
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Fix the levels for S_IN and S_OUT - use assert/release line
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# Support for the built in Timer/Counter Page 91
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When idling, Counter must still be activly counting down. When counter
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reaches 0 it should issue a TINT (if it's not masked), then come out of
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If TINT is masked, the Timer still needs to count down.
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# Support for the built in Serial Port
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# Support for the Global memory register
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# Support for the switch for RAM block 0 banking between RAM and ROM space
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# Correct the multi-cycle instruction cycle counts
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# Add support to set ROM & RAM as Internal/External in order to correctly
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# Check (read) Hold signal level during execution loop ?
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# Add/fix other things I forgot
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*****************************************************************************/
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TMS32025 CONF Mode Decoding Table
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|=======================================|
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| Status bit | Blocks |
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| CNF | B0 | B1 | B2 |
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|------------+---------+---------+------|
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| 0 0 | data | data | data |
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| 1 1 | program | data | data |
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|=======================================|
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TMS32026 CONF Mode Decoding Table
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|==================================================|
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| Status bits | Blocks |
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| CNF1 | CNF0 | B0 | B1 | B2 | B3 |
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|------+------+---------+---------+------+---------|
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| 0 | 0 | data | data | data | data |
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| 0 | 1 | program | data | data | data |
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| 1 | 0 | program | program | data | data |
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| 1 | 1 | program | program | data | program |
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|==================================================|
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Table 3-2. TMS32025/26 Memory Blocks
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|=========================================================|
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| Configured As Data Memory |
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|-------+-------TMS320C25--------+-------TMS320C26--------|
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| | | Hexadecimal | | Hexadecimal |
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| Block | Pages | Address | Pages | Address |
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|-------+---------+--------------+---------+--------------|
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| B2 | 0 | 0060h-007Fh | 0 | 0060h-007Fh |
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| B0 | 4-5 | 0200h-02FFh | 4-7 | 0200h-03FFh |
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| B1 | 6-7 | 0300h-03FFh | 8-11 | 0400h-05FFh |
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| B3 | B3 does not exist | 12-15 | 0600h-07FFh |
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|=========================================================|
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| Configured As Program Memory |
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|-------+-------TMS320C25--------+-------TMS320C26--------|
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| | | Hexadecimal | | Hexadecimal |
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| Block | Pages | Address | Pages | Address |
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|-------+---------+--------------+---------+--------------|
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| B2 | B2 is not configurable | B2 is not configurable |
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| B0 | 510-511 | FF00h-FFFFh | 500-503 | FA00h-FBFFh |
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| B1 | B1 is not configurable | 504-507 | FC00h-FDFFh |
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| B3 | B3 does not exist | 508-511 | FE00h-FFFFh |
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|=========================================================|
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#include "debugger.h"
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#include "tms32025.h"
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#define CLK 4 /* 1 cycle equals 4 clock ticks */ /* PE/DI */
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#define SET_PC(x) do { cpustate->PC = (x); } while (0)
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#define P_IN(A) (cpustate->io->read_word((A)<<1))
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#define P_OUT(A,V) (cpustate->io->write_word(((A)<<1),(V)))
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#define S_IN(A) (cpustate->io->read_word((A)<<1))
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#define S_OUT(A,V) (cpustate->io->write_word(((A)<<1),(V)))
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#define M_RDOP(A) ((cpustate->pgmmap[(A) >> 7]) ? (cpustate->pgmmap[(A) >> 7][(A) & 0x7f]) : cpustate->direct->read_decrypted_word((A)<<1))
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#define M_RDOP_ARG(A) ((cpustate->pgmmap[(A) >> 7]) ? (cpustate->pgmmap[(A) >> 7][(A) & 0x7f]) : cpustate->direct->read_decrypted_word((A)<<1))
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typedef struct _tms32025_state tms32025_state; /* Page 3-6 (45) shows all registers */
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struct _tms32025_state
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/******************** CPU Internal Registers *******************/
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UINT16 PREVPC; /* previous program counter */
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/********************** Status data ****************************/
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int external_mem_access; /** required for hold mode. Implement it ! */
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int init_load_addr; /* 0=No, 1=Yes, 2=Once for repeat mode */
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int tms32025_irq_cycles;
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int tms32025_dec_cycles;
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device_irq_callback irq_callback;
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int mHackIgnoreARP; /* special handling for lst, lst1 instructions */
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int waiting_for_serial_frame;
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legacy_cpu_device *device;
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address_space *program;
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direct_read_data *direct;
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UINT16 *pgmmap[0x200];
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UINT16 *datamap[0x200];
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INLINE tms32025_state *get_safe_token(device_t *device)
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assert(device != NULL);
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assert(device->type() == TMS32025 ||
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device->type() == TMS32026);
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return (tms32025_state *)downcast<legacy_cpu_device *>(device)->token();
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/* opcode table entry */
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typedef struct _tms32025_opcode tms32025_opcode;
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struct _tms32025_opcode
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void (*function)(tms32025_state *);
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/* opcode table entry (Opcode CE has sub-opcodes) */
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typedef struct _tms32025_opcode_CE tms32025_opcode_CE;
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struct _tms32025_opcode_CE
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void (*function)(tms32025_state *);
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/* opcode table entry (Opcode Dx has sub-opcodes) */
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typedef struct _tms32025_opcode_Dx tms32025_opcode_Dx;
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struct _tms32025_opcode_Dx
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void (*function)(tms32025_state *);
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/************************** Memory mapped registers ****************/
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#define DRR cpustate->intRAM[0]
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#define DXR cpustate->intRAM[1]
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#define TIM cpustate->intRAM[2]
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#define PRD cpustate->intRAM[3]
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#define IMR cpustate->intRAM[4]
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#define GREG cpustate->intRAM[5]
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/****************************************************************************
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******* The following is the Status (Flag) register 0 definition. ********
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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| <----ARP---> | OV | OVM | 1 | INTM | <--------------DP---------------> | */
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#define ARP_REG 0xe000 /* ARP (Auxiliary Register Pointer) */
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#define OV_FLAG 0x1000 /* OV (Overflow flag) 1 indicates an overflow */
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#define OVM_FLAG 0x0800 /* OVM (Overflow Mode bit) 1 forces ACC overflow to greatest positive or negative saturation value */
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#define INTM_FLAG 0x0200 /* INTM (Interrupt Mask flag) 0 enables maskable interrupts */
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#define DP_REG 0x01ff /* DP (Data bank memory Pointer) */
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/***********************************************************************************
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*** The following is the Status (Flag) register 1 definition for TMS32025. ********
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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| <----ARB---> | CNF0 | TC | SXM | C | 1 | 1 | HM | FSM | XF | FO | TXM | <-PM-> | */
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/*** The following is the Status (Flag) register 1 definition for TMS32026. ***********
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| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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| <----ARB---> | CNF0 | TC | SXM | C | 1 | CNF1 | HM | FSM | XF | FO | TXM | <-PM-> | */
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#define ARB_REG 0xe000 /* ARB (Auxiliary Register pointer Backup) */
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#define CNF0_REG 0x1000 /* CNF0 (Onchip RAM CoNFiguration) 0 means B0=data memory, 1means B0=program memory */
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#define CNF1_REG 0x0080 /* CNF1 (Onchip RAM CoNFiguration) 0 means B0=data memory, 1means B0=program memory */
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#define TC_FLAG 0x0800 /* TC (Test Control flag) */
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#define SXM_FLAG 0x0400 /* SXM (Sign eXtension Mode) */
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#define C_FLAG 0x0200 /* C (Carry flag) */
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#define HM_FLAG 0x0040 /* HM (Processor Hold Mode) */
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#define FSM_FLAG 0x0020 /* FSM (Frame Synchronization Mode - for serial port) */
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#define XF_FLAG 0x0010 /* XF (XF output pin status) */
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#define FO_FLAG 0x0008 /* FO (Serial port Format In/Out mode) */
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#define TXM_FLAG 0x0004 /* TXM (Transmit Mode - for serial port) */
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#define PM_REG 0x0003 /* PM (Product shift Mode) */
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#define OV ( cpustate->STR0 & OV_FLAG) /* OV (Overflow flag) */
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#define OVM ( cpustate->STR0 & OVM_FLAG) /* OVM (Overflow Mode bit) 1 indicates an overflow */
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#define INTM ( cpustate->STR0 & INTM_FLAG) /* INTM (Interrupt enable flag) 0 enables maskable interrupts */
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#define ARP ((cpustate->STR0 & ARP_REG) >> 13) /* ARP (Auxiliary Register Pointer) */
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#define DP ((cpustate->STR0 & DP_REG) << 7) /* DP (Data memory Pointer bit) */
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#define ARB ( cpustate->STR1 & ARB_REG) /* ARB (Backup Auxiliary Register pointer) */
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#define CNF0 ( cpustate->STR1 & CNF0_REG) /* CNF0 (Onchip Ram Config register) */
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#define TC ( cpustate->STR1 & TC_FLAG) /* TC (Test Control Flag) */
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#define SXM ( cpustate->STR1 & SXM_FLAG) /* SXM (Sign Extension Mode) */
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#define CARRY ( cpustate->STR1 & C_FLAG) /* C (Carry Flag for accumulator) */
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#define HM ( cpustate->STR1 & HM_FLAG) /* HM (Processor Hold Mode) */
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#define FSM ( cpustate->STR1 & FSM_FLAG) /* FSM (Frame Synchronization Mode - for serial port) */
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#define XF ( cpustate->STR1 & FSM_FLAG) /* XF (XF output pin status) */
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#define FO ( cpustate->STR1 & FO_FLAG) /* FO (Serial port Format In/Out mode) */
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#define TXM ( cpustate->STR1 & TXM_FLAG) /* TXM (Transmit Mode - for serial port) */
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#define PM ( cpustate->STR1 & PM_REG) /* PM (P register shift Mode. See SHIFT_Preg_TO_ALU below )*/
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#define DMA (DP | (cpustate->opcode.b.l & 0x7f)) /* address used in direct memory access operations */
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#define DMApg0 (cpustate->opcode.b.l & 0x7f) /* address used in direct memory access operations for sst instruction */
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#define IND cpustate->AR[ARP] /* address used in indirect memory access operations */
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INLINE void CLR0(tms32025_state *cpustate, UINT16 flag) { cpustate->STR0 &= ~flag; cpustate->STR0 |= 0x0400; }
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INLINE void SET0(tms32025_state *cpustate, UINT16 flag) { cpustate->STR0 |= flag; cpustate->STR0 |= 0x0400; }
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INLINE void CLR1(tms32025_state *cpustate, UINT16 flag) { cpustate->STR1 &= ~flag; cpustate->STR1 |= 0x0180; }
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INLINE void SET1(tms32025_state *cpustate, UINT16 flag) { cpustate->STR1 |= flag; cpustate->STR1 |= 0x0180; }
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INLINE void MODIFY_DP(tms32025_state *cpustate, int data)
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cpustate->STR0 &= ~DP_REG;
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cpustate->STR0 |= (data & DP_REG);
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cpustate->STR0 |= 0x0400;
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INLINE void MODIFY_PM(tms32025_state *cpustate, int data)
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cpustate->STR1 &= ~PM_REG;
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cpustate->STR1 |= (data & PM_REG);
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cpustate->STR1 |= 0x0180;
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INLINE void MODIFY_ARP(tms32025_state *cpustate, int data)
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cpustate->STR1 &= ~ARB_REG;
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cpustate->STR1 |= (cpustate->STR0 & ARP_REG);
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cpustate->STR1 |= 0x0180;
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cpustate->STR0 &= ~ARP_REG;
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cpustate->STR0 |= ((data << 13) & ARP_REG);
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cpustate->STR0 |= 0x0400;
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#ifdef UNUSED_FUNCTION
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INLINE void MODIFY_ARB(tms32025_state *cpustate, int data)
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cpustate->STR1 &= ~ARB_REG;
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cpustate->STR1 |= ((data << 13) & ARB_REG);
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cpustate->STR1 |= 0x0180;
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INLINE UINT16 M_RDROM(tms32025_state *cpustate, offs_t addr)
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ram = cpustate->pgmmap[addr >> 7];
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if (ram) return ram[addr & 0x7f];
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return cpustate->program->read_word(addr << 1);
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INLINE void M_WRTROM(tms32025_state *cpustate, offs_t addr, UINT16 data)
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ram = cpustate->pgmmap[addr >> 7];
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if (ram) { ram[addr & 0x7f] = data; }
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else cpustate->program->write_word(addr << 1, data);
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INLINE UINT16 M_RDRAM(tms32025_state *cpustate, offs_t addr)
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ram = cpustate->datamap[addr >> 7];
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if (ram) return ram[addr & 0x7f];
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return cpustate->data->read_word(addr << 1);
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INLINE void M_WRTRAM(tms32025_state *cpustate, offs_t addr, UINT16 data)
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ram = cpustate->datamap[addr >> 7];
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ram[addr & 0x7f] = data;
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if(addr == 1 && ram == cpustate->intRAM && TXM) {
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cpustate->waiting_for_serial_frame = 1;
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cpustate->IFR |= 0x20;
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else cpustate->data->write_word(addr << 1, data);
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static UINT16 reverse_carry_add(UINT16 arg0, UINT16 arg1 )
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for( count=0; count<16; count++ )
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int sum = (arg0>>15)+(arg1>>15)+carry;
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result = (result<<1)|(sum&1);
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INLINE void MODIFY_AR_ARP(tms32025_state *cpustate)
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{ /* modify address register referenced by ARP */
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switch (cpustate->opcode.b.l & 0x70) /* Cases ordered by predicted useage */
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case 0x00: /* 000 nop */
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case 0x10: /* 001 *- */
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cpustate->AR[ARP] -- ;
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case 0x20: /* 010 *+ */
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cpustate->AR[ARP] ++ ;
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case 0x30: /* 011 reserved */
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case 0x40: /* 100 *BR0- */
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cpustate->AR[ARP] = reverse_carry_add(cpustate->AR[ARP],-cpustate->AR[0]);
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case 0x50: /* 101 *0- */
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cpustate->AR[ARP] -= cpustate->AR[0];
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case 0x60: /* 110 *0+ */
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cpustate->AR[ARP] += cpustate->AR[0];
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case 0x70: /* 111 *BR0+ */
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cpustate->AR[ARP] += reverse_carry_add(cpustate->AR[ARP],cpustate->AR[0]);
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if( !cpustate->mHackIgnoreARP )
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if (cpustate->opcode.b.l & 8)
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{ /* bit 3 determines if new value is loaded into ARP */
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MODIFY_ARP(cpustate, (cpustate->opcode.b.l & 7) );
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INLINE void CALCULATE_ADD_CARRY(tms32025_state *cpustate)
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if ( (UINT32)(cpustate->oldacc.d) > (UINT32)(cpustate->ACC.d) ) {
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SET1(cpustate, C_FLAG);
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CLR1(cpustate, C_FLAG);
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INLINE void CALCULATE_SUB_CARRY(tms32025_state *cpustate)
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if ( (UINT32)(cpustate->oldacc.d) < (UINT32)(cpustate->ACC.d) ) {
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CLR1(cpustate, C_FLAG);
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SET1(cpustate, C_FLAG);
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INLINE void CALCULATE_ADD_OVERFLOW(tms32025_state *cpustate, INT32 addval)
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if ((INT32)(~(cpustate->oldacc.d ^ addval) & (cpustate->oldacc.d ^ cpustate->ACC.d)) < 0)
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SET0(cpustate, OV_FLAG);
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// Stroff:HACK! support for overflow capping as implemented results in bad DSP floating point math in many
458
// System22 games - for example, the score display in Prop Cycle.
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// cpustate->ACC.d = ((INT32)cpustate->oldacc.d < 0) ? 0x80000000 : 0x7fffffff;
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INLINE void CALCULATE_SUB_OVERFLOW(tms32025_state *cpustate, INT32 subval)
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if ((INT32)((cpustate->oldacc.d ^ subval) & (cpustate->oldacc.d ^ cpustate->ACC.d)) < 0)
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SET0(cpustate, OV_FLAG);
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cpustate->ACC.d = ((INT32)cpustate->oldacc.d < 0) ? 0x80000000 : 0x7fffffff;
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INLINE UINT16 POP_STACK(tms32025_state *cpustate)
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UINT16 data = cpustate->STACK[7];
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cpustate->STACK[7] = cpustate->STACK[6];
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cpustate->STACK[6] = cpustate->STACK[5];
480
cpustate->STACK[5] = cpustate->STACK[4];
481
cpustate->STACK[4] = cpustate->STACK[3];
482
cpustate->STACK[3] = cpustate->STACK[2];
483
cpustate->STACK[2] = cpustate->STACK[1];
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cpustate->STACK[1] = cpustate->STACK[0];
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INLINE void PUSH_STACK(tms32025_state *cpustate, UINT16 data)
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cpustate->STACK[0] = cpustate->STACK[1];
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cpustate->STACK[1] = cpustate->STACK[2];
491
cpustate->STACK[2] = cpustate->STACK[3];
492
cpustate->STACK[3] = cpustate->STACK[4];
493
cpustate->STACK[4] = cpustate->STACK[5];
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cpustate->STACK[5] = cpustate->STACK[6];
495
cpustate->STACK[6] = cpustate->STACK[7];
496
cpustate->STACK[7] = data;
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INLINE void SHIFT_Preg_TO_ALU(tms32025_state *cpustate)
501
switch(PM) /* PM (in STR1) is the shift mode for Preg */
503
case 0: cpustate->ALU.d = cpustate->Preg.d; break;
504
case 1: cpustate->ALU.d = (cpustate->Preg.d << 1); break;
505
case 2: cpustate->ALU.d = (cpustate->Preg.d << 4); break;
506
case 3: cpustate->ALU.d = (cpustate->Preg.d >> 6); if (cpustate->Preg.d & 0x80000000) cpustate->ALU.d |= 0xfc000000; break;
511
INLINE void GETDATA(tms32025_state *cpustate, int shift,int signext)
513
if (cpustate->opcode.b.l & 0x80)
514
{ /* indirect memory access */
515
cpustate->memaccess = IND;
518
{ /* direct memory address */
519
cpustate->memaccess = DMA;
522
if (cpustate->memaccess >= 0x800)
524
cpustate->external_mem_access = 1; /* Pause if hold pin is active */
528
cpustate->external_mem_access = 0;
531
cpustate->ALU.d = (UINT16)M_RDRAM(cpustate, cpustate->memaccess);
532
if (signext) cpustate->ALU.d = (INT16)cpustate->ALU.d;
533
cpustate->ALU.d <<= shift;
536
if (cpustate->opcode.b.l & 0x80) MODIFY_AR_ARP(cpustate);
539
INLINE void PUTDATA(tms32025_state *cpustate, UINT16 data)
541
if (cpustate->opcode.b.l & 0x80) {
542
if (cpustate->memaccess >= 0x800) cpustate->external_mem_access = 1; /* Pause if hold pin is active */
543
else cpustate->external_mem_access = 0;
545
M_WRTRAM(cpustate, IND, data);
546
MODIFY_AR_ARP(cpustate);
549
if (cpustate->memaccess >= 0x800) cpustate->external_mem_access = 1; /* Pause if hold pin is active */
550
else cpustate->external_mem_access = 0;
552
M_WRTRAM(cpustate, DMA, data);
555
INLINE void PUTDATA_SST(tms32025_state *cpustate, UINT16 data)
557
if (cpustate->opcode.b.l & 0x80) cpustate->memaccess = IND;
558
else cpustate->memaccess = DMApg0;
560
if (cpustate->memaccess >= 0x800) cpustate->external_mem_access = 1; /* Pause if hold pin is active */
561
else cpustate->external_mem_access = 0;
563
if (cpustate->opcode.b.l & 0x80) {
564
cpustate->opcode.b.l &= 0xf7; /* Stop ARP changes */
565
MODIFY_AR_ARP(cpustate);
567
M_WRTRAM(cpustate, cpustate->memaccess, data);
571
/* The following functions are here to fill the void for the */
572
/* opcode call functions. These functions are never actually called. */
573
static void opcodes_CE(tms32025_state *cpustate) { }
574
static void opcodes_Dx(tms32025_state *cpustate) { }
576
static void illegal(tms32025_state *cpustate)
578
logerror("TMS32025: PC = %04x, Illegal opcode = %04x\n", (cpustate->PC-1), cpustate->opcode.w.l);
581
static void abst(tms32025_state *cpustate)
583
if ( (INT32)(cpustate->ACC.d) < 0 ) {
584
cpustate->ACC.d = -cpustate->ACC.d;
585
if (cpustate->ACC.d == 0x80000000) {
586
SET0(cpustate, OV_FLAG);
587
if (OVM) cpustate->ACC.d-- ;
590
CLR1(cpustate, C_FLAG);
592
static void add(tms32025_state *cpustate) /* #### add carry support - see page 3-31 (70) #### */
593
{ /* page 10-13 (348) spru031d */
594
cpustate->oldacc.d = cpustate->ACC.d;
595
GETDATA(cpustate, (cpustate->opcode.b.h & 0xf), SXM);
596
cpustate->ACC.d += cpustate->ALU.d;
598
CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
599
CALCULATE_ADD_CARRY(cpustate);
601
static void addc(tms32025_state *cpustate)
603
cpustate->oldacc.d = cpustate->ACC.d;
604
GETDATA(cpustate, 0, 0);
605
if (CARRY) cpustate->ALU.d++;
606
cpustate->ACC.d += cpustate->ALU.d;
607
CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
608
CALCULATE_ADD_CARRY(cpustate);
610
static void addh(tms32025_state *cpustate)
612
cpustate->oldacc.d = cpustate->ACC.d;
613
GETDATA(cpustate, 0, 0);
614
cpustate->ACC.w.h += cpustate->ALU.w.l;
615
if ((INT16)(~(cpustate->oldacc.w.h ^ cpustate->ALU.w.l) & (cpustate->oldacc.w.h ^ cpustate->ACC.w.h)) < 0) {
616
SET0(cpustate, OV_FLAG);
618
cpustate->ACC.w.h = ((INT16)cpustate->oldacc.w.h < 0) ? 0x8000 : 0x7fff;
620
if ( ((INT16)(cpustate->oldacc.w.h) < 0) && ((INT16)(cpustate->ACC.w.h) >= 0) ) {
621
SET1(cpustate, C_FLAG);
623
/* Carry flag is not cleared, if no carry occured */
625
static void addk(tms32025_state *cpustate)
627
cpustate->oldacc.d = cpustate->ACC.d;
628
cpustate->ALU.d = (UINT8)cpustate->opcode.b.l;
629
cpustate->ACC.d += cpustate->ALU.d;
630
CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
631
CALCULATE_ADD_CARRY(cpustate);
633
static void adds(tms32025_state *cpustate)
635
cpustate->oldacc.d = cpustate->ACC.d;
636
GETDATA(cpustate, 0, 0);
637
cpustate->ACC.d += cpustate->ALU.d;
638
CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
639
CALCULATE_ADD_CARRY(cpustate);
641
static void addt(tms32025_state *cpustate)
643
cpustate->oldacc.d = cpustate->ACC.d;
644
GETDATA(cpustate, (cpustate->Treg & 0xf), SXM);
645
cpustate->ACC.d += cpustate->ALU.d;
646
CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
647
CALCULATE_ADD_CARRY(cpustate);
649
static void adlk(tms32025_state *cpustate)
651
cpustate->oldacc.d = cpustate->ACC.d;
652
if (SXM) cpustate->ALU.d = (INT16)M_RDOP_ARG(cpustate->PC);
653
else cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC);
655
cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf);
656
cpustate->ACC.d += cpustate->ALU.d;
657
CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
658
CALCULATE_ADD_CARRY(cpustate);
660
static void adrk(tms32025_state *cpustate)
662
cpustate->AR[ARP] += cpustate->opcode.b.l;
664
static void and_(tms32025_state *cpustate)
666
GETDATA(cpustate, 0, 0);
667
cpustate->ACC.d &= cpustate->ALU.d;
669
static void andk(tms32025_state *cpustate)
671
cpustate->oldacc.d = cpustate->ACC.d;
672
cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC);
674
cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf);
675
cpustate->ACC.d &= cpustate->ALU.d;
676
cpustate->ACC.d &= 0x7fffffff;
678
static void apac(tms32025_state *cpustate)
680
cpustate->oldacc.d = cpustate->ACC.d;
681
SHIFT_Preg_TO_ALU(cpustate);
682
cpustate->ACC.d += cpustate->ALU.d;
683
CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
684
CALCULATE_ADD_CARRY(cpustate);
686
static void br(tms32025_state *cpustate)
688
SET_PC(M_RDOP_ARG(cpustate->PC));
689
MODIFY_AR_ARP(cpustate);
691
static void bacc(tms32025_state *cpustate)
693
SET_PC(cpustate->ACC.w.l);
695
static void banz(tms32025_state *cpustate)
697
if (cpustate->AR[ARP]) SET_PC(M_RDOP_ARG(cpustate->PC));
698
else cpustate->PC++ ;
699
MODIFY_AR_ARP(cpustate);
701
static void bbnz(tms32025_state *cpustate)
703
if (TC) SET_PC(M_RDOP_ARG(cpustate->PC));
704
else cpustate->PC++ ;
705
MODIFY_AR_ARP(cpustate);
707
static void bbz(tms32025_state *cpustate)
709
if (TC == 0) SET_PC(M_RDOP_ARG(cpustate->PC));
710
else cpustate->PC++ ;
711
MODIFY_AR_ARP(cpustate);
713
static void bc(tms32025_state *cpustate)
715
if (CARRY) SET_PC(M_RDOP_ARG(cpustate->PC));
716
else cpustate->PC++ ;
717
MODIFY_AR_ARP(cpustate);
719
static void bgez(tms32025_state *cpustate)
721
if ( (INT32)(cpustate->ACC.d) >= 0 ) SET_PC(M_RDOP_ARG(cpustate->PC));
722
else cpustate->PC++ ;
723
MODIFY_AR_ARP(cpustate);
725
static void bgz(tms32025_state *cpustate)
727
if ( (INT32)(cpustate->ACC.d) > 0 ) SET_PC(M_RDOP_ARG(cpustate->PC));
728
else cpustate->PC++ ;
729
MODIFY_AR_ARP(cpustate);
731
static void bioz(tms32025_state *cpustate)
733
if (S_IN(TMS32025_BIO) != CLEAR_LINE) SET_PC(M_RDOP_ARG(cpustate->PC));
734
else cpustate->PC++ ;
735
MODIFY_AR_ARP(cpustate);
737
static void bit(tms32025_state *cpustate)
739
GETDATA(cpustate, 0, 0);
740
if (cpustate->ALU.d & (0x8000 >> (cpustate->opcode.b.h & 0xf))) SET1(cpustate, TC_FLAG);
741
else CLR1(cpustate, TC_FLAG);
743
static void bitt(tms32025_state *cpustate)
745
GETDATA(cpustate, 0, 0);
746
if (cpustate->ALU.d & (0x8000 >> (cpustate->Treg & 0xf))) SET1(cpustate, TC_FLAG);
747
else CLR1(cpustate, TC_FLAG);
749
static void blez(tms32025_state *cpustate)
751
if ( (INT32)(cpustate->ACC.d) <= 0 ) SET_PC(M_RDOP_ARG(cpustate->PC));
752
else cpustate->PC++ ;
753
MODIFY_AR_ARP(cpustate);
755
static void blkd(tms32025_state *cpustate)
756
{ /** Fix cycle timing **/
757
if (cpustate->init_load_addr) {
758
cpustate->PFC = M_RDOP_ARG(cpustate->PC);
761
cpustate->ALU.d = M_RDRAM(cpustate, cpustate->PFC);
762
PUTDATA(cpustate, cpustate->ALU.d);
764
cpustate->tms32025_dec_cycles += (1*CLK);
766
static void blkp(tms32025_state *cpustate)
767
{ /** Fix cycle timing **/
768
if (cpustate->init_load_addr) {
769
cpustate->PFC = M_RDOP_ARG(cpustate->PC);
772
cpustate->ALU.d = M_RDROM(cpustate, cpustate->PFC);
773
PUTDATA(cpustate, cpustate->ALU.d);
775
cpustate->tms32025_dec_cycles += (2*CLK);
777
static void blz(tms32025_state *cpustate)
779
if ( (INT32)(cpustate->ACC.d) < 0 ) SET_PC(M_RDOP_ARG(cpustate->PC));
780
else cpustate->PC++ ;
781
MODIFY_AR_ARP(cpustate);
783
static void bnc(tms32025_state *cpustate)
785
if (CARRY == 0) SET_PC(M_RDOP_ARG(cpustate->PC));
786
else cpustate->PC++ ;
787
MODIFY_AR_ARP(cpustate);
789
static void bnv(tms32025_state *cpustate)
791
if (OV == 0) SET_PC(M_RDOP_ARG(cpustate->PC));
794
CLR0(cpustate, OV_FLAG);
796
MODIFY_AR_ARP(cpustate);
798
static void bnz(tms32025_state *cpustate)
800
if (cpustate->ACC.d != 0) SET_PC(M_RDOP_ARG(cpustate->PC));
801
else cpustate->PC++ ;
802
MODIFY_AR_ARP(cpustate);
804
static void bv(tms32025_state *cpustate)
807
SET_PC(M_RDOP_ARG(cpustate->PC));
808
CLR0(cpustate, OV_FLAG);
810
else cpustate->PC++ ;
811
MODIFY_AR_ARP(cpustate);
813
static void bz(tms32025_state *cpustate)
815
if (cpustate->ACC.d == 0) SET_PC(M_RDOP_ARG(cpustate->PC));
816
else cpustate->PC++ ;
817
MODIFY_AR_ARP(cpustate);
819
static void cala(tms32025_state *cpustate)
821
PUSH_STACK(cpustate, cpustate->PC);
822
SET_PC(cpustate->ACC.w.l);
824
static void call(tms32025_state *cpustate)
827
PUSH_STACK(cpustate, cpustate->PC);
828
SET_PC(M_RDOP_ARG((cpustate->PC - 1)));
829
MODIFY_AR_ARP(cpustate);
831
static void cmpl(tms32025_state *cpustate)
833
cpustate->ACC.d = (~cpustate->ACC.d);
835
static void cmpr(tms32025_state *cpustate)
837
switch (cpustate->opcode.b.l & 3)
839
case 00: if ( (UINT16)(cpustate->AR[ARP]) == (UINT16)(cpustate->AR[0]) ) SET1(cpustate, TC_FLAG);
840
else CLR1(cpustate, TC_FLAG);
842
case 01: if ( (UINT16)(cpustate->AR[ARP]) < (UINT16)(cpustate->AR[0]) ) SET1(cpustate, TC_FLAG);
843
else CLR1(cpustate, TC_FLAG);
845
case 02: if ( (UINT16)(cpustate->AR[ARP]) > (UINT16)(cpustate->AR[0]) ) SET1(cpustate, TC_FLAG);
846
else CLR1(cpustate, TC_FLAG);
848
case 03: if ( (UINT16)(cpustate->AR[ARP]) != (UINT16)(cpustate->AR[0]) ) SET1(cpustate, TC_FLAG);
849
else CLR1(cpustate, TC_FLAG);
854
static void cnfd(tms32025_state *cpustate) /** next two fetches need to use previous CNF value ! **/
856
CLR1(cpustate, CNF0_REG);
857
cpustate->datamap[4] = &cpustate->intRAM[0x200]; /* B0 */
858
cpustate->datamap[5] = &cpustate->intRAM[0x280]; /* B0 */
859
cpustate->pgmmap[510] = NULL;
860
cpustate->pgmmap[511] = NULL;
862
static void cnfp(tms32025_state *cpustate) /** next two fetches need to use previous CNF value ! **/
864
SET1(cpustate, CNF0_REG);
865
cpustate->datamap[4] = NULL; /* B0 */
866
cpustate->datamap[5] = NULL; /* B0 */
867
cpustate->pgmmap[510] = &cpustate->intRAM[0x200];
868
cpustate->pgmmap[511] = &cpustate->intRAM[0x280];
870
static void conf(tms32025_state *cpustate) /** Need to reconfigure the memory blocks */
872
switch (cpustate->opcode.b.l & 3)
874
case 00: CLR1(cpustate, CNF1_REG); CLR1(cpustate, CNF0_REG);
875
cpustate->datamap[4] = &cpustate->intRAM[0x200]; /* B0 */
876
cpustate->datamap[5] = &cpustate->intRAM[0x280]; /* B0 */
877
cpustate->datamap[6] = &cpustate->intRAM[0x300]; /* B0 */
878
cpustate->datamap[7] = &cpustate->intRAM[0x380]; /* B0 */
879
cpustate->datamap[8] = &cpustate->intRAM[0x400]; /* B1 */
880
cpustate->datamap[9] = &cpustate->intRAM[0x480]; /* B1 */
881
cpustate->datamap[10] = &cpustate->intRAM[0x500]; /* B1 */
882
cpustate->datamap[11] = &cpustate->intRAM[0x580]; /* B1 */
883
cpustate->datamap[12] = &cpustate->intRAM[0x600]; /* B3 */
884
cpustate->datamap[13] = &cpustate->intRAM[0x680]; /* B3 */
885
cpustate->datamap[14] = &cpustate->intRAM[0x700]; /* B3 */
886
cpustate->datamap[15] = &cpustate->intRAM[0x780]; /* B3 */
887
cpustate->pgmmap[500] = NULL;
888
cpustate->pgmmap[501] = NULL;
889
cpustate->pgmmap[502] = NULL;
890
cpustate->pgmmap[503] = NULL;
891
cpustate->pgmmap[504] = NULL;
892
cpustate->pgmmap[505] = NULL;
893
cpustate->pgmmap[506] = NULL;
894
cpustate->pgmmap[507] = NULL;
895
cpustate->pgmmap[508] = NULL;
896
cpustate->pgmmap[509] = NULL;
897
cpustate->pgmmap[510] = NULL;
898
cpustate->pgmmap[511] = NULL;
901
case 01: CLR1(cpustate, CNF1_REG); SET1(cpustate, CNF0_REG);
902
cpustate->datamap[4] = NULL;
903
cpustate->datamap[5] = NULL;
904
cpustate->datamap[6] = NULL;
905
cpustate->datamap[7] = NULL;
906
cpustate->datamap[8] = &cpustate->intRAM[0x400]; /* B1 */
907
cpustate->datamap[9] = &cpustate->intRAM[0x480]; /* B1 */
908
cpustate->datamap[10] = &cpustate->intRAM[0x500]; /* B1 */
909
cpustate->datamap[11] = &cpustate->intRAM[0x580]; /* B1 */
910
cpustate->datamap[12] = &cpustate->intRAM[0x600]; /* B3 */
911
cpustate->datamap[13] = &cpustate->intRAM[0x680]; /* B3 */
912
cpustate->datamap[14] = &cpustate->intRAM[0x700]; /* B3 */
913
cpustate->datamap[15] = &cpustate->intRAM[0x780]; /* B3 */
914
cpustate->pgmmap[500] = &cpustate->intRAM[0x200]; /* B0 */
915
cpustate->pgmmap[501] = &cpustate->intRAM[0x280]; /* B0 */
916
cpustate->pgmmap[502] = &cpustate->intRAM[0x300]; /* B0 */
917
cpustate->pgmmap[503] = &cpustate->intRAM[0x380]; /* B0 */
918
cpustate->pgmmap[504] = NULL;
919
cpustate->pgmmap[505] = NULL;
920
cpustate->pgmmap[506] = NULL;
921
cpustate->pgmmap[507] = NULL;
922
cpustate->pgmmap[508] = NULL;
923
cpustate->pgmmap[509] = NULL;
924
cpustate->pgmmap[510] = NULL;
925
cpustate->pgmmap[511] = NULL;
928
case 02: SET1(cpustate, CNF1_REG); CLR1(cpustate, CNF0_REG);
929
cpustate->datamap[4] = NULL;
930
cpustate->datamap[5] = NULL;
931
cpustate->datamap[6] = NULL;
932
cpustate->datamap[7] = NULL;
933
cpustate->datamap[8] = NULL;
934
cpustate->datamap[9] = NULL;
935
cpustate->datamap[10] = NULL;
936
cpustate->datamap[11] = NULL;
937
cpustate->datamap[12] = &cpustate->intRAM[0x600]; /* B3 */
938
cpustate->datamap[13] = &cpustate->intRAM[0x680]; /* B3 */
939
cpustate->datamap[14] = &cpustate->intRAM[0x700]; /* B3 */
940
cpustate->datamap[15] = &cpustate->intRAM[0x780]; /* B3 */
941
cpustate->pgmmap[500] = &cpustate->intRAM[0x200]; /* B0 */
942
cpustate->pgmmap[501] = &cpustate->intRAM[0x280]; /* B0 */
943
cpustate->pgmmap[502] = &cpustate->intRAM[0x300]; /* B0 */
944
cpustate->pgmmap[503] = &cpustate->intRAM[0x380]; /* B0 */
945
cpustate->pgmmap[504] = &cpustate->intRAM[0x400]; /* B1 */
946
cpustate->pgmmap[505] = &cpustate->intRAM[0x480]; /* B1 */
947
cpustate->pgmmap[506] = &cpustate->intRAM[0x500]; /* B1 */
948
cpustate->pgmmap[507] = &cpustate->intRAM[0x580]; /* B1 */
949
cpustate->pgmmap[508] = NULL;
950
cpustate->pgmmap[509] = NULL;
951
cpustate->pgmmap[510] = NULL;
952
cpustate->pgmmap[511] = NULL;
955
case 03: SET1(cpustate, CNF1_REG); SET1(cpustate, CNF0_REG);
956
cpustate->datamap[4] = NULL;
957
cpustate->datamap[5] = NULL;
958
cpustate->datamap[6] = NULL;
959
cpustate->datamap[7] = NULL;
960
cpustate->datamap[8] = NULL;
961
cpustate->datamap[9] = NULL;
962
cpustate->datamap[10] = NULL;
963
cpustate->datamap[11] = NULL;
964
cpustate->datamap[12] = NULL;
965
cpustate->datamap[13] = NULL;
966
cpustate->datamap[14] = NULL;
967
cpustate->datamap[15] = NULL;
968
cpustate->pgmmap[500] = &cpustate->intRAM[0x200]; /* B0 */
969
cpustate->pgmmap[501] = &cpustate->intRAM[0x280]; /* B0 */
970
cpustate->pgmmap[502] = &cpustate->intRAM[0x300]; /* B0 */
971
cpustate->pgmmap[503] = &cpustate->intRAM[0x380]; /* B0 */
972
cpustate->pgmmap[504] = &cpustate->intRAM[0x400]; /* B1 */
973
cpustate->pgmmap[505] = &cpustate->intRAM[0x480]; /* B1 */
974
cpustate->pgmmap[506] = &cpustate->intRAM[0x500]; /* B1 */
975
cpustate->pgmmap[507] = &cpustate->intRAM[0x580]; /* B1 */
976
cpustate->pgmmap[508] = &cpustate->intRAM[0x600]; /* B3 */
977
cpustate->pgmmap[509] = &cpustate->intRAM[0x680]; /* B3 */
978
cpustate->pgmmap[510] = &cpustate->intRAM[0x700]; /* B3 */
979
cpustate->pgmmap[511] = &cpustate->intRAM[0x780]; /* B3 */
985
static void dint(tms32025_state *cpustate)
987
SET0(cpustate, INTM_FLAG);
989
static void dmov(tms32025_state *cpustate) /** Careful with how memory is configured !! */
991
GETDATA(cpustate, 0, 0);
992
M_WRTRAM(cpustate, (cpustate->memaccess + 1), cpustate->ALU.w.l);
994
static void eint(tms32025_state *cpustate)
996
CLR0(cpustate, INTM_FLAG);
998
static void fort(tms32025_state *cpustate)
1000
if (cpustate->opcode.b.l & 1) SET1(cpustate, FO_FLAG);
1001
else CLR1(cpustate, FO_FLAG);
1003
static void idle(tms32025_state *cpustate)
1005
CLR0(cpustate, INTM_FLAG);
1008
static void in(tms32025_state *cpustate)
1010
cpustate->ALU.w.l = P_IN( (cpustate->opcode.b.h & 0xf) );
1011
PUTDATA(cpustate, cpustate->ALU.w.l);
1013
static void lac(tms32025_state *cpustate)
1015
GETDATA(cpustate, (cpustate->opcode.b.h & 0xf), SXM);
1016
cpustate->ACC.d = cpustate->ALU.d;
1018
static void lack(tms32025_state *cpustate) /* ZAC is a subset of this instruction */
1020
cpustate->ACC.d = (UINT8)cpustate->opcode.b.l;
1022
static void lact(tms32025_state *cpustate)
1024
GETDATA(cpustate, (cpustate->Treg & 0xf), SXM);
1025
cpustate->ACC.d = cpustate->ALU.d;
1027
static void lalk(tms32025_state *cpustate)
1030
cpustate->ALU.d = (INT16)M_RDOP_ARG(cpustate->PC);
1031
cpustate->ACC.d = cpustate->ALU.d << (cpustate->opcode.b.h & 0xf);
1034
cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC);
1035
cpustate->ACC.d = cpustate->ALU.d << (cpustate->opcode.b.h & 0xf);
1036
cpustate->ACC.d &= 0x7fffffff;
1040
static void lar_ar0(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[0] = cpustate->ALU.w.l; }
1041
static void lar_ar1(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[1] = cpustate->ALU.w.l; }
1042
static void lar_ar2(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[2] = cpustate->ALU.w.l; }
1043
static void lar_ar3(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[3] = cpustate->ALU.w.l; }
1044
static void lar_ar4(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[4] = cpustate->ALU.w.l; }
1045
static void lar_ar5(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[5] = cpustate->ALU.w.l; }
1046
static void lar_ar6(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[6] = cpustate->ALU.w.l; }
1047
static void lar_ar7(tms32025_state *cpustate) { GETDATA(cpustate, 0, 0); cpustate->AR[7] = cpustate->ALU.w.l; }
1048
static void lark_ar0(tms32025_state *cpustate) { cpustate->AR[0] = cpustate->opcode.b.l; }
1049
static void lark_ar1(tms32025_state *cpustate) { cpustate->AR[1] = cpustate->opcode.b.l; }
1050
static void lark_ar2(tms32025_state *cpustate) { cpustate->AR[2] = cpustate->opcode.b.l; }
1051
static void lark_ar3(tms32025_state *cpustate) { cpustate->AR[3] = cpustate->opcode.b.l; }
1052
static void lark_ar4(tms32025_state *cpustate) { cpustate->AR[4] = cpustate->opcode.b.l; }
1053
static void lark_ar5(tms32025_state *cpustate) { cpustate->AR[5] = cpustate->opcode.b.l; }
1054
static void lark_ar6(tms32025_state *cpustate) { cpustate->AR[6] = cpustate->opcode.b.l; }
1055
static void lark_ar7(tms32025_state *cpustate) { cpustate->AR[7] = cpustate->opcode.b.l; }
1056
static void ldp(tms32025_state *cpustate)
1058
GETDATA(cpustate, 0, 0);
1059
MODIFY_DP(cpustate, cpustate->ALU.d & 0x1ff);
1061
static void ldpk(tms32025_state *cpustate)
1063
MODIFY_DP(cpustate, cpustate->opcode.w.l & 0x1ff);
1065
static void lph(tms32025_state *cpustate)
1067
GETDATA(cpustate, 0, 0);
1068
cpustate->Preg.w.h = cpustate->ALU.w.l;
1070
static void lrlk(tms32025_state *cpustate)
1072
cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC);
1074
cpustate->AR[cpustate->opcode.b.h & 7] = cpustate->ALU.w.l;
1076
static void lst(tms32025_state *cpustate)
1078
cpustate->mHackIgnoreARP = 1;
1079
GETDATA(cpustate, 0, 0);
1080
cpustate->mHackIgnoreARP = 0;
1082
cpustate->ALU.w.l &= (~INTM_FLAG);
1083
cpustate->STR0 &= INTM_FLAG;
1084
cpustate->STR0 |= cpustate->ALU.w.l; /* Must not affect INTM */
1085
cpustate->STR0 |= 0x0400;
1087
static void lst1(tms32025_state *cpustate)
1089
cpustate->mHackIgnoreARP = 1;
1090
GETDATA(cpustate, 0, 0);
1091
cpustate->mHackIgnoreARP = 0;
1093
cpustate->STR1 = cpustate->ALU.w.l;
1094
cpustate->STR1 |= 0x0180;
1095
cpustate->STR0 &= (~ARP_REG); /* ARB also gets copied to ARP */
1096
cpustate->STR0 |= (cpustate->STR1 & ARB_REG);
1098
static void lt(tms32025_state *cpustate)
1100
GETDATA(cpustate, 0, 0);
1101
cpustate->Treg = cpustate->ALU.w.l;
1103
static void lta(tms32025_state *cpustate)
1105
cpustate->oldacc.d = cpustate->ACC.d;
1106
GETDATA(cpustate, 0, 0);
1107
cpustate->Treg = cpustate->ALU.w.l;
1108
SHIFT_Preg_TO_ALU(cpustate);
1109
cpustate->ACC.d += cpustate->ALU.d;
1110
CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
1111
CALCULATE_ADD_CARRY(cpustate);
1113
static void ltd(tms32025_state *cpustate) /** Careful with how memory is configured !! */
1115
cpustate->oldacc.d = cpustate->ACC.d;
1116
GETDATA(cpustate, 0, 0);
1117
cpustate->Treg = cpustate->ALU.w.l;
1118
M_WRTRAM(cpustate, (cpustate->memaccess+1), cpustate->ALU.w.l);
1119
SHIFT_Preg_TO_ALU(cpustate);
1120
cpustate->ACC.d += cpustate->ALU.d;
1121
CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
1122
CALCULATE_ADD_CARRY(cpustate);
1124
static void ltp(tms32025_state *cpustate)
1126
cpustate->oldacc.d = cpustate->ACC.d;
1127
GETDATA(cpustate, 0, 0);
1128
cpustate->Treg = cpustate->ALU.w.l;
1129
SHIFT_Preg_TO_ALU(cpustate);
1130
cpustate->ACC.d = cpustate->ALU.d;
1132
static void lts(tms32025_state *cpustate)
1134
cpustate->oldacc.d = cpustate->ACC.d;
1135
GETDATA(cpustate, 0, 0);
1136
cpustate->Treg = cpustate->ALU.w.l;
1137
SHIFT_Preg_TO_ALU(cpustate);
1138
cpustate->ACC.d -= cpustate->ALU.d;
1139
CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1140
CALCULATE_SUB_CARRY(cpustate);
1142
static void mac(tms32025_state *cpustate) /** RAM blocks B0,B1,B2 may be important ! */
1143
{ /** Fix cycle timing **/
1144
cpustate->oldacc.d = cpustate->ACC.d;
1145
if (cpustate->init_load_addr) {
1146
cpustate->PFC = M_RDOP_ARG(cpustate->PC);
1149
SHIFT_Preg_TO_ALU(cpustate);
1150
cpustate->ACC.d += cpustate->ALU.d;
1151
CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
1152
CALCULATE_ADD_CARRY(cpustate);
1153
GETDATA(cpustate, 0, 0);
1154
cpustate->Treg = cpustate->ALU.w.l;
1155
cpustate->Preg.d = ( (INT16)cpustate->ALU.w.l * (INT16)M_RDROM(cpustate, cpustate->PFC) );
1157
cpustate->tms32025_dec_cycles += (2*CLK);
1159
static void macd(tms32025_state *cpustate) /** RAM blocks B0,B1,B2 may be important ! */
1160
{ /** Fix cycle timing **/
1161
cpustate->oldacc.d = cpustate->ACC.d;
1162
if (cpustate->init_load_addr) {
1163
cpustate->PFC = M_RDOP_ARG(cpustate->PC);
1166
SHIFT_Preg_TO_ALU(cpustate);
1167
cpustate->ACC.d += cpustate->ALU.d;
1168
CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
1169
CALCULATE_ADD_CARRY(cpustate);
1170
GETDATA(cpustate, 0, 0);
1171
if ( (cpustate->opcode.b.l & 0x80) || cpustate->init_load_addr ) { /* No writing during repitition, or DMA mode */
1172
M_WRTRAM(cpustate, (cpustate->memaccess+1), cpustate->ALU.w.l);
1174
cpustate->Treg = cpustate->ALU.w.l;
1175
cpustate->Preg.d = ( (INT16)cpustate->ALU.w.l * (INT16)M_RDROM(cpustate, cpustate->PFC) );
1177
cpustate->tms32025_dec_cycles += (2*CLK);
1179
static void mar(tms32025_state *cpustate) /* LARP and NOP are a subset of this instruction */
1181
if (cpustate->opcode.b.l & 0x80) MODIFY_AR_ARP(cpustate);
1183
static void mpy(tms32025_state *cpustate)
1185
GETDATA(cpustate, 0, 0);
1186
cpustate->Preg.d = (INT16)(cpustate->ALU.w.l) * (INT16)(cpustate->Treg);
1188
static void mpya(tms32025_state *cpustate)
1190
cpustate->oldacc.d = cpustate->ACC.d;
1191
SHIFT_Preg_TO_ALU(cpustate);
1192
cpustate->ACC.d += cpustate->ALU.d;
1193
CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
1194
CALCULATE_ADD_CARRY(cpustate);
1195
GETDATA(cpustate, 0, 0);
1196
cpustate->Preg.d = (INT16)(cpustate->ALU.w.l) * (INT16)(cpustate->Treg);
1198
static void mpyk(tms32025_state *cpustate)
1200
cpustate->Preg.d = (INT16)cpustate->Treg * ((INT16)(cpustate->opcode.w.l << 3) >> 3);
1203
static void mpys(tms32025_state *cpustate)
1205
cpustate->oldacc.d = cpustate->ACC.d;
1206
SHIFT_Preg_TO_ALU(cpustate);
1207
cpustate->ACC.d -= cpustate->ALU.d;
1208
CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1209
CALCULATE_SUB_CARRY(cpustate);
1210
GETDATA(cpustate, 0, 0);
1211
cpustate->Preg.d = (INT16)(cpustate->ALU.w.l) * (INT16)(cpustate->Treg);
1213
static void mpyu(tms32025_state *cpustate)
1215
GETDATA(cpustate, 0, 0);
1216
cpustate->Preg.d = (UINT16)(cpustate->ALU.w.l) * (UINT16)(cpustate->Treg);
1218
static void neg(tms32025_state *cpustate)
1220
if (cpustate->ACC.d == 0x80000000) {
1221
SET0(cpustate, OV_FLAG);
1222
if (OVM) cpustate->ACC.d = 0x7fffffff;
1224
else cpustate->ACC.d = -cpustate->ACC.d;
1225
if (cpustate->ACC.d) CLR0(cpustate, C_FLAG);
1226
else SET0(cpustate, C_FLAG);
1229
static void nop(tms32025_state *cpustate) { } // NOP is a subset of the MAR instruction
1231
static void norm(tms32025_state *cpustate)
1233
UINT32 acc = cpustate->ACC.d;
1235
if( acc == 0 || ((acc^(acc<<1))&(1<<31))!=0 ) {
1236
SET1(cpustate, TC_FLAG); /* 1 -> TC */
1239
CLR1(cpustate, TC_FLAG); /* 0 -> TC */
1240
cpustate->ACC.d <<= 1; /* (ACC)*2 -> ACC */
1241
MODIFY_AR_ARP(cpustate);
1244
static void or_(tms32025_state *cpustate)
1246
GETDATA(cpustate, 0, 0);
1247
cpustate->ACC.w.l |= cpustate->ALU.w.l;
1249
static void ork(tms32025_state *cpustate)
1251
cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC);
1253
cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf);
1254
cpustate->ACC.d |= (cpustate->ALU.d & 0x7fffffff);
1256
static void out(tms32025_state *cpustate)
1258
GETDATA(cpustate, 0, 0);
1259
P_OUT( (cpustate->opcode.b.h & 0xf), cpustate->ALU.w.l );
1261
static void pac(tms32025_state *cpustate)
1263
SHIFT_Preg_TO_ALU(cpustate);
1264
cpustate->ACC.d = cpustate->ALU.d;
1266
static void pop(tms32025_state *cpustate)
1268
cpustate->ACC.d = (UINT16)POP_STACK(cpustate);
1270
static void popd(tms32025_state *cpustate)
1272
cpustate->ALU.d = (UINT16)POP_STACK(cpustate);
1273
PUTDATA(cpustate, cpustate->ALU.w.l);
1275
static void pshd(tms32025_state *cpustate)
1277
GETDATA(cpustate, 0, 0);
1278
PUSH_STACK(cpustate, cpustate->ALU.w.l);
1280
static void push(tms32025_state *cpustate)
1282
PUSH_STACK(cpustate, cpustate->ACC.w.l);
1284
static void rc(tms32025_state *cpustate)
1286
CLR1(cpustate, C_FLAG);
1288
static void ret(tms32025_state *cpustate)
1290
SET_PC(POP_STACK(cpustate));
1292
static void rfsm(tms32025_state *cpustate) /** serial port mode */
1294
CLR1(cpustate, FSM_FLAG);
1296
static void rhm(tms32025_state *cpustate)
1298
CLR1(cpustate, HM_FLAG);
1300
static void rol(tms32025_state *cpustate)
1302
cpustate->ALU.d = cpustate->ACC.d;
1303
cpustate->ACC.d <<= 1;
1304
if (CARRY) cpustate->ACC.d |= 1;
1305
if (cpustate->ALU.d & 0x80000000) SET1(cpustate, C_FLAG);
1306
else CLR1(cpustate, C_FLAG);
1308
static void ror(tms32025_state *cpustate)
1310
cpustate->ALU.d = cpustate->ACC.d;
1311
cpustate->ACC.d >>= 1;
1312
if (CARRY) cpustate->ACC.d |= 0x80000000;
1313
if (cpustate->ALU.d & 1) SET1(cpustate, C_FLAG);
1314
else CLR1(cpustate, C_FLAG);
1316
static void rovm(tms32025_state *cpustate)
1318
CLR0(cpustate, OVM_FLAG);
1320
static void rpt(tms32025_state *cpustate)
1322
GETDATA(cpustate, 0, 0);
1323
cpustate->RPTC = cpustate->ALU.b.l;
1324
cpustate->init_load_addr = 2; /* Initiate repeat mode */
1326
static void rptk(tms32025_state *cpustate)
1328
cpustate->RPTC = cpustate->opcode.b.l;
1329
cpustate->init_load_addr = 2; /* Initiate repeat mode */
1331
static void rsxm(tms32025_state *cpustate)
1333
CLR1(cpustate, SXM_FLAG);
1335
static void rtc(tms32025_state *cpustate)
1337
CLR1(cpustate, TC_FLAG);
1339
static void rtxm(tms32025_state *cpustate) /** Serial port stuff */
1341
CLR1(cpustate, TXM_FLAG);
1343
static void rxf(tms32025_state *cpustate)
1345
CLR1(cpustate, XF_FLAG);
1346
S_OUT(TMS32025_XF,CLEAR_LINE);
1348
static void sach(tms32025_state *cpustate)
1350
cpustate->ALU.d = (cpustate->ACC.d << (cpustate->opcode.b.h & 7));
1351
PUTDATA(cpustate, cpustate->ALU.w.h);
1353
static void sacl(tms32025_state *cpustate)
1355
cpustate->ALU.d = (cpustate->ACC.d << (cpustate->opcode.b.h & 7));
1356
PUTDATA(cpustate, cpustate->ALU.w.l);
1358
static void sar_ar0(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[0]); }
1359
static void sar_ar1(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[1]); }
1360
static void sar_ar2(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[2]); }
1361
static void sar_ar3(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[3]); }
1362
static void sar_ar4(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[4]); }
1363
static void sar_ar5(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[5]); }
1364
static void sar_ar6(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[6]); }
1365
static void sar_ar7(tms32025_state *cpustate) { PUTDATA(cpustate, cpustate->AR[7]); }
1367
static void sblk(tms32025_state *cpustate)
1369
cpustate->oldacc.d = cpustate->ACC.d;
1370
if (SXM) cpustate->ALU.d = (INT16)M_RDOP_ARG(cpustate->PC);
1371
else cpustate->ALU.d = (UINT16)M_RDOP_ARG(cpustate->PC);
1373
cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf);
1374
cpustate->ACC.d -= cpustate->ALU.d;
1375
CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1376
CALCULATE_SUB_CARRY(cpustate);
1378
static void sbrk_tms(tms32025_state *cpustate)
1380
cpustate->AR[ARP] -= cpustate->opcode.b.l;
1382
static void sc(tms32025_state *cpustate)
1384
SET1(cpustate, C_FLAG);
1386
static void sfl(tms32025_state *cpustate)
1388
cpustate->ALU.d = cpustate->ACC.d;
1389
cpustate->ACC.d <<= 1;
1390
if (cpustate->ALU.d & 0x80000000) SET1(cpustate, C_FLAG);
1391
else CLR1(cpustate, C_FLAG);
1393
static void sfr(tms32025_state *cpustate)
1395
cpustate->ALU.d = cpustate->ACC.d;
1396
cpustate->ACC.d >>= 1;
1398
if (cpustate->ALU.d & 0x80000000) cpustate->ACC.d |= 0x80000000;
1400
if (cpustate->ALU.d & 1) SET1(cpustate, C_FLAG);
1401
else CLR1(cpustate, C_FLAG);
1403
static void sfsm(tms32025_state *cpustate) /** Serial port mode */
1405
SET1(cpustate, FSM_FLAG);
1407
static void shm(tms32025_state *cpustate)
1409
SET1(cpustate, HM_FLAG);
1411
static void sovm(tms32025_state *cpustate)
1413
SET0(cpustate, OVM_FLAG);
1415
static void spac(tms32025_state *cpustate)
1417
cpustate->oldacc.d = cpustate->ACC.d;
1418
SHIFT_Preg_TO_ALU(cpustate);
1419
cpustate->ACC.d -= cpustate->ALU.d;
1420
CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1421
CALCULATE_SUB_CARRY(cpustate);
1423
static void sph(tms32025_state *cpustate)
1425
SHIFT_Preg_TO_ALU(cpustate);
1426
PUTDATA(cpustate, cpustate->ALU.w.h);
1428
static void spl(tms32025_state *cpustate)
1430
SHIFT_Preg_TO_ALU(cpustate);
1431
PUTDATA(cpustate, cpustate->ALU.w.l);
1433
static void spm(tms32025_state *cpustate)
1435
MODIFY_PM(cpustate, (cpustate->opcode.b.l & 3) );
1437
static void sqra(tms32025_state *cpustate)
1439
cpustate->oldacc.d = cpustate->ACC.d;
1440
SHIFT_Preg_TO_ALU(cpustate);
1441
cpustate->ACC.d += cpustate->ALU.d;
1442
CALCULATE_ADD_OVERFLOW(cpustate, cpustate->ALU.d);
1443
CALCULATE_ADD_CARRY(cpustate);
1444
GETDATA(cpustate, 0, 0);
1445
cpustate->Treg = cpustate->ALU.w.l;
1446
cpustate->Preg.d = ((INT16)cpustate->ALU.w.l * (INT16)cpustate->ALU.w.l);
1448
static void sqrs(tms32025_state *cpustate)
1450
cpustate->oldacc.d = cpustate->ACC.d;
1451
SHIFT_Preg_TO_ALU(cpustate);
1452
cpustate->ACC.d -= cpustate->ALU.d;
1453
CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1454
CALCULATE_SUB_CARRY(cpustate);
1455
GETDATA(cpustate, 0, 0);
1456
cpustate->Treg = cpustate->ALU.w.l;
1457
cpustate->Preg.d = ((INT16)cpustate->ALU.w.l * (INT16)cpustate->ALU.w.l);
1459
static void sst(tms32025_state *cpustate)
1461
PUTDATA_SST(cpustate, cpustate->STR0);
1463
static void sst1(tms32025_state *cpustate)
1465
PUTDATA_SST(cpustate, cpustate->STR1);
1467
static void ssxm(tms32025_state *cpustate)
1468
{ /** Check instruction description, and make sure right instructions use SXM */
1469
SET1(cpustate, SXM_FLAG);
1471
static void stc(tms32025_state *cpustate)
1473
SET1(cpustate, TC_FLAG);
1475
static void stxm(tms32025_state *cpustate) /** Serial port stuff */
1477
SET1(cpustate, TXM_FLAG);
1479
static void sub(tms32025_state *cpustate)
1481
cpustate->oldacc.d = cpustate->ACC.d;
1482
GETDATA(cpustate, (cpustate->opcode.b.h & 0xf), SXM);
1483
cpustate->ACC.d -= cpustate->ALU.d;
1484
CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1485
CALCULATE_SUB_CARRY(cpustate);
1487
static void subb(tms32025_state *cpustate)
1489
cpustate->oldacc.d = cpustate->ACC.d;
1490
GETDATA(cpustate, 0, 0);
1491
if (CARRY == 0) cpustate->ALU.d--;
1492
cpustate->ACC.d -= cpustate->ALU.d;
1493
CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1494
CALCULATE_SUB_CARRY(cpustate);
1498
static void subc(tms32025_state *cpustate)
1501
* conditional subtraction, which may be used for division
1502
* execute 16 times for 16-bit division
1504
* input: 32 bit numerator in accumulator
1505
* 16 bit denominator in data memory
1507
* output: remainder in upper 16 bits
1508
* quotient in lower 16 bits
1510
GETDATA(cpustate, 15, SXM);
1511
if( cpustate->ACC.d >= cpustate->ALU.d ) {
1512
cpustate->ACC.d = (cpustate->ACC.d - cpustate->ALU.d)*2+1;
1515
cpustate->ACC.d = cpustate->ACC.d*2;
1517
// Stroff: HACK! support for overflow capping as implemented results in bad DSP floating point math in many
1518
// System22 games - for example, the score display in Prop Cycle.
1519
// cpustate->ACC.d = ((INT32)cpustate->oldacc.d < 0) ? 0x80000000 : 0x7fffffff;
1521
// if ((INT32)((cpustate->oldacc.d ^ subval ) & (cpustate->oldacc.d ^ cpustate->ALU.d)) < 0) {
1522
// SET0(cpustate, OV_FLAG);
1524
// CALCULATE_SUB_CARRY(cpustate);
1527
static void subh(tms32025_state *cpustate)
1529
cpustate->oldacc.d = cpustate->ACC.d;
1530
GETDATA(cpustate, 0, 0);
1531
cpustate->ACC.w.h -= cpustate->ALU.w.l;
1532
if ((INT16)((cpustate->oldacc.w.h ^ cpustate->ALU.w.l) & (cpustate->oldacc.w.h ^ cpustate->ACC.w.h)) < 0) {
1533
SET0(cpustate, OV_FLAG);
1535
cpustate->ACC.w.h = ((INT16)cpustate->oldacc.w.h < 0) ? 0x8000 : 0x7fff;
1537
if ( ((INT16)(cpustate->oldacc.w.h) >= 0) && ((INT16)(cpustate->ACC.w.h) < 0) ) {
1538
CLR1(cpustate, C_FLAG);
1540
/* Carry flag is not affected, if no borrow occured */
1542
static void subk(tms32025_state *cpustate)
1544
cpustate->oldacc.d = cpustate->ACC.d;
1545
cpustate->ALU.d = (UINT8)cpustate->opcode.b.l;
1546
cpustate->ACC.d -= cpustate->ALU.b.l;
1547
CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1548
CALCULATE_SUB_CARRY(cpustate);
1550
static void subs(tms32025_state *cpustate)
1552
cpustate->oldacc.d = cpustate->ACC.d;
1553
GETDATA(cpustate, 0, 0);
1554
cpustate->ACC.d -= cpustate->ALU.w.l;
1555
CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1556
CALCULATE_SUB_CARRY(cpustate);
1558
static void subt(tms32025_state *cpustate)
1560
cpustate->oldacc.d = cpustate->ACC.d;
1561
GETDATA(cpustate, (cpustate->Treg & 0xf), SXM);
1562
cpustate->ACC.d -= cpustate->ALU.d;
1563
CALCULATE_SUB_OVERFLOW(cpustate, cpustate->ALU.d);
1564
CALCULATE_SUB_CARRY(cpustate);
1566
static void sxf(tms32025_state *cpustate)
1568
SET1(cpustate, XF_FLAG);
1569
S_OUT(TMS32025_XF,ASSERT_LINE);
1571
static void tblr(tms32025_state *cpustate)
1573
if (cpustate->init_load_addr) {
1574
cpustate->PFC = cpustate->ACC.w.l;
1576
cpustate->ALU.w.l = M_RDROM(cpustate, cpustate->PFC);
1577
if ( (CNF0) && ( (UINT16)(cpustate->PFC) >= 0xff00 ) ) {} /** TMS32025 only */
1578
else cpustate->tms32025_dec_cycles += (1*CLK);
1579
PUTDATA(cpustate, cpustate->ALU.w.l);
1582
static void tblw(tms32025_state *cpustate)
1584
if (cpustate->init_load_addr) {
1585
cpustate->PFC = cpustate->ACC.w.l;
1587
cpustate->tms32025_dec_cycles += (1*CLK);
1588
GETDATA(cpustate, 0, 0);
1589
if (cpustate->external_mem_access) cpustate->tms32025_dec_cycles += (1*CLK);
1590
M_WRTROM(cpustate, cpustate->PFC, cpustate->ALU.w.l);
1593
static void trap(tms32025_state *cpustate)
1595
PUSH_STACK(cpustate, cpustate->PC);
1596
SET_PC(0x001E); /* Trap vector */
1598
static void xor_(tms32025_state *cpustate)
1600
GETDATA(cpustate, 0, 0);
1601
cpustate->ACC.w.l ^= cpustate->ALU.w.l;
1603
static void xork(tms32025_state *cpustate)
1605
cpustate->oldacc.d = cpustate->ACC.d;
1606
cpustate->ALU.d = M_RDOP_ARG(cpustate->PC);
1608
cpustate->ALU.d <<= (cpustate->opcode.b.h & 0xf);
1609
cpustate->ACC.d ^= cpustate->ALU.d;
1610
cpustate->ACC.d |= (cpustate->oldacc.d & 0x80000000);
1612
static void zalh(tms32025_state *cpustate)
1614
GETDATA(cpustate, 0, 0);
1615
cpustate->ACC.w.h = cpustate->ALU.w.l;
1616
cpustate->ACC.w.l = 0x0000;
1618
static void zalr(tms32025_state *cpustate)
1620
GETDATA(cpustate, 0, 0);
1621
cpustate->ACC.w.h = cpustate->ALU.w.l;
1622
cpustate->ACC.w.l = 0x8000;
1624
static void zals(tms32025_state *cpustate)
1626
GETDATA(cpustate, 0, 0);
1627
cpustate->ACC.w.l = cpustate->ALU.w.l;
1628
cpustate->ACC.w.h = 0x0000;
1632
/***********************************************************************
1633
* Opcode Table (Cycles, Instruction)
1634
***********************************************************************/
1636
static const tms32025_opcode opcode_main[256]=
1638
/*00*/ {1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },
1639
/*08*/ {1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },{1*CLK, add },
1640
/*10*/ {1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },
1641
/*18*/ {1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },{1*CLK, sub },
1642
/*20*/ {1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },
1643
/*28*/ {1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },{1*CLK, lac },
1644
/*30*/ {1*CLK, lar_ar0 },{1*CLK, lar_ar1 },{1*CLK, lar_ar2 },{1*CLK, lar_ar3 },{1*CLK, lar_ar4 },{1*CLK, lar_ar5 },{1*CLK, lar_ar6 },{1*CLK, lar_ar7 },
1645
/*38*/ {1*CLK, mpy },{1*CLK, sqra },{1*CLK, mpya },{1*CLK, mpys },{1*CLK, lt },{1*CLK, lta },{1*CLK, ltp },{1*CLK, ltd },
1646
/*40*/ {1*CLK, zalh },{1*CLK, zals },{1*CLK, lact },{1*CLK, addc },{1*CLK, subh },{1*CLK, subs },{1*CLK, subt },{1*CLK, subc },
1647
/*48*/ {1*CLK, addh },{1*CLK, adds },{1*CLK, addt },{1*CLK, rpt },{1*CLK, xor_ },{1*CLK, or_ },{1*CLK, and_ },{1*CLK, subb },
1648
/*50*/ {1*CLK, lst },{1*CLK, lst1 },{1*CLK, ldp },{1*CLK, lph },{1*CLK, pshd },{1*CLK, mar },{1*CLK, dmov },{1*CLK, bitt },
1649
/*58*/ {3*CLK, tblr },{2*CLK, tblw },{1*CLK, sqrs },{1*CLK, lts },{2*CLK, macd },{2*CLK, mac },{2*CLK, bc },{2*CLK, bnc },
1650
/*60*/ {1*CLK, sacl },{1*CLK, sacl },{1*CLK, sacl },{1*CLK, sacl },{1*CLK, sacl },{1*CLK, sacl },{1*CLK, sacl },{1*CLK, sacl },
1651
/*68*/ {1*CLK, sach },{1*CLK, sach },{1*CLK, sach },{1*CLK, sach },{1*CLK, sach },{1*CLK, sach },{1*CLK, sach },{1*CLK, sach },
1652
/*70*/ {1*CLK, sar_ar0 },{1*CLK, sar_ar1 },{1*CLK, sar_ar2 },{1*CLK, sar_ar3 },{1*CLK, sar_ar4 },{1*CLK, sar_ar5 },{1*CLK, sar_ar6 },{1*CLK, sar_ar7 },
1653
/*78*/ {1*CLK, sst },{1*CLK, sst1 },{1*CLK, popd },{1*CLK, zalr },{1*CLK, spl },{1*CLK, sph },{1*CLK, adrk },{1*CLK, sbrk_tms },
1654
/*80*/ {2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },
1655
/*88*/ {2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },{2*CLK, in },
1656
/*90*/ {1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },
1657
/*98*/ {1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },{1*CLK, bit },
1658
/*A0*/ {1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },
1659
/*A8*/ {1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },
1660
/*B0*/ {1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },
1661
/*B8*/ {1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },{1*CLK, mpyk },
1662
/*C0*/ {1*CLK, lark_ar0 },{1*CLK, lark_ar1 },{1*CLK, lark_ar2 },{1*CLK, lark_ar3 },{1*CLK, lark_ar4 },{1*CLK, lark_ar5 },{1*CLK, lark_ar6 },{1*CLK, lark_ar7 },
1663
/*C8*/ {1*CLK, ldpk },{1*CLK, ldpk },{1*CLK, lack },{1*CLK, rptk },{1*CLK, addk },{1*CLK, subk },{1*CLK, opcodes_CE},{1*CLK, mpyu },
1664
/*D0*/ {1*CLK,opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{0*CLK, opcodes_Dx},
1665
/*D8*/ {1*CLK,opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},{1*CLK, opcodes_Dx},
1666
/*E0*/ {2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },
1667
/*E8*/ {2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },{2*CLK, out },
1668
/*F0*/ {2*CLK, bv },{2*CLK, bgz },{2*CLK, blez },{2*CLK, blz },{2*CLK, bgez },{2*CLK, bnz },{2*CLK, bz },{2*CLK, bnv },
1669
/*F8*/ {2*CLK, bbz },{2*CLK, bbnz },{2*CLK, bioz },{2*CLK, banz },{2*CLK, blkp },{2*CLK, blkd },{2*CLK, call },{2*CLK, br }
1672
static const tms32025_opcode_CE opcode_CE_subset[256]= /* Instructions living under the CExx opcode */
1674
/*00*/ {1*CLK, eint },{1*CLK, dint },{1*CLK, rovm },{1*CLK, sovm },{1*CLK, cnfd },{1*CLK, cnfp },{1*CLK, rsxm },{1*CLK, ssxm },
1675
/*08*/ {1*CLK, spm },{1*CLK, spm },{1*CLK, spm },{1*CLK, spm },{1*CLK, rxf },{1*CLK, sxf },{1*CLK, fort },{1*CLK, fort },
1676
/*10*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{1*CLK, pac },{1*CLK, apac },{1*CLK, spac },{0*CLK, illegal },
1677
/*18*/ {1*CLK, sfl },{1*CLK, sfr },{0*CLK, illegal },{1*CLK, abst },{1*CLK, push },{1*CLK, pop },{2*CLK, trap },{3*CLK, idle },
1678
/*20*/ {1*CLK, rtxm },{1*CLK, stxm },{0*CLK, illegal },{1*CLK, neg },{2*CLK, cala },{2*CLK, bacc },{2*CLK, ret },{1*CLK, cmpl },
1679
/*28*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1680
/*30*/ {1*CLK, rc },{1*CLK, sc },{1*CLK, rtc },{1*CLK, stc },{1*CLK, rol },{1*CLK, ror },{1*CLK, rfsm },{1*CLK, sfsm },
1681
/*38*/ {1*CLK, rhm },{1*CLK, shm },{0*CLK, illegal },{0*CLK, illegal },{1*CLK, conf },{1*CLK, conf },{1*CLK, conf },{1*CLK, conf },
1682
/*40*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1683
/*48*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1684
/*50*/ {1*CLK, cmpr },{1*CLK, cmpr },{1*CLK, cmpr },{1*CLK, cmpr },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1685
/*58*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1686
/*60*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1687
/*68*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1688
/*70*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1689
/*78*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1690
/*80*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1691
/*88*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1692
/*90*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1693
/*98*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1694
/*A0*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1695
/*A8*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1696
/*B0*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1697
/*B8*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1698
/*C0*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1699
/*C8*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1700
/*D0*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1701
/*D8*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1702
/*E0*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1703
/*E8*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1704
/*F0*/ {0*CLK, illegal },{0*CLK, illegal },{1*CLK, norm },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },
1705
/*F8*/ {0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal },{0*CLK, illegal }
1708
static const tms32025_opcode_Dx opcode_Dx_subset[8]= /* Instructions living under the Dxxx opcode */
1710
/*00*/ {2*CLK, lrlk },{2*CLK, lalk },{2*CLK, adlk },{2*CLK, sblk },{2*CLK, andk },{2*CLK, ork },{2*CLK, xork },{0*CLK, illegal }
1715
/****************************************************************************
1716
* Inits CPU emulation
1717
****************************************************************************/
1718
static CPU_INIT( tms32025 )
1720
tms32025_state *cpustate = get_safe_token(device);
1722
cpustate->intRAM = auto_alloc_array(device->machine(), UINT16, 0x800);
1723
cpustate->irq_callback = irqcallback;
1724
cpustate->device = device;
1725
cpustate->program = device->space(AS_PROGRAM);
1726
cpustate->direct = &cpustate->program->direct();
1727
cpustate->data = device->space(AS_DATA);
1728
cpustate->io = device->space(AS_IO);
1730
device->save_item(NAME(cpustate->PC));
1731
device->save_item(NAME(cpustate->STR0));
1732
device->save_item(NAME(cpustate->STR1));
1733
device->save_item(NAME(cpustate->PFC));
1734
device->save_item(NAME(cpustate->IFR));
1735
device->save_item(NAME(cpustate->RPTC));
1736
device->save_item(NAME(cpustate->ACC.d));
1737
device->save_item(NAME(cpustate->ALU.d));
1738
device->save_item(NAME(cpustate->Preg.d));
1739
device->save_item(NAME(cpustate->Treg));
1740
device->save_item(NAME(cpustate->AR[0]));
1741
device->save_item(NAME(cpustate->AR[1]));
1742
device->save_item(NAME(cpustate->AR[2]));
1743
device->save_item(NAME(cpustate->AR[3]));
1744
device->save_item(NAME(cpustate->AR[4]));
1745
device->save_item(NAME(cpustate->AR[5]));
1746
device->save_item(NAME(cpustate->AR[6]));
1747
device->save_item(NAME(cpustate->AR[7]));
1748
device->save_item(NAME(cpustate->STACK[0]));
1749
device->save_item(NAME(cpustate->STACK[1]));
1750
device->save_item(NAME(cpustate->STACK[2]));
1751
device->save_item(NAME(cpustate->STACK[3]));
1752
device->save_item(NAME(cpustate->STACK[4]));
1753
device->save_item(NAME(cpustate->STACK[5]));
1754
device->save_item(NAME(cpustate->STACK[6]));
1755
device->save_item(NAME(cpustate->STACK[7]));
1757
device->save_item(NAME(cpustate->oldacc));
1758
device->save_item(NAME(cpustate->memaccess));
1759
device->save_item(NAME(cpustate->icount));
1760
device->save_item(NAME(cpustate->mHackIgnoreARP));
1762
device->save_item(NAME(cpustate->idle));
1763
device->save_item(NAME(cpustate->hold));
1764
device->save_item(NAME(cpustate->external_mem_access));
1765
device->save_item(NAME(cpustate->init_load_addr));
1766
device->save_item(NAME(cpustate->PREVPC));
1768
// device->save_pointer(NAME(cpustate->intRAM), 0x800*2);
1771
/****************************************************************************
1772
* Reset registers to their initial values
1773
****************************************************************************/
1774
static CPU_RESET( tms32025 )
1776
tms32025_state *cpustate = get_safe_token(device);
1778
SET_PC(0); /* Starting address on a reset */
1779
cpustate->STR0 |= 0x0600; /* INTM and unused bit set to 1 */
1780
cpustate->STR0 &= 0xefff; /* OV cleared to 0. Remaining bits undefined */
1781
cpustate->STR1 |= 0x07f0; /* SXM, C, HM, FSM, XF and unused bits set to 1 */
1782
cpustate->STR1 &= 0xeff0; /* CNF, FO, TXM, PM bits cleared to 0. Remaining bits undefined */
1783
cpustate->RPTC = 0; /* Reset repeat counter to 0 */
1784
cpustate->IFR = 0; /* IRQ pending flags */
1786
S_OUT(TMS32025_XF,ASSERT_LINE); /* XF flag is high. Must set the pin */
1788
/* Set the internal memory mapped registers */
1796
cpustate->init_load_addr = 1;
1798
/* Reset the Data/Program address banks */
1799
memset(cpustate->pgmmap, 0, sizeof(cpustate->pgmmap));
1800
memset(cpustate->datamap, 0, sizeof(cpustate->datamap));
1802
cpustate->datamap[0] = &cpustate->intRAM[0x000]; /* B2 */
1803
cpustate->datamap[4] = &cpustate->intRAM[0x200]; /* B0 */
1804
cpustate->datamap[5] = &cpustate->intRAM[0x280]; /* B0 */
1805
cpustate->datamap[6] = &cpustate->intRAM[0x300]; /* B1 */
1806
cpustate->datamap[7] = &cpustate->intRAM[0x380]; /* B1 */
1809
static CPU_RESET( tms32026 )
1811
tms32025_state *cpustate = get_safe_token(device);
1813
CPU_RESET_CALL(tms32025);
1815
/* Reset the Data/Program address banks */
1816
memset(cpustate->pgmmap, 0, sizeof(cpustate->pgmmap));
1817
memset(cpustate->datamap, 0, sizeof(cpustate->datamap));
1819
cpustate->datamap[0] = &cpustate->intRAM[0x000]; /* B2 */
1820
cpustate->datamap[4] = &cpustate->intRAM[0x200]; /* B0 */
1821
cpustate->datamap[5] = &cpustate->intRAM[0x280]; /* B0 */
1822
cpustate->datamap[6] = &cpustate->intRAM[0x300]; /* B0 */
1823
cpustate->datamap[7] = &cpustate->intRAM[0x380]; /* B0 */
1824
cpustate->datamap[8] = &cpustate->intRAM[0x400]; /* B1 */
1825
cpustate->datamap[9] = &cpustate->intRAM[0x480]; /* B1 */
1826
cpustate->datamap[10] = &cpustate->intRAM[0x500]; /* B1 */
1827
cpustate->datamap[11] = &cpustate->intRAM[0x580]; /* B1 */
1828
cpustate->datamap[12] = &cpustate->intRAM[0x600]; /* B3 */
1829
cpustate->datamap[13] = &cpustate->intRAM[0x680]; /* B3 */
1830
cpustate->datamap[14] = &cpustate->intRAM[0x700]; /* B3 */
1831
cpustate->datamap[15] = &cpustate->intRAM[0x780]; /* B3 */
1835
/****************************************************************************
1836
* Shut down CPU emulation
1837
****************************************************************************/
1838
static CPU_EXIT( tms32025 )
1843
/****************************************************************************
1844
* Issue an interrupt if necessary
1845
****************************************************************************/
1846
static int process_IRQs(tms32025_state *cpustate)
1848
/********** Interrupt Flag Register (IFR) **********
1849
| 5 | 4 | 3 | 2 | 1 | 0 |
1850
| XINT| RINT| TINT| INT2| INT1| INT0|
1853
cpustate->tms32025_irq_cycles = 0;
1855
/* Dont service Interrupts if masked, or prev instruction was EINT ! */
1857
if ( (INTM == 0) && (cpustate->opcode.w.l != 0xce00) && (cpustate->IFR & IMR) )
1859
cpustate->tms32025_irq_cycles = (3*CLK); /* 3 clock cycles used due to PUSH and DINT operation ? */
1860
PUSH_STACK(cpustate, cpustate->PC);
1862
if ((cpustate->IFR & 0x01) && (IMR & 0x01)) { /* IRQ line 0 */
1863
//logerror("TMS32025: Active INT0\n");
1865
(*cpustate->irq_callback)(cpustate->device, 0);
1867
cpustate->IFR &= (~0x01);
1868
SET0(cpustate, INTM_FLAG);
1869
return cpustate->tms32025_irq_cycles;
1871
if ((cpustate->IFR & 0x02) && (IMR & 0x02)) { /* IRQ line 1 */
1872
//logerror("TMS32025: Active INT1\n");
1874
(*cpustate->irq_callback)(cpustate->device, 1);
1876
cpustate->IFR &= (~0x02);
1877
SET0(cpustate, INTM_FLAG);
1878
return cpustate->tms32025_irq_cycles;
1880
if ((cpustate->IFR & 0x04) && (IMR & 0x04)) { /* IRQ line 2 */
1881
//logerror("TMS32025: Active INT2\n");
1883
(*cpustate->irq_callback)(cpustate->device, 2);
1885
cpustate->IFR &= (~0x04);
1886
SET0(cpustate, INTM_FLAG);
1887
return cpustate->tms32025_irq_cycles;
1889
if ((cpustate->IFR & 0x08) && (IMR & 0x08)) { /* Timer IRQ (internal) */
1890
// logerror("TMS32025: Active TINT (Timer)\n");
1893
cpustate->IFR &= (~0x08);
1894
SET0(cpustate, INTM_FLAG);
1895
return cpustate->tms32025_irq_cycles;
1897
if ((cpustate->IFR & 0x10) && (IMR & 0x10)) { /* Serial port receive IRQ (internal) */
1898
// logerror("TMS32025: Active RINT (Serial receive)\n");
1899
DRR = S_IN(TMS32025_DR);
1902
cpustate->IFR &= (~0x10);
1903
SET0(cpustate, INTM_FLAG);
1904
return cpustate->tms32025_irq_cycles;
1906
if ((cpustate->IFR & 0x20) && (IMR & 0x20)) { /* Serial port transmit IRQ (internal) */
1907
// logerror("TMS32025: Active XINT (Serial transmit)\n");
1908
S_OUT(TMS32025_DX,DXR);
1911
cpustate->IFR &= (~0x20);
1912
SET0(cpustate, INTM_FLAG);
1913
return cpustate->tms32025_irq_cycles;
1916
return cpustate->tms32025_irq_cycles;
1919
static void set_fsx_line(tms32025_state *cpustate, int state)
1921
if (state != CLEAR_LINE && cpustate->waiting_for_serial_frame)
1923
cpustate->waiting_for_serial_frame = 0;
1924
cpustate->IFR = 0x20;
1928
INLINE void process_timer(tms32025_state *cpustate, int clocks)
1930
int preclocks, ticks;
1932
/* easy case: no actual ticks */
1934
preclocks = CLK - cpustate->timerover;
1935
if (clocks < preclocks)
1937
cpustate->timerover += clocks;
1938
cpustate->icount -= clocks;
1942
/* if we're not going to overflow the timer, just count the clocks */
1943
ticks = 1 + (clocks - preclocks) / CLK;
1946
cpustate->icount -= clocks;
1947
cpustate->timerover = clocks - (ticks - 1) * CLK - preclocks;
1951
/* otherwise, overflow the timer and signal an interrupt */
1954
cpustate->icount -= preclocks + CLK * TIM;
1955
cpustate->timerover = 0;
1958
cpustate->IFR |= 0x08;
1959
clocks = process_IRQs(cpustate); /* Handle Timer IRQ */
1965
/****************************************************************************
1966
* Execute ICount cycles. Exit when 0 or less
1967
****************************************************************************/
1968
static CPU_EXECUTE( tms32025 )
1970
tms32025_state *cpustate = get_safe_token(device);
1973
/**** Respond to external hold signal */
1974
if (S_IN(TMS32025_HOLD) == ASSERT_LINE) {
1975
if (cpustate->hold == 0) {
1976
S_OUT(TMS32025_HOLDA,ASSERT_LINE); /* Hold-Ack (active low) */
1980
cpustate->icount = 0; /* Exit */
1983
if (cpustate->external_mem_access) {
1984
cpustate->icount = 0; /* Exit */
1989
if (cpustate->hold == 1) {
1990
S_OUT(TMS32025_HOLDA,CLEAR_LINE); /* Hold-Ack (active low) */
1991
process_timer(cpustate, 3);
1996
/**** If idling, update timer and/or exit execution, but test for irqs first */
1997
if (cpustate->idle && cpustate->IFR && cpustate->icount > 0)
1998
cpustate->icount -= process_IRQs(cpustate);
2000
while (cpustate->idle && cpustate->icount > 0)
2001
process_timer(cpustate, cpustate->icount);
2003
if (cpustate->icount <= 0) debugger_instruction_hook(device, cpustate->PC);
2006
while (cpustate->icount > 0)
2008
cpustate->tms32025_dec_cycles = 0;
2010
if (cpustate->IFR) { /* Check IRQ Flag Register for pending IRQs */
2011
cpustate->tms32025_dec_cycles += process_IRQs(cpustate);
2014
cpustate->PREVPC = cpustate->PC;
2016
debugger_instruction_hook(device, cpustate->PC);
2018
cpustate->opcode.d = M_RDOP(cpustate->PC);
2021
if (cpustate->opcode.b.h == 0xCE) /* Opcode 0xCExx has many sub-opcodes in its minor byte */
2023
cpustate->tms32025_dec_cycles += opcode_CE_subset[cpustate->opcode.b.l].cycles;
2024
(*opcode_CE_subset[cpustate->opcode.b.l].function)(cpustate);
2026
else if ((cpustate->opcode.w.l & 0xf0f8) == 0xd000) /* Opcode 0xDxxx has many sub-opcodes in its minor byte */
2028
cpustate->tms32025_dec_cycles += opcode_Dx_subset[cpustate->opcode.b.l].cycles;
2029
(*opcode_Dx_subset[cpustate->opcode.b.l].function)(cpustate);
2031
else /* Do all opcodes except the CExx and Dxxx ones */
2033
cpustate->tms32025_dec_cycles += opcode_main[cpustate->opcode.b.h].cycles;
2034
(*opcode_main[cpustate->opcode.b.h].function)(cpustate);
2038
if (cpustate->init_load_addr == 2) { /* Repeat next instruction */
2039
cpustate->PREVPC = cpustate->PC;
2041
debugger_instruction_hook(device, cpustate->PC);
2043
cpustate->opcode.d = M_RDOP(cpustate->PC);
2045
cpustate->tms32025_dec_cycles += (1*CLK);
2048
if (cpustate->opcode.b.h == 0xCE)
2049
{ /* Do all 0xCExx Opcodes */
2050
if (cpustate->init_load_addr) {
2051
cpustate->tms32025_dec_cycles += (1*CLK);
2054
cpustate->tms32025_dec_cycles += (1*CLK);
2056
(*opcode_CE_subset[cpustate->opcode.b.l].function)(cpustate);
2058
if ((cpustate->opcode.w.l & 0xf0f8) == 0xd000)
2059
{ /* Do all valid 0xDxxx Opcodes */
2060
if (cpustate->init_load_addr) {
2061
cpustate->tms32025_dec_cycles += (1*CLK);
2064
cpustate->tms32025_dec_cycles += (1*CLK);
2066
(*opcode_Dx_subset[cpustate->opcode.b.l].function)(cpustate);
2069
{ /* Do all other opcodes */
2070
if (cpustate->init_load_addr) {
2071
cpustate->tms32025_dec_cycles += (1*CLK);
2074
cpustate->tms32025_dec_cycles += (1*CLK);
2076
(*opcode_main[cpustate->opcode.b.h].function)(cpustate);
2078
cpustate->init_load_addr = 0;
2080
} while ((INT8)(cpustate->RPTC) != -1);
2082
cpustate->PFC = cpustate->PC;
2083
cpustate->init_load_addr = 1;
2086
process_timer(cpustate, cpustate->tms32025_dec_cycles);
2088
/**** If device is put into idle mode, exit and wait for an interrupt */
2089
while (cpustate->idle && cpustate->icount > 0)
2090
process_timer(cpustate, cpustate->icount);
2093
/**** If hold pin is active, exit if accessing external memory or if HM is set */
2094
if (cpustate->hold) {
2095
if (cpustate->external_mem_access || (HM)) {
2096
if (cpustate->icount > 0) {
2097
cpustate->icount = 0;
2106
/****************************************************************************
2107
* Set IRQ line state
2108
****************************************************************************/
2109
static void set_irq_line(tms32025_state *cpustate, int irqline, int state)
2111
/* Pending IRQs cannot be cleared */
2113
if (state != CLEAR_LINE)
2115
cpustate->IFR |= (1 << irqline);
2116
// cpustate->IFR &= 0x07;
2121
/****************************************************************************
2123
****************************************************************************/
2124
static CPU_READOP( tms32025 )
2126
tms32025_state *cpustate = get_safe_token(device);
2130
/* skip if not custom */
2131
if (!cpustate->pgmmap[offset >> 8])
2134
ptr = &((UINT8 *)&cpustate->pgmmap[offset >> 8])[offset & 0xff];
2137
case 1: *value = *((UINT8 *) ptr);
2138
case 2: *value = *((UINT16 *) ptr);
2139
case 4: *value = *((UINT32 *) ptr);
2140
case 8: *value = *((UINT64 *) ptr);
2146
/****************************************************************************
2148
****************************************************************************/
2149
static CPU_READ( tms32025 )
2151
tms32025_state *cpustate = get_safe_token(device);
2159
ptr = cpustate->pgmmap[offset >> 8];
2165
ptr = cpustate->datamap[offset >> 8];
2178
*value = ((UINT8 *)ptr)[BYTE_XOR_BE(offset & 0xff)];
2181
*value = ((UINT16 *)ptr)[(offset & 0xff) / 2];
2184
CPU_READ_NAME(tms32025)(device, space, offset + 0, 2, &temp);
2185
*value = temp << 16;
2186
CPU_READ_NAME(tms32025)(device, space, offset + 2, 2, &temp);
2187
*value |= temp & 0xffff;
2190
CPU_READ_NAME(tms32025)(device, space, offset + 0, 4, &temp);
2191
*value = temp << 32;
2192
CPU_READ_NAME(tms32025)(device, space, offset + 4, 4, &temp);
2193
*value |= temp & 0xffffffff;
2200
/****************************************************************************
2202
****************************************************************************/
2203
static CPU_WRITE( tms32025 )
2205
tms32025_state *cpustate = get_safe_token(device);
2212
ptr = cpustate->pgmmap[offset >> 8];
2218
ptr = cpustate->datamap[offset >> 8];
2231
((UINT8 *)ptr)[BYTE_XOR_BE(offset & 0xff)] = value;
2234
((UINT16 *)ptr)[(offset & 0xff) / 2] = value;
2237
CPU_WRITE_NAME(tms32025)(device, space, offset + 0, 2, value >> 16);
2238
CPU_WRITE_NAME(tms32025)(device, space, offset + 2, 2, value);
2241
CPU_WRITE_NAME(tms32025)(device, space, offset + 0, 4, value >> 32);
2242
CPU_WRITE_NAME(tms32025)(device, space, offset + 4, 4, value);
2250
/**************************************************************************
2252
**************************************************************************/
2254
static CPU_SET_INFO( tms32025 )
2256
tms32025_state *cpustate = get_safe_token(device);
2260
/* --- the following bits of info are set as 64-bit signed integers --- */
2261
case CPUINFO_INT_INPUT_STATE + TMS32025_INT0: set_irq_line(cpustate, TMS32025_INT0, info->i); break;
2262
case CPUINFO_INT_INPUT_STATE + TMS32025_INT1: set_irq_line(cpustate, TMS32025_INT1, info->i); break;
2263
case CPUINFO_INT_INPUT_STATE + TMS32025_INT2: set_irq_line(cpustate, TMS32025_INT2, info->i); break;
2264
case CPUINFO_INT_INPUT_STATE + TMS32025_TINT: set_irq_line(cpustate, TMS32025_TINT, info->i); break;
2265
case CPUINFO_INT_INPUT_STATE + TMS32025_RINT: set_irq_line(cpustate, TMS32025_RINT, info->i); break;
2266
case CPUINFO_INT_INPUT_STATE + TMS32025_XINT: set_irq_line(cpustate, TMS32025_XINT, info->i); break;
2267
case CPUINFO_INT_INPUT_STATE + TMS32025_FSX: set_fsx_line(cpustate, info->i); break;
2269
case CPUINFO_INT_PC:
2270
case CPUINFO_INT_REGISTER + TMS32025_PC: cpustate->PC = info->i; break;
2271
/* This is actually not a stack pointer, but the stack contents */
2272
case CPUINFO_INT_SP:
2273
case CPUINFO_INT_REGISTER + TMS32025_STK7: cpustate->STACK[7] = info->i; break;
2274
case CPUINFO_INT_REGISTER + TMS32025_STK6: cpustate->STACK[6] = info->i; break;
2275
case CPUINFO_INT_REGISTER + TMS32025_STK5: cpustate->STACK[5] = info->i; break;
2276
case CPUINFO_INT_REGISTER + TMS32025_STK4: cpustate->STACK[4] = info->i; break;
2277
case CPUINFO_INT_REGISTER + TMS32025_STK3: cpustate->STACK[3] = info->i; break;
2278
case CPUINFO_INT_REGISTER + TMS32025_STK2: cpustate->STACK[2] = info->i; break;
2279
case CPUINFO_INT_REGISTER + TMS32025_STK1: cpustate->STACK[1] = info->i; break;
2280
case CPUINFO_INT_REGISTER + TMS32025_STK0: cpustate->STACK[0] = info->i; break;
2281
case CPUINFO_INT_REGISTER + TMS32025_STR0: cpustate->STR0 = info->i; break;
2282
case CPUINFO_INT_REGISTER + TMS32025_STR1: cpustate->STR1 = info->i; break;
2283
case CPUINFO_INT_REGISTER + TMS32025_IFR: cpustate->IFR = info->i; break;
2284
case CPUINFO_INT_REGISTER + TMS32025_RPTC: cpustate->RPTC = info->i; break;
2285
case CPUINFO_INT_REGISTER + TMS32025_ACC: cpustate->ACC.d = info->i; break;
2286
case CPUINFO_INT_REGISTER + TMS32025_PREG: cpustate->Preg.d = info->i; break;
2287
case CPUINFO_INT_REGISTER + TMS32025_TREG: cpustate->Treg = info->i; break;
2288
case CPUINFO_INT_REGISTER + TMS32025_AR0: cpustate->AR[0] = info->i; break;
2289
case CPUINFO_INT_REGISTER + TMS32025_AR1: cpustate->AR[1] = info->i; break;
2290
case CPUINFO_INT_REGISTER + TMS32025_AR2: cpustate->AR[2] = info->i; break;
2291
case CPUINFO_INT_REGISTER + TMS32025_AR3: cpustate->AR[3] = info->i; break;
2292
case CPUINFO_INT_REGISTER + TMS32025_AR4: cpustate->AR[4] = info->i; break;
2293
case CPUINFO_INT_REGISTER + TMS32025_AR5: cpustate->AR[5] = info->i; break;
2294
case CPUINFO_INT_REGISTER + TMS32025_AR6: cpustate->AR[6] = info->i; break;
2295
case CPUINFO_INT_REGISTER + TMS32025_AR7: cpustate->AR[7] = info->i; break;
2296
case CPUINFO_INT_REGISTER + TMS32025_DRR: M_WRTRAM(cpustate, 0,info->i); break;
2297
case CPUINFO_INT_REGISTER + TMS32025_DXR: M_WRTRAM(cpustate, 1,info->i); break;
2298
case CPUINFO_INT_REGISTER + TMS32025_TIM: M_WRTRAM(cpustate, 2,info->i); break;
2299
case CPUINFO_INT_REGISTER + TMS32025_PRD: M_WRTRAM(cpustate, 3,info->i); break;
2300
case CPUINFO_INT_REGISTER + TMS32025_IMR: M_WRTRAM(cpustate, 4,info->i); break;
2301
case CPUINFO_INT_REGISTER + TMS32025_GREG: M_WRTRAM(cpustate, 5,info->i); break;
2307
/**************************************************************************
2309
**************************************************************************/
2311
CPU_GET_INFO( tms32025 )
2313
tms32025_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
2317
/* --- the following bits of info are returned as 64-bit signed integers --- */
2318
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(tms32025_state); break;
2319
case CPUINFO_INT_INPUT_LINES: info->i = 6; break;
2320
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
2321
case DEVINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
2322
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
2323
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
2324
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break;
2325
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
2326
case CPUINFO_INT_MIN_CYCLES: info->i = 1*CLK; break;
2327
case CPUINFO_INT_MAX_CYCLES: info->i = 5*CLK; break;
2329
case DEVINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break;
2330
case DEVINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break;
2331
case DEVINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = -1; break;
2332
case DEVINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 16; break;
2333
case DEVINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 16; break;
2334
case DEVINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = -1; break;
2335
case DEVINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 16; break;
2336
case DEVINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 17; break;
2337
case DEVINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = -1; break;
2339
case CPUINFO_INT_INPUT_STATE + TMS32025_INT0: info->i = (cpustate->IFR & 0x01) ? ASSERT_LINE : CLEAR_LINE; break;
2340
case CPUINFO_INT_INPUT_STATE + TMS32025_INT1: info->i = (cpustate->IFR & 0x02) ? ASSERT_LINE : CLEAR_LINE; break;
2341
case CPUINFO_INT_INPUT_STATE + TMS32025_INT2: info->i = (cpustate->IFR & 0x04) ? ASSERT_LINE : CLEAR_LINE; break;
2342
case CPUINFO_INT_INPUT_STATE + TMS32025_TINT: info->i = (cpustate->IFR & 0x08) ? ASSERT_LINE : CLEAR_LINE; break;
2343
case CPUINFO_INT_INPUT_STATE + TMS32025_RINT: info->i = (cpustate->IFR & 0x10) ? ASSERT_LINE : CLEAR_LINE; break;
2344
case CPUINFO_INT_INPUT_STATE + TMS32025_XINT: info->i = (cpustate->IFR & 0x20) ? ASSERT_LINE : CLEAR_LINE; break;
2346
case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->PREVPC; break;
2348
case CPUINFO_INT_PC:
2349
case CPUINFO_INT_REGISTER + TMS32025_PC: info->i = cpustate->PC; break;
2350
/* This is actually not a stack pointer, but the stack contents */
2351
case CPUINFO_INT_SP:
2352
case CPUINFO_INT_REGISTER + TMS32025_STK7: info->i = cpustate->STACK[7]; break;
2353
case CPUINFO_INT_REGISTER + TMS32025_STK6: info->i = cpustate->STACK[6]; break;
2354
case CPUINFO_INT_REGISTER + TMS32025_STK5: info->i = cpustate->STACK[5]; break;
2355
case CPUINFO_INT_REGISTER + TMS32025_STK4: info->i = cpustate->STACK[4]; break;
2356
case CPUINFO_INT_REGISTER + TMS32025_STK3: info->i = cpustate->STACK[3]; break;
2357
case CPUINFO_INT_REGISTER + TMS32025_STK2: info->i = cpustate->STACK[2]; break;
2358
case CPUINFO_INT_REGISTER + TMS32025_STK1: info->i = cpustate->STACK[1]; break;
2359
case CPUINFO_INT_REGISTER + TMS32025_STK0: info->i = cpustate->STACK[0]; break;
2360
case CPUINFO_INT_REGISTER + TMS32025_STR0: info->i = cpustate->STR0; break;
2361
case CPUINFO_INT_REGISTER + TMS32025_STR1: info->i = cpustate->STR1; break;
2362
case CPUINFO_INT_REGISTER + TMS32025_IFR: info->i = cpustate->IFR; break;
2363
case CPUINFO_INT_REGISTER + TMS32025_RPTC: info->i = cpustate->RPTC; break;
2364
case CPUINFO_INT_REGISTER + TMS32025_ACC: info->i = cpustate->ACC.d; break;
2365
case CPUINFO_INT_REGISTER + TMS32025_PREG: info->i = cpustate->Preg.d; break;
2366
case CPUINFO_INT_REGISTER + TMS32025_TREG: info->i = cpustate->Treg; break;
2367
case CPUINFO_INT_REGISTER + TMS32025_AR0: info->i = cpustate->AR[0]; break;
2368
case CPUINFO_INT_REGISTER + TMS32025_AR1: info->i = cpustate->AR[1]; break;
2369
case CPUINFO_INT_REGISTER + TMS32025_AR2: info->i = cpustate->AR[2]; break;
2370
case CPUINFO_INT_REGISTER + TMS32025_AR3: info->i = cpustate->AR[3]; break;
2371
case CPUINFO_INT_REGISTER + TMS32025_AR4: info->i = cpustate->AR[4]; break;
2372
case CPUINFO_INT_REGISTER + TMS32025_AR5: info->i = cpustate->AR[5]; break;
2373
case CPUINFO_INT_REGISTER + TMS32025_AR6: info->i = cpustate->AR[6]; break;
2374
case CPUINFO_INT_REGISTER + TMS32025_AR7: info->i = cpustate->AR[7]; break;
2375
case CPUINFO_INT_REGISTER + TMS32025_DRR: info->i = M_RDRAM(cpustate, 0); break;
2376
case CPUINFO_INT_REGISTER + TMS32025_DXR: info->i = M_RDRAM(cpustate, 1); break;
2377
case CPUINFO_INT_REGISTER + TMS32025_TIM: info->i = M_RDRAM(cpustate, 2); break;
2378
case CPUINFO_INT_REGISTER + TMS32025_PRD: info->i = M_RDRAM(cpustate, 3); break;
2379
case CPUINFO_INT_REGISTER + TMS32025_IMR: info->i = M_RDRAM(cpustate, 4); break;
2380
case CPUINFO_INT_REGISTER + TMS32025_GREG: info->i = M_RDRAM(cpustate, 5); break;
2382
/* --- the following bits of info are returned as pointers to data or functions --- */
2383
case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(tms32025); break;
2384
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(tms32025); break;
2385
case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(tms32025); break;
2386
case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(tms32025); break;
2387
case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(tms32025); break;
2388
case CPUINFO_FCT_BURN: info->burn = NULL; break;
2389
case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(tms32025); break;
2390
case CPUINFO_FCT_READ: info->read = CPU_READ_NAME(tms32025); break;
2391
case CPUINFO_FCT_WRITE: info->write = CPU_WRITE_NAME(tms32025); break;
2392
case CPUINFO_FCT_READOP: info->readop = CPU_READOP_NAME(tms32025); break;
2393
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
2395
/* --- the following bits of info are returned as NULL-terminated strings --- */
2396
case DEVINFO_STR_NAME: strcpy(info->s, "TMS32025"); break;
2397
case DEVINFO_STR_FAMILY: strcpy(info->s, "Texas Instruments TMS320x25"); break;
2398
case DEVINFO_STR_VERSION: strcpy(info->s, "1.10"); break;
2399
case DEVINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
2400
case DEVINFO_STR_CREDITS: strcpy(info->s, "Copyright Tony La Porta"); break;
2402
case CPUINFO_STR_FLAGS:
2403
sprintf(info->s, "arp%d%c%c%c%cdp%03x arb%d%c%c%c%c%c%c%c%c%c%c%cpm%d",
2404
(cpustate->STR0 & 0xe000) >> 13,
2405
cpustate->STR0 & 0x1000 ? 'O':'.',
2406
cpustate->STR0 & 0x0800 ? 'M':'.',
2407
cpustate->STR0 & 0x0400 ? '.':'?',
2408
cpustate->STR0 & 0x0200 ? 'I':'.',
2409
(cpustate->STR0 & 0x01ff),
2411
(cpustate->STR1 & 0xe000) >> 13,
2412
cpustate->STR1 & 0x1000 ? 'P':'D',
2413
cpustate->STR1 & 0x0800 ? 'T':'.',
2414
cpustate->STR1 & 0x0400 ? 'S':'.',
2415
cpustate->STR1 & 0x0200 ? 'C':'?',
2416
cpustate->STR0 & 0x0100 ? '.':'?',
2417
cpustate->STR1 & 0x0080 ? '.':'?',
2418
cpustate->STR1 & 0x0040 ? 'H':'.',
2419
cpustate->STR1 & 0x0020 ? 'F':'.',
2420
cpustate->STR1 & 0x0010 ? 'X':'.',
2421
cpustate->STR1 & 0x0008 ? 'f':'.',
2422
cpustate->STR1 & 0x0004 ? 'o':'i',
2423
(cpustate->STR1 & 0x0003) );
2426
case CPUINFO_STR_REGISTER + TMS32025_PC: sprintf(info->s, "PC:%04X", cpustate->PC); break;
2427
case CPUINFO_STR_REGISTER + TMS32025_STR0: sprintf(info->s, "STR0:%04X", cpustate->STR0); break;
2428
case CPUINFO_STR_REGISTER + TMS32025_STR1: sprintf(info->s, "STR1:%04X", cpustate->STR1); break;
2429
case CPUINFO_STR_REGISTER + TMS32025_IFR: sprintf(info->s, "IFR:%04X", cpustate->IFR); break;
2430
case CPUINFO_STR_REGISTER + TMS32025_RPTC: sprintf(info->s, "RPTC:%02X", cpustate->RPTC); break;
2431
case CPUINFO_STR_REGISTER + TMS32025_STK7: sprintf(info->s, "STK7:%04X", cpustate->STACK[7]); break;
2432
case CPUINFO_STR_REGISTER + TMS32025_STK6: sprintf(info->s, "STK6:%04X", cpustate->STACK[6]); break;
2433
case CPUINFO_STR_REGISTER + TMS32025_STK5: sprintf(info->s, "STK5:%04X", cpustate->STACK[5]); break;
2434
case CPUINFO_STR_REGISTER + TMS32025_STK4: sprintf(info->s, "STK4:%04X", cpustate->STACK[4]); break;
2435
case CPUINFO_STR_REGISTER + TMS32025_STK3: sprintf(info->s, "STK3:%04X", cpustate->STACK[3]); break;
2436
case CPUINFO_STR_REGISTER + TMS32025_STK2: sprintf(info->s, "STK2:%04X", cpustate->STACK[2]); break;
2437
case CPUINFO_STR_REGISTER + TMS32025_STK1: sprintf(info->s, "STK1:%04X", cpustate->STACK[1]); break;
2438
case CPUINFO_STR_REGISTER + TMS32025_STK0: sprintf(info->s, "STK0:%04X", cpustate->STACK[0]); break;
2439
case CPUINFO_STR_REGISTER + TMS32025_ACC: sprintf(info->s, "ACC:%08X", cpustate->ACC.d); break;
2440
case CPUINFO_STR_REGISTER + TMS32025_PREG: sprintf(info->s, "P:%08X", cpustate->Preg.d); break;
2441
case CPUINFO_STR_REGISTER + TMS32025_TREG: sprintf(info->s, "T:%04X", cpustate->Treg); break;
2442
case CPUINFO_STR_REGISTER + TMS32025_AR0: sprintf(info->s, "AR0:%04X", cpustate->AR[0]); break;
2443
case CPUINFO_STR_REGISTER + TMS32025_AR1: sprintf(info->s, "AR1:%04X", cpustate->AR[1]); break;
2444
case CPUINFO_STR_REGISTER + TMS32025_AR2: sprintf(info->s, "AR2:%04X", cpustate->AR[2]); break;
2445
case CPUINFO_STR_REGISTER + TMS32025_AR3: sprintf(info->s, "AR3:%04X", cpustate->AR[3]); break;
2446
case CPUINFO_STR_REGISTER + TMS32025_AR4: sprintf(info->s, "AR4:%04X", cpustate->AR[4]); break;
2447
case CPUINFO_STR_REGISTER + TMS32025_AR5: sprintf(info->s, "AR5:%04X", cpustate->AR[5]); break;
2448
case CPUINFO_STR_REGISTER + TMS32025_AR6: sprintf(info->s, "AR6:%04X", cpustate->AR[6]); break;
2449
case CPUINFO_STR_REGISTER + TMS32025_AR7: sprintf(info->s, "AR7:%04X", cpustate->AR[7]); break;
2450
case CPUINFO_STR_REGISTER + TMS32025_DRR: sprintf(info->s, "DRR:%04X", M_RDRAM(cpustate, 0)); break;
2451
case CPUINFO_STR_REGISTER + TMS32025_DXR: sprintf(info->s, "DXR:%04X", M_RDRAM(cpustate, 1)); break;
2452
case CPUINFO_STR_REGISTER + TMS32025_TIM: sprintf(info->s, "TIM:%04X", M_RDRAM(cpustate, 2)); break;
2453
case CPUINFO_STR_REGISTER + TMS32025_PRD: sprintf(info->s, "PRD:%04X", M_RDRAM(cpustate, 3)); break;
2454
case CPUINFO_STR_REGISTER + TMS32025_IMR: sprintf(info->s, "IMR:%04X", M_RDRAM(cpustate, 4)); break;
2455
case CPUINFO_STR_REGISTER + TMS32025_GREG: sprintf(info->s, "GREG:%04X", M_RDRAM(cpustate, 5)); break;
2460
/**************************************************************************
2461
* CPU-specific set_info
2462
**************************************************************************/
2464
CPU_GET_INFO( tms32026 )
2468
/* --- the following bits of info are returned as pointers to data or functions --- */
2469
case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(tms32026); break;
2471
/* --- the following bits of info are returned as NULL-terminated strings --- */
2472
case DEVINFO_STR_NAME: strcpy(info->s, "TMS32026"); break;
2474
default: CPU_GET_INFO_CALL(tms32025); break;
2478
DEFINE_LEGACY_CPU_DEVICE(TMS32025, tms32025);
2479
DEFINE_LEGACY_CPU_DEVICE(TMS32026, tms32026);
added
removed
mess/src/emu/cpu/tms32025/tms32025.c
