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Viewing changes to src/emu/cpu/m68000/m68kmmu.h

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Jordi Mallach, Emmanuel Kasper
  • Date: 2011-12-19 22:56:27 UTC
  • mfrom: (0.1.2)
  • Revision ID: package-import@ubuntu.com-20111219225627-ub5oga1oys4ogqzm
Tags: 0.144-1
http://bugs.debian.org/651538
[ Jordi Mallach ]
* Fix syntax errors in DEP5 copyright file (lintian).
* Use a versioned copyright Format specification field.
* Update Vcs-* URLs.
* Move transitional packages to the new metapackages section, and make
  them priority extra.
* Remove references to GNU/Linux and MESS sources from copyright.
* Add build variables for s390x.
* Use .xz tarballs as it cuts 4MB for the upstream sources.
* Add nplayers.ini as a patch. Update copyright file to add CC-BY-SA-3.0.

[ Emmanuel Kasper ]
* New upstream release. Closes: #651538.
* Add Free Desktop compliant png icons of various sizes taken from
  the hydroxygen iconset
* Mess is now built from a new source package, to avoid possible source
  incompatibilities between mame and the mess overlay.
* Mame-tools are not built from the mame source package anymore, but
  from the mess source package

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Lines of Context:
src/emu/cpu/m68000/m68kmmu.h
2
2
    m68kmmu.h - PMMU implementation for 68851/68030/68040
3
3
            HMMU implementation for 68020 (II and LC variants)
4
4
 
5
 
    By R. Belmont
 
5
    By R. Belmont and Hans Ostermeyer
6
6
 
7
7
    Copyright Nicola Salmoria and the MAME Team.
8
8
    Visit http://mamedev.org for licensing and usage restrictions.
56
56
        {
57
57
                case 2:         // (An)
58
58
                {
59
 
                        return REG_A[reg];
 
59
                        return REG_A(m68k)[reg];
60
60
                }
61
61
                case 3:         // (An)+
62
62
                {
94
94
                                        UINT32 ea = EA_PCDI_32(m68k);
95
95
                                        return ea;
96
96
                                }
97
 
                                default:        fatalerror("m68k: DECODE_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
 
97
                                default:        fatalerror("m68k: DECODE_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC(m68k));
98
98
                        }
99
99
                        break;
100
100
                }
101
 
                default:        fatalerror("m68k: DECODE_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC);
 
101
                default:        fatalerror("m68k: DECODE_EA_32: unhandled mode %d, reg %d at %08X\n", mode, reg, REG_PC(m68k));
102
102
        }
103
103
        return 0;
104
104
}
148
148
        }
149
149
 
150
150
        // add the entry
151
 
    // logerror("ATC[%2d] add: log %08x -> phys %08x (fc=%d)\n", found, (logical>>ps) << ps, (physical >> ps) << ps, fc);
 
151
    // printf("ATC[%2d] add: log %08x -> phys %08x (fc=%d)\n", found, (logical>>ps) << ps, (physical >> ps) << ps, fc);
152
152
        m68k->mmu_atc_tag[found] = atc_tag;
153
153
        m68k->mmu_atc_data[found] = (physical >> ps) << (ps-8);
154
154
 
166
166
void pmmu_atc_flush(m68ki_cpu_core *m68k)
167
167
{
168
168
        int i;
169
 
    // logerror("ATC flush: pc=%08x\n", REG_PPC);
 
169
    // printf("ATC flush: pc=%08x\n", REG_PPC(m68k));
170
170
 
171
171
        for (i = 0; i < MMU_ATC_ENTRIES; i++)
172
172
        {
255
255
                UINT32 address_mask = ((m68k->mmu_tt0 << 8) & 0xff000000) ^ 0xff000000;
256
256
                if ((addr_in & address_mask) == address_base)
257
257
                {
258
 
//          logerror("PMMU: pc=%x TT0 fc=%x addr_in=%08x address_mask=%08x address_base=%08x\n", m68k->ppc, fc, addr_in, address_mask, address_base);
 
258
//          printf("PMMU: pc=%x TT0 fc=%x addr_in=%08x address_mask=%08x address_base=%08x\n", m68k->ppc, fc, addr_in, address_mask, address_base);
259
259
                        return addr_in;
260
260
                }
261
261
        }
262
262
 
263
263
//  if ((++pmmu_access_count % 10000000) == 0) {
264
 
//      logerror("pmmu_translate_addr_with_fc: atc usage = %d%%\n", pmmu_atc_count*100/pmmu_access_count);
 
264
//      printf("pmmu_translate_addr_with_fc: atc usage = %d%%\n", pmmu_atc_count*100/pmmu_access_count);
265
265
//      pmmu_atc_count = pmmu_access_count = 0;
266
266
//  }
267
267
 
298
298
                                m68k->mmu_tmp_sr = M68K_MMU_SR_MODIFIED;
299
299
                        }
300
300
                        addr_out = (m68k->mmu_atc_data[i] << 8) | (addr_in & ~(~0 << ps));
301
 
//          logerror("ATC[%2d] hit: log %08x -> phys %08x  pc=%08x fc=%d\n", i, addr_in, addr_out, REG_PPC, fc);
 
301
//          printf("ATC[%2d] hit: log %08x -> phys %08x  pc=%08x fc=%d\n", i, addr_in, addr_out, REG_PPC(m68k), fc);
302
302
//          pmmu_atc_count++;
303
303
                        return addr_out;
304
304
                }
323
323
        bbits = (m68k->mmu_tc >> 8) & 0xf;
324
324
        cbits = (m68k->mmu_tc >> 4) & 0xf;
325
325
 
326
 
//  logerror("PMMU: tcr %08x limit %08x aptr %08x is %x abits %d bbits %d cbits %d\n", m68k->mmu_tc, root_limit, root_aptr, is, abits, bbits, cbits);
 
326
//  printf("PMMU: tcr %08x limit %08x aptr %08x is %x abits %d bbits %d cbits %d\n", m68k->mmu_tc, root_limit, root_aptr, is, abits, bbits, cbits);
327
327
 
328
328
        // get table A offset
329
329
        tofs = (addr_in<<is)>>(32-abits);
338
338
 
339
339
                case M68K_MMU_DF_DT1:   // page descriptor, will cause direct mapping
340
340
                        addr_out = tptr + addr_in;
341
 
//          logerror("PMMU: PC=%x root mode %d (addr_in %08x -> %08x)\n", m68k->ppc, M68K_MMU_DF_DT1, addr_in, addr_out);
 
341
//          printf("PMMU: PC=%x root mode %d (addr_in %08x -> %08x)\n", m68k->ppc, M68K_MMU_DF_DT1, addr_in, addr_out);
342
342
                        return addr_out;
343
343
 
344
344
                case M68K_MMU_DF_DT2:   // valid 4 byte descriptors
345
345
                        tofs *= 4;
346
 
//          if (verbose) logerror("PMMU: reading table A entry at %08x\n", tofs + tptr);
 
346
//          if (verbose) printf("PMMU: reading table A entry at %08x\n", tofs + tptr);
347
347
                        tbl_entry = get_dt2_table_entry(m68k,  tptr + tofs,  ptest);
348
348
                        tamode = tbl_entry & M68K_MMU_DF_DT;
349
 
//          if (verbose) logerror("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tamode, tofs);
 
349
//          if (verbose) printf("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tamode, tofs);
350
350
                        break;
351
351
 
352
352
                case M68K_MMU_DF_DT3: // valid 8 byte descriptors
353
353
                        tofs *= 8;
354
 
//          if (verbose) logerror("PMMU: reading table A entries at %08x\n", tofs + tptr);
 
354
//          if (verbose) printf("PMMU: reading table A entries at %08x\n", tofs + tptr);
355
355
                        tbl_entry = get_dt3_table_entry(m68k,  tofs + tptr, fc,  ptest);
356
356
                        tamode = tbl_entry & M68K_MMU_DF_DT;
357
 
//          if (verbose) logerror("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tamode, tofs);
 
357
//          if (verbose) printf("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tamode, tofs);
358
358
                        break;
359
359
        }
360
360
 
376
376
 
377
377
                case M68K_MMU_DF_DT2: // 4-byte table B descriptor
378
378
                        tofs *= 4;
379
 
//          if (verbose) logerror("PMMU: reading table B entry at %08x\n", tofs + tptr);
 
379
//          if (verbose) printf("PMMU: reading table B entry at %08x\n", tofs + tptr);
380
380
                        tbl_entry = get_dt2_table_entry(m68k, tptr + tofs,  ptest);
381
381
                        tbmode = tbl_entry & M68K_MMU_DF_DT;
382
 
//          if (verbose) logerror("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tbmode, tofs);
 
382
//          if (verbose) printf("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tbmode, tofs);
383
383
                        break;
384
384
 
385
385
                case M68K_MMU_DF_DT3: // 8-byte table B descriptor
386
386
                        tofs *= 8;
387
 
//          if (verbose) logerror("PMMU: reading table B entries at %08x\n", tofs + tptr);
 
387
//          if (verbose) printf("PMMU: reading table B entries at %08x\n", tofs + tptr);
388
388
                        tbl_entry = get_dt3_table_entry(m68k, tptr + tofs, fc,  ptest);
389
389
                        tbmode = tbl_entry & M68K_MMU_DF_DT;
390
390
                        tbl_entry &= ~M68K_MMU_DF_DT;
391
 
//          if (verbose) logerror("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tbmode, tofs);
 
391
//          if (verbose) printf("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tbmode, tofs);
392
392
                        break;
393
393
 
394
394
                case M68K_MMU_DF_DT1:   // early termination descriptor
420
420
 
421
421
                        case M68K_MMU_DF_DT2: // 4-byte table C descriptor
422
422
                                tofs *= 4;
423
 
//              if (verbose) logerror("PMMU: reading table C entry at %08x\n", tofs + tptr);
 
423
//              if (verbose) printf("PMMU: reading table C entry at %08x\n", tofs + tptr);
424
424
                                tbl_entry = get_dt2_table_entry(m68k, tptr + tofs, ptest);
425
425
                                tcmode = tbl_entry & M68K_MMU_DF_DT;
426
 
//              if (verbose) logerror("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tbmode, tofs);
 
426
//              if (verbose) printf("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tbmode, tofs);
427
427
                                break;
428
428
 
429
429
                        case M68K_MMU_DF_DT3: // 8-byte table C descriptor
430
430
                                tofs *= 8;
431
 
//              if (verbose) logerror("PMMU: reading table C entries at %08x\n", tofs + tptr);
 
431
//              if (verbose) printf("PMMU: reading table C entries at %08x\n", tofs + tptr);
432
432
                                tbl_entry = get_dt3_table_entry(m68k,  tptr+ tofs, fc,  ptest);
433
433
                                tcmode = tbl_entry & M68K_MMU_DF_DT;
434
 
//              if (verbose) logerror("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tcmode, tofs);
 
434
//              if (verbose) printf("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tcmode, tofs);
435
435
                                break;
436
436
 
437
437
                        case M68K_MMU_DF_DT1: // termination descriptor
500
500
                }
501
501
        }
502
502
 
503
 
        //logerror("PMMU: [%08x] => [%08x]\n", addr_in, addr_out);
 
503
        //printf("PMMU: [%08x] => [%08x]\n", addr_in, addr_out);
 
504
 
 
505
        return addr_out;
 
506
}
 
507
 
 
508
 
 
509
// FC bits: 2 = supervisor, 1 = program, 0 = data
 
510
// the 68040 is a subset of the 68851 and 68030 PMMUs - the page table sizes are fixed, there is no early termination, etc, etc.
 
511
/*INLINE*/ static UINT32 pmmu_translate_addr_with_fc_040(m68ki_cpu_core *m68k, UINT32 addr_in, UINT8 fc, UINT8 ptest)
 
512
{
 
513
        UINT32 addr_out, tt0, tt1;
 
514
 
 
515
        addr_out = addr_in;
 
516
        m68k->mmu_tmp_sr = 0;
 
517
 
 
518
        // transparent translation registers are always in force even if the PMMU itself is disabled
 
519
        // they don't do much in emulation because we never write out of order, but the write-protect and cache control features
 
520
        // are emulatable, and apparently transparent translation regions skip the page table lookup.
 
521
        if (fc & 1)     // data, use DTT0/DTT1
 
522
        {
 
523
                tt0 = m68k->mmu_dtt0;
 
524
                tt1 = m68k->mmu_dtt1;
 
525
        }
 
526
        else if (fc & 2)        // program, use ITT0/ITT1
 
527
        {
 
528
                tt0 = m68k->mmu_itt0;
 
529
                tt1 = m68k->mmu_itt1;
 
530
        }
 
531
        else
 
532
        {
 
533
                fatalerror("68040: function code %d is neither data nor program!\n", fc&7);
 
534
        }
 
535
 
 
536
        if (tt0 & 0x8000)
 
537
        {
 
538
                UINT32 mask = (tt0>>16) & 0xff;
 
539
                mask ^= 0xff;
 
540
                mask <<= 24;
 
541
 
 
542
                if ((addr_in & mask) == (tt0 & mask))
 
543
                {
 
544
//          printf("TT0 match on address %08x (TT0 = %08x, mask = %08x)\n", addr_in, tt0, mask);
 
545
                        if ((tt0 & 4) && !m68k->mmu_tmp_rw && !ptest)   // write protect?
 
546
                        {
 
547
                                if (++m68k->mmu_tmp_buserror_occurred == 1)
 
548
                                {
 
549
                                        m68k->mmu_tmp_buserror_address = addr_in;
 
550
                                }
 
551
                        }
 
552
 
 
553
                        return addr_in;
 
554
                }
 
555
        }
 
556
 
 
557
        if (tt1 & 0x8000)
 
558
        {
 
559
                UINT32 mask = (tt1>>16) & 0xff;
 
560
                mask ^= 0xff;
 
561
                mask <<= 24;
 
562
 
 
563
                if ((addr_in & mask) == (tt1 & mask))
 
564
                {
 
565
//          printf("TT1 match on address %08x (TT0 = %08x, mask = %08x)\n", addr_in, tt1, mask);
 
566
                        if ((tt1 & 4) && !m68k->mmu_tmp_rw && !ptest)   // write protect?
 
567
                        {
 
568
                                if (++m68k->mmu_tmp_buserror_occurred == 1)
 
569
                                {
 
570
                                        m68k->mmu_tmp_buserror_address = addr_in;
 
571
                                }
 
572
                        }
 
573
 
 
574
                        return addr_in;
 
575
                }
 
576
        }
 
577
 
 
578
        if (m68k->pmmu_enabled)
 
579
        {
 
580
                UINT32 root_idx = (addr_in>>25) & 0x7f;
 
581
                UINT32 ptr_idx = (addr_in>>18) & 0x7f;
 
582
                UINT32 page_idx, page;
 
583
                UINT32 root_ptr, pointer_ptr, page_ptr;
 
584
                UINT32 root_entry, pointer_entry, page_entry;
 
585
 
 
586
                // select supervisor or user root pointer
 
587
                if (fc & 4)
 
588
                {
 
589
                        root_ptr = m68k->mmu_srp_aptr + (root_idx<<2);
 
590
                }
 
591
                else
 
592
                {
 
593
                        root_ptr = m68k->mmu_urp_aptr + (root_idx<<2);
 
594
                }
 
595
 
 
596
                // get the root entry
 
597
                root_entry = m68k->program->read_dword(root_ptr);
 
598
//      printf("root entry = %08x\n", root_entry);
 
599
 
 
600
                // is UDT marked valid?
 
601
                if (root_entry & 2)
 
602
                {
 
603
                        pointer_ptr = (root_entry & ~0x1ff) + (ptr_idx<<2);
 
604
                        pointer_entry = m68k->program->read_dword(pointer_ptr);
 
605
 
 
606
//          printf("pointer entry = %08x\n", pointer_entry);
 
607
 
 
608
                        // write protected by the root or pointer entries?
 
609
                        if ((((root_entry & 4) && !m68k->mmu_tmp_rw) || ((pointer_entry & 4) && !m68k->mmu_tmp_rw)) && !ptest)
 
610
                        {
 
611
                                if (++m68k->mmu_tmp_buserror_occurred == 1)
 
612
                                {
 
613
                                        m68k->mmu_tmp_buserror_address = addr_in;
 
614
                                }
 
615
 
 
616
                                return addr_in;
 
617
                        }
 
618
 
 
619
                        // is UDT valid on the pointer entry?
 
620
                        if (!(pointer_entry & 2) && !ptest)
 
621
                        {
 
622
//              printf("Invalid pointer entry!  PC=%x, addr=%x\n", m68k->ppc, addr_in);
 
623
                                if (++m68k->mmu_tmp_buserror_occurred == 1)
 
624
                                {
 
625
                                        m68k->mmu_tmp_buserror_address = addr_in;
 
626
                                }
 
627
 
 
628
                                return addr_in;
 
629
                        }
 
630
 
 
631
                        // (fall out of these ifs into the page lookup below)
 
632
                }
 
633
                else // throw an error
 
634
                {
 
635
//          printf("Invalid root entry!  PC=%x, addr=%x\n", m68k->ppc, addr_in);
 
636
                        if (!ptest)
 
637
                        {
 
638
                                if (++m68k->mmu_tmp_buserror_occurred == 1)
 
639
                                {
 
640
                                        m68k->mmu_tmp_buserror_address = addr_in;
 
641
                                }
 
642
                        }
 
643
 
 
644
                        return addr_in;
 
645
                }
 
646
 
 
647
                // now do the page lookup
 
648
                if (m68k->mmu_tc & 0x4000)      // 8k pages?
 
649
                {
 
650
                        page_idx = (addr_in >> 13) & 0x1f;
 
651
                        page = addr_in & 0x1fff;
 
652
                        pointer_entry &= ~0x7f;
 
653
 
 
654
//          printf("8k pages: index %x page %x\n", page_idx, page);
 
655
                }
 
656
                else    // 4k pages
 
657
                {
 
658
                        page_idx = (addr_in >> 12) & 0x3f;
 
659
                        page = addr_in & 0xfff;
 
660
                        pointer_entry &= ~0xff;
 
661
 
 
662
//          printf("4k pages: index %x page %x\n", page_idx, page);
 
663
                }
 
664
 
 
665
                page_ptr = pointer_entry + (page_idx<<2);
 
666
                page_entry = m68k->program->read_dword(page_ptr);
 
667
 
 
668
//      printf("page_entry = %08x\n", page_entry);
 
669
 
 
670
                // resolve indirect page pointers
 
671
                while ((page_entry & 3) == 2)
 
672
                {
 
673
                        page_entry = m68k->program->read_dword(page_entry & ~0x3);
 
674
                }
 
675
 
 
676
                // is the page write protected or supervisor protected?
 
677
                if ((((page_entry & 4) && !m68k->mmu_tmp_rw) || ((page_entry & 0x80) && !(fc&4))) && !ptest)
 
678
                {
 
679
                        if (++m68k->mmu_tmp_buserror_occurred == 1)
 
680
                        {
 
681
                                m68k->mmu_tmp_buserror_address = addr_in;
 
682
                        }
 
683
 
 
684
                        return addr_in;
 
685
                }
 
686
 
 
687
                switch (page_entry & 3)
 
688
                {
 
689
                        case 0: // invalid
 
690
//              printf("Invalid page entry!  PC=%x, addr=%x\n", m68k->ppc, addr_in);
 
691
                                if (!ptest)
 
692
                                {
 
693
                                        if (++m68k->mmu_tmp_buserror_occurred == 1)
 
694
                                        {
 
695
                                                m68k->mmu_tmp_buserror_address = addr_in;
 
696
                                        }
 
697
                                }
 
698
 
 
699
                                return addr_in;
 
700
 
 
701
                        case 1:
 
702
                        case 3: // normal
 
703
                                if (m68k->mmu_tc & 0x4000)      // 8k pages?
 
704
                                {
 
705
                                        addr_out = (page_entry & ~0x1fff) | page;
 
706
                                }
 
707
                                else
 
708
                                {
 
709
                                        addr_out = (page_entry & ~0xfff) | page;
 
710
                                }
 
711
 
 
712
 
 
713
                                break;
 
714
 
 
715
                        case 2: // shouldn't happen
 
716
                                fatalerror("68040: got indirect final page pointer, shouldn't be possible\n");
 
717
                                break;
 
718
                }
 
719
//      if (addr_in != addr_out) printf("040MMU: [%08x] => [%08x]\n", addr_in, addr_out);
 
720
        }
504
721
 
505
722
        return addr_out;
506
723
}
510
727
*/
511
728
/*INLINE*/ static UINT32 pmmu_translate_addr(m68ki_cpu_core *m68k, UINT32 addr_in)
512
729
{
513
 
        UINT32 addr_out = pmmu_translate_addr_with_fc(m68k, addr_in, m68k->mmu_tmp_fc, 0);
 
730
        UINT32 addr_out;
 
731
 
 
732
        if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type))
 
733
        {
 
734
                addr_out = pmmu_translate_addr_with_fc_040(m68k, addr_in, m68k->mmu_tmp_fc, 0);
 
735
        }
 
736
        else
 
737
        {
 
738
                addr_out = pmmu_translate_addr_with_fc(m68k, addr_in, m68k->mmu_tmp_fc, 0);
 
739
        }
514
740
 
515
741
//  if (m68k->mmu_tmp_buserror_occurred > 0) {
516
 
//      logerror("PMMU: pc=%08x sp=%08x va=%08x pa=%08x - invalid Table mode for level=%d (buserror %d)\n",
517
 
//              REG_PPC, REG_A[7], addr_in, addr_out, m68k->mmu_tmp_sr & M68K_MMU_SR_LEVEL_3,
 
742
//      printf("PMMU: pc=%08x sp=%08x va=%08x pa=%08x - invalid Table mode for level=%d (buserror %d)\n",
 
743
//              REG_PPC(m68k), REG_A(m68k)[7], addr_in, addr_out, m68k->mmu_tmp_sr & M68K_MMU_SR_LEVEL_3,
518
744
//              m68k->mmu_tmp_buserror_occurred);
519
745
//  }
520
746
 
522
748
}
523
749
 
524
750
/*
525
 
    m68881_mmu_ops: COP 0 MMU opcode handling
526
 
 
 
751
    m68851_mmu_ops: COP 0 MMU opcode handling
527
752
*/
528
753
 
529
754
void m68881_mmu_ops(m68ki_cpu_core *m68k)
536
761
        // catch the 2 "weird" encodings up front (PBcc)
537
762
        if ((m68k->ir & 0xffc0) == 0xf0c0)
538
763
        {
539
 
                logerror("680x0: unhandled PBcc\n");
 
764
                printf("680x0: unhandled PBcc\n");
540
765
                return;
541
766
        }
542
767
        else if ((m68k->ir & 0xffc0) == 0xf080)
543
768
        {
544
 
                logerror("680x0: unhandled PBcc\n");
 
769
                printf("680x0: unhandled PBcc\n");
545
770
                return;
546
771
        }
547
772
        else    // the rest are 1111000xxxXXXXXX where xxx is the instruction family
559
784
                                        ptmp = ltmp;
560
785
                                        if (m68k->pmmu_enabled)
561
786
                                        {
562
 
                                                ptmp = pmmu_translate_addr_with_fc(m68k, ltmp, modes & 0x07, 0);
 
787
                                                if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type))
 
788
                                                {
 
789
                                                        ptmp = pmmu_translate_addr_with_fc_040(m68k, ltmp, modes & 0x07, 0);
 
790
                                                }
 
791
                                                else
 
792
                                                {
 
793
                                                        ptmp = pmmu_translate_addr_with_fc(m68k, ltmp, modes & 0x07, 0);
 
794
                                                }
563
795
                                        }
564
796
 
565
 
                    logerror("680x0: PLOADing ATC with logical %08x => phys %08x\n", ltmp, ptmp);
 
797
                    printf("680x0: PLOADing ATC with logical %08x => phys %08x\n", ltmp, ptmp);
566
798
                                        // FIXME: rw bit?
567
799
                                        pmmu_atc_add(m68k, ltmp, ptmp,  modes & 0x07);
568
800
                                        return;
579
811
                                }
580
812
                                else if (modes == 0x2800)       // PVALID (FORMAT 1)
581
813
                                {
582
 
                                        logerror("680x0: unhandled PVALID1\n");
 
814
                                        printf("680x0: unhandled PVALID1\n");
583
815
                                        return;
584
816
                                }
585
817
                                else if ((modes & 0xfff8) == 0x2c00)    // PVALID (FORMAT 2)
586
818
                                {
587
 
                                        logerror("680x0: unhandled PVALID2\n");
 
819
                                        printf("680x0: unhandled PVALID2\n");
588
820
                                        return;
589
821
                                }
590
822
                                else if ((modes & 0xe000) == 0x8000)    // PTEST
597
829
                                                fc = fc == 0 ? m68k->sfc :  m68k->dfc;
598
830
                                                break;
599
831
                                        case 1:
600
 
                                                fc = REG_D[fc &7] &7;
 
832
                                                fc = REG_D(m68k)[fc &7] &7;
601
833
                                                break;
602
834
                                        case 2:
603
835
                                                fc &=7;
604
836
                                                break;
605
837
                                        }
606
838
 
607
 
                                        p_addr = pmmu_translate_addr_with_fc(m68k, v_addr, fc, 1);
 
839
                                        if (CPU_TYPE_IS_040_PLUS(m68k->cpu_type))
 
840
                                        {
 
841
                                                p_addr = pmmu_translate_addr_with_fc_040(m68k, v_addr, fc, 1);
 
842
                                        }
 
843
                                        else
 
844
                                        {
 
845
                                                p_addr = pmmu_translate_addr_with_fc(m68k, v_addr, fc, 1);
 
846
                                        }
608
847
                                        m68k->mmu_sr = m68k->mmu_tmp_sr;
609
848
 
610
 
//                  logerror("PMMU: pc=%08x sp=%08x va=%08x pa=%08x PTEST fc=%x level=%x mmu_sr=%04x\n",
611
 
//                          m68k->ppc, REG_A[7], v_addr, p_addr, fc, (modes >> 10) & 0x07, m68k->mmu_sr);
 
849
//                  printf("PMMU: pc=%08x sp=%08x va=%08x pa=%08x PTEST fc=%x level=%x mmu_sr=%04x\n",
 
850
//                          m68k->ppc, REG_A(m68k)[7], v_addr, p_addr, fc, (modes >> 10) & 0x07, m68k->mmu_sr);
612
851
 
613
852
                                        if (modes & 0x100)
614
853
                                        {
629
868
                                                                        {
630
869
                                                                                case 0x02: // transparent translation register 0
631
870
                                                                                        WRITE_EA_32(m68k, ea, m68k->mmu_tt0);
632
 
//                                          logerror("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", m68k->ppc, m68k->mmu_tt0);
 
871
//                                          printf("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", m68k->ppc, m68k->mmu_tt0);
633
872
                                                                                        break;
634
873
                                                                                case 0x03: // transparent translation register 1
635
874
                                                                                        WRITE_EA_32(m68k, ea, m68k->mmu_tt1);
636
 
//                                          logerror("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", m68k->ppc, m68k->mmu_tt1);
 
875
//                                          printf("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", m68k->ppc, m68k->mmu_tt1);
637
876
                                                                                        break;
638
877
                                                                                case 0x10:      // translation control register
639
878
                                                                                        WRITE_EA_32(m68k, ea, m68k->mmu_tc);
640
 
//                                          logerror("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", m68k->ppc, m68k->mmu_tc);
 
879
//                                          printf("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", m68k->ppc, m68k->mmu_tc);
641
880
                                                                                        break;
642
881
 
643
882
                                                                                case 0x12: // supervisor root pointer
644
883
                                                                                        WRITE_EA_64(m68k, ea, (UINT64)m68k->mmu_srp_limit<<32 | (UINT64)m68k->mmu_srp_aptr);
645
 
//                                          logerror("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", REG_PPC, m68k->mmu_srp_limit, m68k->mmu_srp_aptr);
 
884
//                                          printf("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", REG_PPC(m68k), m68k->mmu_srp_limit, m68k->mmu_srp_aptr);
646
885
                                                                                        break;
647
886
 
648
887
                                                                                case 0x13: // CPU root pointer
649
888
                                                                                        WRITE_EA_64(m68k, ea, (UINT64)m68k->mmu_crp_limit<<32 | (UINT64)m68k->mmu_crp_aptr);
650
 
//                                          logerror("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", REG_PPC, m68k->mmu_crp_limit, m68k->mmu_crp_aptr);
 
889
//                                          printf("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", REG_PPC(m68k), m68k->mmu_crp_limit, m68k->mmu_crp_aptr);
651
890
                                                                                        break;
652
891
 
653
892
                                                                                default:
654
 
                                                                                        logerror("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68k->pc);
 
893
                                                                                        printf("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68k->pc);
655
894
                                                                                        break;
656
895
                                                                }
657
896
 
676
915
                                                                                break;
677
916
 
678
917
                                                                        case 1:
679
 
                                                                                logerror("680x0: unknown PMOVE case 1, PC %x\n", m68k->pc);
 
918
                                                                                printf("680x0: unknown PMOVE case 1, PC %x\n", m68k->pc);
680
919
                                                                                break;
681
920
 
682
921
                                                                        case 2:
684
923
                                                                                {
685
924
                                                                                        case 0: // translation control register
686
925
                                                                                                m68k->mmu_tc = READ_EA_32(m68k, ea);
687
 
//                                              logerror("PMMU: TC = %08x\n", m68k->mmu_tc);
 
926
//                                              printf("PMMU: TC = %08x\n", m68k->mmu_tc);
688
927
 
689
928
                                                                                                if (m68k->mmu_tc & 0x80000000)
690
929
                                                                                                {
691
930
                                                                                                        m68k->pmmu_enabled = 1;
692
 
//                                                  logerror("PMMU enabled\n");
 
931
//                                                  printf("PMMU enabled\n");
693
932
                                                                                                }
694
933
                                                                                                else
695
934
                                                                                                {
696
935
                                                                                                        m68k->pmmu_enabled = 0;
697
 
//                                                  logerror("PMMU disabled\n");
 
936
//                                                  printf("PMMU disabled\n");
698
937
                                                                                                }
699
938
 
700
939
                                                                                                if (!(modes & 0x100))   // flush ATC on moves to TC, SRP, CRP with FD bit clear
707
946
                                                                                                temp64 = READ_EA_64(m68k, ea);
708
947
                                                                                                m68k->mmu_srp_limit = (temp64>>32) & 0xffffffff;
709
948
                                                                                                m68k->mmu_srp_aptr = temp64 & 0xffffffff;
710
 
//                                              logerror("PMMU: SRP limit = %08x aptr = %08x\n", m68k->mmu_srp_limit, m68k->mmu_srp_aptr);
 
949
//                                              printf("PMMU: SRP limit = %08x aptr = %08x\n", m68k->mmu_srp_limit, m68k->mmu_srp_aptr);
711
950
                                                                                                if (!(modes & 0x100))
712
951
                                                                                                {
713
952
                                                                                                        pmmu_atc_flush(m68k);
718
957
                                                                                                temp64 = READ_EA_64(m68k, ea);
719
958
                                                                                                m68k->mmu_crp_limit = (temp64>>32) & 0xffffffff;
720
959
                                                                                                m68k->mmu_crp_aptr = temp64 & 0xffffffff;
721
 
//                                              logerror("PMMU: CRP limit = %08x aptr = %08x\n", m68k->mmu_crp_limit, m68k->mmu_crp_aptr);
 
960
//                                              printf("PMMU: CRP limit = %08x aptr = %08x\n", m68k->mmu_crp_limit, m68k->mmu_crp_aptr);
722
961
                                                                                                if (!(modes & 0x100))
723
962
                                                                                                {
724
963
                                                                                                        pmmu_atc_flush(m68k);
726
965
                                                                                                break;
727
966
 
728
967
                                                                                        default:
729
 
                                                                                                logerror("680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68k->pc);
 
968
                                                                                                printf("680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68k->pc);
730
969
                                                                                                break;
731
970
                                                                                }
732
971
                                                                                break;
734
973
                                                                        case 3: // MMU status
735
974
                                                                                {
736
975
                                                                                        UINT32 temp = READ_EA_32(m68k, ea);
737
 
                                                                                        logerror("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, m68k->pc);
 
976
                                                                                        printf("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, m68k->pc);
738
977
                                                                                }
739
978
                                                                                break;
740
979
                                                                }
753
992
                                                        break;
754
993
 
755
994
                                                default:
756
 
                                                        logerror("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes>>13) & 0x7, modes, m68k->pc);
 
995
                                                        printf("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes>>13) & 0x7, modes, m68k->pc);
757
996
                                                        break;
758
997
 
759
998
                                        }
761
1000
                                break;
762
1001
 
763
1002
                        default:
764
 
                                logerror("680x0: unknown PMMU instruction group %d\n", (m68k->ir>>9) & 0x7);
 
1003
                                printf("680x0: unknown PMMU instruction group %d\n", (m68k->ir>>9) & 0x7);
765
1004
                                break;
766
1005
                }
767
1006
        }
784
1023
        {
785
1024
                addr_out = addr_in & 0xffffff;
786
1025
 
787
 
                if ((addr_in >= 0x800000) && (addr_in <= 0x8fffff))
 
1026
                if ((addr_out >= 0x800000) && (addr_out <= 0x8fffff))
788
1027
                {
789
1028
                        addr_out |= 0x40000000; // ROM
790
1029
                }
791
 
                else if ((addr_in >= 0x900000) && (addr_in <= 0xefffff))
 
1030
                else if ((addr_out >= 0x900000) && (addr_out <= 0xefffff))
792
1031
                {
793
 
                        addr_out |= 0xf0ff0000; // NuBus
 
1032
                        addr_out = 0xf0000000;  // NuBus
794
1033
                        addr_out |= ((addr_in & 0xf00000)<<4);
 
1034
                        addr_out |= (addr_in & 0xfffff);
795
1035
                }
796
 
                else if (addr_in >= 0xf00000)
 
1036
                else if (addr_out >= 0xf00000)
797
1037
                {
798
1038
                        addr_out |= 0x50000000; // I/O
799
1039
                }