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Viewing changes to src/emu/cpu/sh4/sh4comn.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Jordi Mallach, Emmanuel Kasper
  • Date: 2011-12-19 22:56:27 UTC
  • mfrom: (0.1.2)
  • Revision ID: package-import@ubuntu.com-20111219225627-ub5oga1oys4ogqzm
Tags: 0.144-1
http://bugs.debian.org/651538
[ Jordi Mallach ]
* Fix syntax errors in DEP5 copyright file (lintian).
* Use a versioned copyright Format specification field.
* Update Vcs-* URLs.
* Move transitional packages to the new metapackages section, and make
  them priority extra.
* Remove references to GNU/Linux and MESS sources from copyright.
* Add build variables for s390x.
* Use .xz tarballs as it cuts 4MB for the upstream sources.
* Add nplayers.ini as a patch. Update copyright file to add CC-BY-SA-3.0.

[ Emmanuel Kasper ]
* New upstream release. Closes: #651538.
* Add Free Desktop compliant png icons of various sizes taken from
  the hydroxygen iconset
* Mess is now built from a new source package, to avoid possible source
  incompatibilities between mame and the mess overlay.
* Mame-tools are not built from the mame source package anymore, but
  from the mess source package

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Lines of Context:
src/emu/cpu/sh4/sh4comn.c
11
11
#include "sh4.h"
12
12
#include "sh4regs.h"
13
13
#include "sh4comn.h"
 
14
#include "sh3comn.h"
 
15
#include "sh4tmu.h"
 
16
#include "sh4dmac.h"
14
17
 
15
 
static const int tcnt_div[8] = { 4, 16, 64, 256, 1024, 1, 1, 1 };
16
18
static const int rtcnt_div[8] = { 0, 4, 16, 64, 256, 1024, 2048, 4096 };
17
19
static const int daysmonth[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
18
 
static const int dmasize[8] = { 8, 1, 2, 4, 32, 0, 0, 0 };
19
 
static const UINT32 exception_priority_default[] = { EXPPRI(1,1,0,0), EXPPRI(1,2,0,1), EXPPRI(1,1,0,2), EXPPRI(1,3,0,3), EXPPRI(1,4,0,4),
20
 
        EXPPRI(2,0,0,5), EXPPRI(2,1,0,6), EXPPRI(2,2,0,7), EXPPRI(2,3,0,8), EXPPRI(2,4,0,9), EXPPRI(2,4,0,10), EXPPRI(2,4,0,11), EXPPRI(2,4,0,12),
21
 
        EXPPRI(2,5,0,13), EXPPRI(2,5,0,14), EXPPRI(2,6,0,15), EXPPRI(2,6,0,16), EXPPRI(2,7,0,17), EXPPRI(2,7,0,18), EXPPRI(2,8,0,19),
22
 
        EXPPRI(2,9,0,20), EXPPRI(2,4,0,21), EXPPRI(2,10,0,22), EXPPRI(3,0,16,SH4_INTC_NMI) };
23
 
static const int exception_codes[] = { 0x000, 0x020, 0x000, 0x140, 0x140, 0x1E0, 0x0E0, 0x040, 0x0A0, 0x180, 0x1A0, 0x800, 0x820, 0x0E0,
24
 
        0x100, 0x040, 0x060, 0x0A0, 0x0C0, 0x120, 0x080, 0x160, 0x1E0, 0x1C0, 0x200, 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x2E0, 0x300,
25
 
        0x320, 0x340, 0x360, 0x380, 0x3A0, 0x3C0, 0x240, 0x2A0, 0x300, 0x360, 0x600, 0x620, 0x640, 0x660, 0x680, 0x6A0, 0x780, 0x7A0, 0x7C0,
26
 
        0x7E0, 0x6C0, 0xB00, 0xB80, 0x400, 0x420, 0x440, 0x460, 0x480, 0x4A0, 0x4C0, 0x4E0, 0x500, 0x520, 0x540, 0x700, 0x720, 0x740, 0x760,
27
 
        0x560, 0x580, 0x5A0 };
28
 
 
29
 
static const UINT16 tcnt[] = { TCNT0, TCNT1, TCNT2 };
30
 
static const UINT16 tcor[] = { TCOR0, TCOR1, TCOR2 };
31
 
static const UINT16 tcr[] = { TCR0, TCR1, TCR2 };
 
20
 
 
21
 
 
22
 
 
23
static const UINT32 exception_priority_default[] = {
 
24
        EXPPRI(1,1,0,0),                         /* Power-on Reset */
 
25
        EXPPRI(1,2,0,1),                         /* Manual Reset */
 
26
        EXPPRI(1,1,0,2),                         /* H-UDI Reset */
 
27
        EXPPRI(1,3,0,3),                         /* Inst TLB Multiple Hit */
 
28
        EXPPRI(1,4,0,4),                         /* Data TLB Multiple Hit */
 
29
 
 
30
        EXPPRI(2,0,0,5),                        /* User break Before Instruction */
 
31
        EXPPRI(2,1,0,6),                        /* Inst Address Error */
 
32
        EXPPRI(2,2,0,7),                        /* Inst TLB Miss */
 
33
        EXPPRI(2,3,0,8),                        /* Inst TLB Protection Violation */
 
34
        EXPPRI(2,4,0,9),                        /* Illegal Instruction */
 
35
        EXPPRI(2,4,0,10),                       /* Slot Illegal Instruction */
 
36
        EXPPRI(2,4,0,11),                       /* FPU Disable */
 
37
        EXPPRI(2,4,0,12),                       /* Slot FPU Disable */
 
38
        EXPPRI(2,5,0,13),                       /* Data Address Error (Read) */
 
39
        EXPPRI(2,5,0,14),                       /* Data Address Error (Write) */
 
40
        EXPPRI(2,6,0,15),                       /* Data TBL Miss Read */
 
41
        EXPPRI(2,6,0,16),                       /* Data TBL Miss Write */
 
42
        EXPPRI(2,7,0,17),                       /* Data TBL Protection Violation Read */
 
43
        EXPPRI(2,7,0,18),                       /* Data TBL Protection Violation Write */
 
44
        EXPPRI(2,8,0,19),                       /* FPU Exception */
 
45
        EXPPRI(2,9,0,20),                       /* Initial Page Write exception */
 
46
 
 
47
        EXPPRI(2,4,0,21),                       /* Unconditional TRAP */
 
48
        EXPPRI(2,10,0,22),                      /* User break After Instruction */
 
49
 
 
50
        EXPPRI(3,0,16,SH4_INTC_NMI)     /* NMI */
 
51
        /* This is copied to a table, and the IRQ priorities filled in later */
 
52
};
 
53
 
 
54
static const int exception_codes[] =
 
55
 
 
56
{ 0x000, /* Power-on Reset */
 
57
  0x020, /* Manual Reset */
 
58
  0x000, /* H-UDI Reset */
 
59
  0x140, /* Inst TLB Multiple Hit */
 
60
  0x140, /* Data TLB Multiple Hit */
 
61
 
 
62
  0x1E0, /* User break Before Instruction */
 
63
  0x0E0, /* Inst Address Error */
 
64
  0x040, /* Inst TLB Miss */
 
65
  0x0A0, /* Inst TLB Protection Violation */
 
66
  0x180, /* Illegal Instruction */
 
67
  0x1A0, /* Slot Illegal Instruction */
 
68
  0x800, /* FPU Disable */
 
69
  0x820, /* Slot FPU Disable */
 
70
  0x0E0, /* Data Address Error (Read) */
 
71
  0x100, /* Data Address Error (Write) */
 
72
  0x040, /* Data TBL Miss Read */
 
73
  0x060, /* Data TBL Miss Write */
 
74
  0x0A0, /* Data TBL Protection Violation Read */
 
75
  0x0C0, /* Data TBL Protection Violation Write */
 
76
  0x120, /* FPU Exception */
 
77
  0x080, /* Initial Page Write exception */
 
78
 
 
79
  0x160, /* Unconditional TRAP */
 
80
  0x1E0, /* User break After Instruction */
 
81
 
 
82
  0x1C0, /* NMI */     /* SH4_INTC_NMI=23 represents this location in this list.. */
 
83
 
 
84
  0x200, /* EX Irq 0 */
 
85
  0x220, /*        1 */
 
86
  0x240, /*        2 */
 
87
  0x260, /*        3 */
 
88
  0x280, /*        4 */
 
89
  0x2A0, /*        5 */
 
90
  0x2C0, /*        6 */
 
91
  0x2E0, /*        7 */
 
92
  0x300, /*        8 */
 
93
  0x320, /*        9 */
 
94
  0x340, /*        A */
 
95
  0x360, /*        B */
 
96
  0x380, /*        C */
 
97
  0x3A0, /*        D */
 
98
  0x3C0, /*        E */
 
99
 
 
100
  0x240, /* SH4_INTC_IRL0 */
 
101
  0x2A0, /* SH4_INTC_IRL1 */
 
102
  0x300, /* SH4_INTC_IRL2 */
 
103
  0x360, /* SH4_INTC_IRL3 */
 
104
 
 
105
  0x600, /* HUDI */
 
106
  0x620, /* SH4_INTC_GPOI */
 
107
  0x640, /* SH4_INTC_DMTE0 */
 
108
  0x660, /* SH4_INTC_DMTE1 */
 
109
  0x680, /* SH4_INTC_DMTE2 */
 
110
  0x6A0, /* SH4_INTC_DMTE3 */
 
111
 
 
112
  0x780, /* SH4_INTC_DMTE4 */
 
113
  0x7A0, /* SH4_INTC_DMTE5 */
 
114
  0x7C0, /* SH4_INTC_DMTE6 */
 
115
  0x7E0, /* SH4_INTC_DMTE7 */
 
116
 
 
117
  0x6C0, /* SH4_INTC_DMAE */
 
118
 
 
119
  0xB00, /* SH4_INTC_TUNI3 */
 
120
  0xB80, /* SH4_INTC_TUNI4 */
 
121
  0x400, /* SH4_INTC_TUNI0 */
 
122
  0x420, /* SH4_INTC_TUNI1 */
 
123
  0x440, /* SH4_INTC_TUNI2 */
 
124
  0x460, /* SH4_INTC_TICPI2 */
 
125
  0x480, /* SH4_INTC_ATI */
 
126
  0x4A0, /* SH4_INTC_PRI */
 
127
  0x4C0, /* SH4_INTC_CUI */
 
128
  0x4E0, /* SH4_INTC_SCI1ERI */
 
129
  0x500, /* SH4_INTC_SCI1RXI */
 
130
  0x520, /* SH4_INTC_SCI1TXI */
 
131
  0x540, /* SH4_INTC_SCI1TEI */
 
132
 
 
133
  0x700, /* SH4_INTC_SCIFERI */
 
134
  0x720, /* SH4_INTC_SCIFRXI */
 
135
  0x740, /* SH4_INTC_SCIFBRI */
 
136
  0x760, /* SH4_INTC_SCIFTXI */
 
137
  0x560, /* SH4_INTC_ITI */
 
138
  0x580, /* SH4_INTC_RCMI */
 
139
  0x5A0 /* SH4_INTC_ROVI */
 
140
};
 
141
 
 
142
/* SH3 INTEVT2 uses a different table - values of -1 aren't filled in yet, some may not exist on the sh3. */
 
143
/* The above table should differ too, some things depend on the interrupt level rather than beign fixed values */
 
144
 
 
145
static const int sh3_intevt2_exception_codes[] =
 
146
 
 
147
{ 0x000, /* Power-on Reset */
 
148
  -1, /* Manual Reset */
 
149
  -1, /* H-UDI Reset */
 
150
  -1, /* Inst TLB Multiple Hit */
 
151
  -1, /* Data TLB Multiple Hit */
 
152
 
 
153
  -1, /* User break Before Instruction */
 
154
  -1, /* Inst Address Error */
 
155
  -1, /* Inst TLB Miss */
 
156
  -1, /* Inst TLB Protection Violation */
 
157
  -1, /* Illegal Instruction */
 
158
  -1, /* Slot Illegal Instruction */
 
159
  -1, /* FPU Disable */
 
160
  -1, /* Slot FPU Disable */
 
161
  -1, /* Data Address Error (Read) */
 
162
  -1, /* Data Address Error (Write) */
 
163
  -1, /* Data TBL Miss Read */
 
164
  -1, /* Data TBL Miss Write */
 
165
  -1, /* Data TBL Protection Violation Read */
 
166
  -1, /* Data TBL Protection Violation Write */
 
167
  -1, /* FPU Exception */
 
168
  -1, /* Initial Page Write exception */
 
169
 
 
170
  -1, /* Unconditional TRAP */
 
171
  -1, /* User break After Instruction */
 
172
 
 
173
  -1, /* NMI */     /* SH4_INTC_NMI=23 represents this location in this list.. */
 
174
 
 
175
  -1, /* EX Irq 0 */
 
176
  -1, /*        1 */
 
177
  -1, /*        2 */
 
178
  -1, /*        3 */
 
179
  -1, /*        4 */
 
180
  -1, /*        5 */
 
181
  -1, /*        6 */
 
182
  -1, /*        7 */
 
183
  -1, /*        8 */
 
184
  -1, /*        9 */
 
185
  -1, /*        A */
 
186
  -1, /*        B */
 
187
  -1, /*        C */
 
188
  -1, /*        D */
 
189
  -1, /*        E */
 
190
 
 
191
  0x600, /* SH4_INTC_IRL0 */
 
192
  0x620, /* SH4_INTC_IRL1 */
 
193
  0x640, /* SH4_INTC_IRL2 */
 
194
  0x660, /* SH4_INTC_IRL3 */
 
195
    /* todo: SH3 should have lines 4+5 too? */
 
196
 
 
197
  -1, /* HUDI */
 
198
  -1, /* SH4_INTC_GPOI */
 
199
  -1, /* SH4_INTC_DMTE0 */
 
200
  -1, /* SH4_INTC_DMTE1 */
 
201
  -1, /* SH4_INTC_DMTE2 */
 
202
  -1, /* SH4_INTC_DMTE3 */
 
203
 
 
204
  -1, /* SH4_INTC_DMTE4 */
 
205
  -1, /* SH4_INTC_DMTE5 */
 
206
  -1, /* SH4_INTC_DMTE6 */
 
207
  -1, /* SH4_INTC_DMTE7 */
 
208
 
 
209
  -1, /* SH4_INTC_DMAE */
 
210
 
 
211
  -1, /* SH4_INTC_TUNI3 */
 
212
  -1, /* SH4_INTC_TUNI4 */
 
213
  0x400, /* SH4_INTC_TUNI0 */
 
214
  0x420, /* SH4_INTC_TUNI1 */
 
215
  0x440, /* SH4_INTC_TUNI2 */
 
216
  0x460, /* SH4_INTC_TICPI2 */
 
217
  -1, /* SH4_INTC_ATI */
 
218
  -1, /* SH4_INTC_PRI */
 
219
  -1, /* SH4_INTC_CUI */
 
220
  -1, /* SH4_INTC_SCI1ERI */
 
221
  -1, /* SH4_INTC_SCI1RXI */
 
222
  -1, /* SH4_INTC_SCI1TXI */
 
223
  -1, /* SH4_INTC_SCI1TEI */
 
224
 
 
225
  -1, /* SH4_INTC_SCIFERI */
 
226
  -1, /* SH4_INTC_SCIFRXI */
 
227
  -1, /* SH4_INTC_SCIFBRI */
 
228
  -1, /* SH4_INTC_SCIFTXI */
 
229
  -1, /* SH4_INTC_ITI */
 
230
  -1, /* SH4_INTC_RCMI */
 
231
  -1 /* SH4_INTC_ROVI */
 
232
};
 
233
 
 
234
 
32
235
 
33
236
void sh4_change_register_bank(sh4_state *sh4, int to)
34
237
{
120
323
        for (a=0;a <= SH4_INTC_ROVI;a++)
121
324
        {
122
325
                if (sh4->exception_requesting[a])
123
 
                        if ((((int)sh4->exception_priority[a] >> 8) & 255) > z)
 
326
                {
 
327
                        int pri = (((int)sh4->exception_priority[a] >> 8) & 255);
 
328
                        //logerror("pri is %02x z is %02x\n",pri,z);
 
329
                        if (pri > z)
124
330
                        {
 
331
                                //logerror("will test\n");
125
332
                                sh4->test_irq = 1; // will check for exception at end of instructions
126
333
                                break;
127
334
                        }
 
335
                }
128
336
        }
129
337
}
130
338
 
131
339
void sh4_exception_request(sh4_state *sh4, int exception) // start requesting an exception
132
340
{
 
341
        //logerror("sh4_exception_request a\n");
133
342
        if (!sh4->exception_requesting[exception])
134
343
        {
 
344
                //logerror("sh4_exception_request b\n");
135
345
                sh4->exception_requesting[exception] = 1;
136
346
                sh4->pending_irq++;
137
347
                sh4_exception_recompute(sh4);
161
371
{
162
372
        UINT32 vector;
163
373
 
164
 
        if (exception < SH4_INTC_NMI)
165
 
                return; // Not yet supported
166
 
        if (exception == SH4_INTC_NMI) {
167
 
                if ((sh4->sr & BL) && (!(sh4->m[ICR] & 0x200)))
168
 
                        return;
169
 
                sh4->m[ICR] &= ~0x200;
170
 
                sh4->m[INTEVT] = 0x1c0;
171
 
                vector = 0x600;
172
 
                sh4->irq_callback(sh4->device, INPUT_LINE_NMI);
173
 
                LOG(("SH-4 '%s' nmi exception after [%s]\n", sh4->device->tag(), message));
174
 
        } else {
175
 
//      if ((sh4->m[ICR] & 0x4000) && (sh4->nmi_line_state == ASSERT_LINE))
176
 
//          return;
177
 
                if (sh4->sr & BL)
178
 
                        return;
179
 
                if (((sh4->exception_priority[exception] >> 8) & 255) <= ((sh4->sr >> 4) & 15))
180
 
                        return;
181
 
                sh4->m[INTEVT] = exception_codes[exception];
182
 
                vector = 0x600;
183
 
                if ((exception >= SH4_INTC_IRL0) && (exception <= SH4_INTC_IRL3))
184
 
                        sh4->irq_callback(sh4->device, SH4_INTC_IRL0-exception+SH4_IRL0);
 
374
 
 
375
        if (sh4->cpu_type == CPU_TYPE_SH4)
 
376
        {
 
377
                if (exception < SH4_INTC_NMI)
 
378
                        return; // Not yet supported
 
379
                if (exception == SH4_INTC_NMI) {
 
380
                        if ((sh4->sr & BL) && (!(sh4->m[ICR] & 0x200)))
 
381
                                return;
 
382
 
 
383
                        sh4->m[ICR] &= ~0x200;
 
384
                        sh4->m[INTEVT] = 0x1c0;
 
385
 
 
386
 
 
387
                        vector = 0x600;
 
388
                        sh4->irq_callback(sh4->device, INPUT_LINE_NMI);
 
389
                        LOG(("SH-4 '%s' nmi exception after [%s]\n", sh4->device->tag(), message));
 
390
                } else {
 
391
        //      if ((sh4->m[ICR] & 0x4000) && (sh4->nmi_line_state == ASSERT_LINE))
 
392
        //          return;
 
393
                        if (sh4->sr & BL)
 
394
                                return;
 
395
                        if (((sh4->exception_priority[exception] >> 8) & 255) <= ((sh4->sr >> 4) & 15))
 
396
                                return;
 
397
                        sh4->m[INTEVT] = exception_codes[exception];
 
398
                        vector = 0x600;
 
399
                        if ((exception >= SH4_INTC_IRL0) && (exception <= SH4_INTC_IRL3))
 
400
                                sh4->irq_callback(sh4->device, SH4_INTC_IRL0-exception+SH4_IRL0);
 
401
                        else
 
402
                                sh4->irq_callback(sh4->device, SH4_IRL3+1);
 
403
                        LOG(("SH-4 '%s' interrupt exception #%d after [%s]\n", sh4->device->tag(), exception, message));
 
404
                }
 
405
        }
 
406
        else /* SH3 exceptions */
 
407
        {
 
408
                /***** ASSUME THIS TO BE WRONG FOR NOW *****/
 
409
 
 
410
                if (exception < SH4_INTC_NMI)
 
411
                        return; // Not yet supported
 
412
                if (exception == SH4_INTC_NMI)
 
413
                {
 
414
                        return;
 
415
                }
185
416
                else
186
 
                        sh4->irq_callback(sh4->device, SH4_IRL3+1);
187
 
                LOG(("SH-4 '%s' interrupt exception #%d after [%s]\n", sh4->device->tag(), exception, message));
 
417
                {
 
418
 
 
419
                        if (sh4->sr & BL)
 
420
                                return;
 
421
                        if (((sh4->exception_priority[exception] >> 8) & 255) <= ((sh4->sr >> 4) & 15))
 
422
                                return;
 
423
 
 
424
 
 
425
                        vector = 0x600;
 
426
 
 
427
                        if ((exception >= SH4_INTC_IRL0) && (exception <= SH4_INTC_IRL3))
 
428
                                sh4->irq_callback(sh4->device, SH4_INTC_IRL0-exception+SH4_IRL0);
 
429
                        else
 
430
                                sh4->irq_callback(sh4->device, SH4_IRL3+1);
 
431
 
 
432
                        if (sh3_intevt2_exception_codes[exception]==-1)
 
433
                                fatalerror("sh3_intevt2_exception_codes unpopulated for exception %02x\n", exception);
 
434
 
 
435
                        sh4->m_sh3internal_lower[INTEVT2] = sh3_intevt2_exception_codes[exception];
 
436
                        sh4->m_sh3internal_upper[SH3_EXPEVT_ADDR] = exception_codes[exception];
 
437
 
 
438
 
 
439
                        LOG(("SH-3 '%s' interrupt exception #%d after [%s]\n", sh4->device->tag(), exception, message));
 
440
                }
 
441
 
 
442
                /***** END ASSUME THIS TO BE WRONG FOR NOW *****/
188
443
        }
189
444
        sh4_exception_checkunrequest(sh4, exception);
190
445
 
207
462
        if(sh4->sleep_mode == 1) { sh4->sleep_mode = 2; }
208
463
}
209
464
 
 
465
 
210
466
static UINT32 compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor)
211
467
{
212
468
        // elapsed:total = x : ticks
219
475
{
220
476
UINT32 ticks;
221
477
 
 
478
        if (sh4->cpu_type != CPU_TYPE_SH4)
 
479
                fatalerror("sh4_refresh_timer_recompute uses sh4->m[] with SH3\n");
 
480
 
 
481
 
222
482
        //if rtcnt < rtcor then rtcor-rtcnt
223
483
        //if rtcnt >= rtcor then 256-rtcnt+rtcor=256+rtcor-rtcnt
224
484
        ticks = sh4->m[RTCOR]-sh4->m[RTCNT];
228
488
        sh4->refresh_timer_base = sh4->m[RTCNT];
229
489
}
230
490
 
231
 
/*-------------------------------------------------
232
 
    sh4_scale_up_mame_time - multiply a attotime by
233
 
    a (constant+1) where 0 <= constant < 2^32
234
 
-------------------------------------------------*/
235
 
 
236
 
INLINE attotime sh4_scale_up_mame_time(attotime _time1, UINT32 factor1)
237
 
{
238
 
        return _time1 * factor1 + _time1;
239
 
}
240
 
 
241
 
static UINT32 compute_ticks_timer(emu_timer *timer, int hertz, int divisor)
242
 
{
243
 
        double ret;
244
 
 
245
 
        ret=((timer->remaining().as_double() * (double)hertz) / (double)divisor) - 1;
246
 
        return (UINT32)ret;
247
 
}
248
 
 
249
 
static void sh4_timer_recompute(sh4_state *sh4, int which)
250
 
{
251
 
        double ticks;
252
 
 
253
 
        ticks = sh4->m[tcnt[which]];
254
 
        sh4->timer[which]->adjust(sh4_scale_up_mame_time(attotime::from_hz(sh4->pm_clock) * tcnt_div[sh4->m[tcr[which]] & 7], ticks), which);
255
 
}
256
491
 
257
492
static TIMER_CALLBACK( sh4_refresh_timer_callback )
258
493
{
259
494
        sh4_state *sh4 = (sh4_state *)ptr;
260
495
 
 
496
        if (sh4->cpu_type != CPU_TYPE_SH4)
 
497
                fatalerror("sh4_refresh_timer_callback uses sh4->m[] with SH3\n");
 
498
 
261
499
        sh4->m[RTCNT] = 0;
262
500
        sh4_refresh_timer_recompute(sh4);
263
501
        sh4->m[RTCSR] |= 128;
276
514
{
277
515
        int carry, year, leap, days;
278
516
 
 
517
        if (sh4->cpu_type != CPU_TYPE_SH4)
 
518
                fatalerror("increment_rtc_time uses sh4->m[] with SH3\n");
 
519
 
279
520
        if (mode == 0)
280
521
        {
281
522
                carry = 0;
369
610
{
370
611
        sh4_state *sh4 = (sh4_state *)ptr;
371
612
 
 
613
        if (sh4->cpu_type != CPU_TYPE_SH4)
 
614
        {
 
615
                logerror("sh4_rtc_timer_callback uses sh4->m[] with SH3\n");
 
616
                return;
 
617
        }
 
618
 
372
619
        sh4->rtc_timer->adjust(attotime::from_hz(128));
373
620
        sh4->m[R64CNT] = (sh4->m[R64CNT]+1) & 0x7f;
374
621
        if (sh4->m[R64CNT] == 64)
379
626
        }
380
627
}
381
628
 
382
 
static TIMER_CALLBACK( sh4_timer_callback )
383
 
{
384
 
        static const UINT16 tuni[] = { SH4_INTC_TUNI0, SH4_INTC_TUNI1, SH4_INTC_TUNI2 };
385
 
        sh4_state *sh4 = (sh4_state *)ptr;
386
 
        int which = param;
387
 
        int idx = tcr[which];
388
 
 
389
 
        sh4->m[tcnt[which]] = sh4->m[tcor[which]];
390
 
        sh4_timer_recompute(sh4, which);
391
 
        sh4->m[idx] = sh4->m[idx] | 0x100;
392
 
        if (sh4->m[idx] & 0x20)
393
 
                sh4_exception_request(sh4, tuni[which]);
394
 
}
395
 
 
396
 
static TIMER_CALLBACK( sh4_dmac_callback )
397
 
{
398
 
        sh4_state *sh4 = (sh4_state *)ptr;
399
 
        int channel = param;
400
 
 
401
 
        LOG(("SH4 '%s': DMA %d complete\n", sh4->device->tag(), channel));
402
 
        sh4->dma_timer_active[channel] = 0;
403
 
        switch (channel)
404
 
        {
405
 
        case 0:
406
 
                sh4->m[DMATCR0] = 0;
407
 
                sh4->m[CHCR0] |= 2;
408
 
                if (sh4->m[CHCR0] & 4)
409
 
                        sh4_exception_request(sh4, SH4_INTC_DMTE0);
410
 
                break;
411
 
        case 1:
412
 
                sh4->m[DMATCR1] = 0;
413
 
                sh4->m[CHCR1] |= 2;
414
 
                if (sh4->m[CHCR1] & 4)
415
 
                        sh4_exception_request(sh4, SH4_INTC_DMTE1);
416
 
                break;
417
 
        case 2:
418
 
                sh4->m[DMATCR2] = 0;
419
 
                sh4->m[CHCR2] |= 2;
420
 
                if (sh4->m[CHCR2] & 4)
421
 
                        sh4_exception_request(sh4, SH4_INTC_DMTE2);
422
 
                break;
423
 
        case 3:
424
 
                sh4->m[DMATCR3] = 0;
425
 
                sh4->m[CHCR3] |= 2;
426
 
                if (sh4->m[CHCR3] & 4)
427
 
                        sh4_exception_request(sh4, SH4_INTC_DMTE3);
428
 
                break;
429
 
        }
430
 
}
431
 
 
432
 
static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr)
433
 
{
434
 
        int incs, incd, size;
435
 
        UINT32 src, dst, count;
436
 
 
437
 
        incd = (chcr >> 14) & 3;
438
 
        incs = (chcr >> 12) & 3;
439
 
        size = dmasize[(chcr >> 4) & 7];
440
 
        if(incd == 3 || incs == 3)
441
 
        {
442
 
                logerror("SH4: DMA: bad increment values (%d, %d, %d, %04x)\n", incd, incs, size, chcr);
443
 
                return 0;
444
 
        }
445
 
        src   = *sar;
446
 
        dst   = *dar;
447
 
        count = *dmatcr;
448
 
        if (!count)
449
 
                count = 0x1000000;
450
 
 
451
 
        LOG(("SH4: DMA %d start %x, %x, %x, %04x, %d, %d, %d\n", channel, src, dst, count, chcr, incs, incd, size));
452
 
 
453
 
        if (timermode == 1)
454
 
        {
455
 
                sh4->dma_timer_active[channel] = 1;
456
 
                sh4->dma_timer[channel]->adjust(sh4->device->cycles_to_attotime(2*count+1), channel);
457
 
        }
458
 
        else if (timermode == 2)
459
 
        {
460
 
                sh4->dma_timer_active[channel] = 1;
461
 
                sh4->dma_timer[channel]->adjust(attotime::zero, channel);
462
 
        }
463
 
 
464
 
        src &= AM;
465
 
        dst &= AM;
466
 
 
467
 
        switch(size)
468
 
        {
469
 
        case 1: // 8 bit
470
 
                for(;count > 0; count --)
471
 
                {
472
 
                        if(incs == 2)
473
 
                                src --;
474
 
                        if(incd == 2)
475
 
                                dst --;
476
 
                        sh4->program->write_byte(dst, sh4->program->read_byte(src));
477
 
                        if(incs == 1)
478
 
                                src ++;
479
 
                        if(incd == 1)
480
 
                                dst ++;
481
 
                }
482
 
                break;
483
 
        case 2: // 16 bit
484
 
                src &= ~1;
485
 
                dst &= ~1;
486
 
                for(;count > 0; count --)
487
 
                {
488
 
                        if(incs == 2)
489
 
                                src -= 2;
490
 
                        if(incd == 2)
491
 
                                dst -= 2;
492
 
                        sh4->program->write_word(dst, sh4->program->read_word(src));
493
 
                        if(incs == 1)
494
 
                                src += 2;
495
 
                        if(incd == 1)
496
 
                                dst += 2;
497
 
                }
498
 
                break;
499
 
        case 8: // 64 bit
500
 
                src &= ~7;
501
 
                dst &= ~7;
502
 
                for(;count > 0; count --)
503
 
                {
504
 
                        if(incs == 2)
505
 
                                src -= 8;
506
 
                        if(incd == 2)
507
 
                                dst -= 8;
508
 
                        sh4->program->write_qword(dst, sh4->program->read_qword(src));
509
 
                        if(incs == 1)
510
 
                                src += 8;
511
 
                        if(incd == 1)
512
 
                                dst += 8;
513
 
 
514
 
                }
515
 
                break;
516
 
        case 4: // 32 bit
517
 
                src &= ~3;
518
 
                dst &= ~3;
519
 
                for(;count > 0; count --)
520
 
                {
521
 
                        if(incs == 2)
522
 
                                src -= 4;
523
 
                        if(incd == 2)
524
 
                                dst -= 4;
525
 
                        sh4->program->write_dword(dst, sh4->program->read_dword(src));
526
 
                        if(incs == 1)
527
 
                                src += 4;
528
 
                        if(incd == 1)
529
 
                                dst += 4;
530
 
 
531
 
                }
532
 
                break;
533
 
        case 32:
534
 
                src &= ~31;
535
 
                dst &= ~31;
536
 
                for(;count > 0; count --)
537
 
                {
538
 
                        if(incs == 2)
539
 
                                src -= 32;
540
 
                        if(incd == 2)
541
 
                                dst -= 32;
542
 
                        sh4->program->write_qword(dst, sh4->program->read_qword(src));
543
 
                        sh4->program->write_qword(dst+8, sh4->program->read_qword(src+8));
544
 
                        sh4->program->write_qword(dst+16, sh4->program->read_qword(src+16));
545
 
                        sh4->program->write_qword(dst+24, sh4->program->read_qword(src+24));
546
 
                        if(incs == 1)
547
 
                                src += 32;
548
 
                        if(incd == 1)
549
 
                                dst += 32;
550
 
                }
551
 
                break;
552
 
        }
553
 
        *sar    = (*sar & !AM) | src;
554
 
        *dar    = (*dar & !AM) | dst;
555
 
        *dmatcr = count;
556
 
        return 1;
557
 
}
558
 
 
559
 
static void sh4_dmac_check(sh4_state *sh4, int channel)
560
 
{
561
 
UINT32 dmatcr,chcr,sar,dar;
562
 
 
563
 
        switch (channel)
564
 
        {
565
 
        case 0:
566
 
                sar = sh4->m[SAR0];
567
 
                dar = sh4->m[DAR0];
568
 
                chcr = sh4->m[CHCR0];
569
 
                dmatcr = sh4->m[DMATCR0];
570
 
                break;
571
 
        case 1:
572
 
                sar = sh4->m[SAR1];
573
 
                dar = sh4->m[DAR1];
574
 
                chcr = sh4->m[CHCR1];
575
 
                dmatcr = sh4->m[DMATCR1];
576
 
                break;
577
 
        case 2:
578
 
                sar = sh4->m[SAR2];
579
 
                dar = sh4->m[DAR2];
580
 
                chcr = sh4->m[CHCR2];
581
 
                dmatcr = sh4->m[DMATCR2];
582
 
                break;
583
 
        case 3:
584
 
                sar = sh4->m[SAR3];
585
 
                dar = sh4->m[DAR3];
586
 
                chcr = sh4->m[CHCR3];
587
 
                dmatcr = sh4->m[DMATCR3];
588
 
                break;
589
 
        default:
590
 
                return;
591
 
        }
592
 
        if (chcr & sh4->m[DMAOR] & 1)
593
 
        {
594
 
                if ((((chcr >> 8) & 15) < 4) || (((chcr >> 8) & 15) > 6))
595
 
                        return;
596
 
                if (!sh4->dma_timer_active[channel] && !(chcr & 2) && !(sh4->m[DMAOR] & 6))
597
 
                        sh4_dma_transfer(sh4, channel, 1, chcr, &sar, &dar, &dmatcr);
598
 
        }
599
 
        else
600
 
        {
601
 
                if (sh4->dma_timer_active[channel])
602
 
                {
603
 
                        logerror("SH4: DMA %d cancelled in-flight but all data transferred", channel);
604
 
                        sh4->dma_timer[channel]->adjust(attotime::never, channel);
605
 
                        sh4->dma_timer_active[channel] = 0;
606
 
                }
607
 
        }
608
 
}
609
 
 
610
 
static void sh4_dmac_nmi(sh4_state *sh4) // manage dma when nmi
611
 
{
612
 
int s;
613
 
 
614
 
        sh4->m[DMAOR] |= 2; // nmif = 1
 
629
 
 
630
static void sh4_dmac_nmi(sh4_state *sh4) // manage dma when nmi gets asserted
 
631
{
 
632
        int s;
 
633
 
 
634
        sh4->SH4_DMAOR |= DMAOR_NMIF;
615
635
        for (s = 0;s < 4;s++)
616
636
        {
617
637
                if (sh4->dma_timer_active[s])
623
643
        }
624
644
}
625
645
 
 
646
void sh4_handler_ipra_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask)
 
647
{
 
648
        COMBINE_DATA(&sh4->SH4_IPRA);
 
649
        /* 15 - 12 TMU0 */
 
650
        /* 11 -  8 TMU1 */
 
651
        /*  7 -  4 TMU2 */
 
652
        /*  3 -  0 RTC  */
 
653
        sh4->exception_priority[SH4_INTC_ATI]     = INTPRI(sh4->SH4_IPRA & 0x000f, SH4_INTC_ATI);
 
654
        sh4->exception_priority[SH4_INTC_PRI]     = INTPRI(sh4->SH4_IPRA & 0x000f, SH4_INTC_PRI);
 
655
        sh4->exception_priority[SH4_INTC_CUI]     = INTPRI(sh4->SH4_IPRA & 0x000f, SH4_INTC_CUI);
 
656
 
 
657
        sh4->exception_priority[SH4_INTC_TUNI2]  = INTPRI((sh4->SH4_IPRA & 0x00f0) >> 4, SH4_INTC_TUNI2);
 
658
        sh4->exception_priority[SH4_INTC_TICPI2] = INTPRI((sh4->SH4_IPRA & 0x00f0) >> 4, SH4_INTC_TICPI2);
 
659
 
 
660
        sh4->exception_priority[SH4_INTC_TUNI1]  = INTPRI((sh4->SH4_IPRA & 0x0f00) >> 8, SH4_INTC_TUNI1);
 
661
 
 
662
        sh4->exception_priority[SH4_INTC_TUNI0]  = INTPRI((sh4->SH4_IPRA & 0xf000) >> 12, SH4_INTC_TUNI0);
 
663
 
 
664
        logerror("setting priorities TMU0 %01x TMU1 %01x TMU2 %01x RTC %01x\n", (sh4->SH4_IPRA & 0xf000)>>12, (sh4->SH4_IPRA & 0x0f00)>>8, (sh4->SH4_IPRA & 0x00f0)>>4, (sh4->SH4_IPRA & 0x000f)>>0);
 
665
 
 
666
        sh4_exception_recompute(sh4);
 
667
}
 
668
 
 
669
 
626
670
WRITE32_HANDLER( sh4_internal_w )
627
671
{
628
672
        sh4_state *sh4 = get_safe_token(&space->device());
630
674
        UINT32 addr = (offset << 2) + 0xfe000000;
631
675
        offset = ((addr & 0xfc) >> 2) | ((addr & 0x1fe0000) >> 11);
632
676
 
 
677
        if (sh4->cpu_type != CPU_TYPE_SH4)
 
678
                fatalerror("sh4_internal_w uses sh4->m[] with SH3\n");
 
679
 
633
680
        UINT32 old = sh4->m[offset];
634
681
        COMBINE_DATA(sh4->m+offset);
635
682
 
638
685
        switch( offset )
639
686
        {
640
687
        case MMUCR: // MMU Control
641
 
                if (data & 1)
 
688
                if (data & MMUCR_AT)
642
689
                {
643
690
                        printf("SH4 MMU Enabled\n");
644
691
                        printf("If you're seeing this, but running something other than a Naomi GD-ROM game then chances are it won't work\n");
728
775
                }
729
776
                break;
730
777
 
731
 
                // TMU
732
 
        case TSTR:
733
 
                if (old & 1)
734
 
                        sh4->m[TCNT0] = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->m[TCR0] & 7]);
735
 
                if ((sh4->m[TSTR] & 1) == 0) {
736
 
                        sh4->timer[0]->adjust(attotime::never);
737
 
                } else
738
 
                        sh4_timer_recompute(sh4, 0);
739
 
 
740
 
                if (old & 2)
741
 
                        sh4->m[TCNT1] = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->m[TCR1] & 7]);
742
 
                if ((sh4->m[TSTR] & 2) == 0) {
743
 
                        sh4->timer[1]->adjust(attotime::never);
744
 
                } else
745
 
                        sh4_timer_recompute(sh4, 1);
746
 
 
747
 
                if (old & 4)
748
 
                        sh4->m[TCNT2] = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->m[TCR2] & 7]);
749
 
                if ((sh4->m[TSTR] & 4) == 0) {
750
 
                        sh4->timer[2]->adjust(attotime::never);
751
 
                } else
752
 
                        sh4_timer_recompute(sh4, 2);
753
 
                break;
754
 
 
755
 
        case TCR0:
756
 
                if (sh4->m[TSTR] & 1)
757
 
                {
758
 
                        sh4->m[TCNT0] = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[old & 7]);
759
 
                        sh4_timer_recompute(sh4, 0);
760
 
                }
761
 
                if (!(sh4->m[TCR0] & 0x20) || !(sh4->m[TCR0] & 0x100))
762
 
                        sh4_exception_unrequest(sh4, SH4_INTC_TUNI0);
763
 
                break;
764
 
        case TCR1:
765
 
                if (sh4->m[TSTR] & 2)
766
 
                {
767
 
                        sh4->m[TCNT1] = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[old & 7]);
768
 
                        sh4_timer_recompute(sh4, 1);
769
 
                }
770
 
                if (!(sh4->m[TCR1] & 0x20) || !(sh4->m[TCR1] & 0x100))
771
 
                        sh4_exception_unrequest(sh4, SH4_INTC_TUNI1);
772
 
                break;
773
 
        case TCR2:
774
 
                if (sh4->m[TSTR] & 4)
775
 
                {
776
 
                        sh4->m[TCNT2] = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[old & 7]);
777
 
                        sh4_timer_recompute(sh4, 2);
778
 
                }
779
 
                if (!(sh4->m[TCR2] & 0x20) || !(sh4->m[TCR2] & 0x100))
780
 
                        sh4_exception_unrequest(sh4, SH4_INTC_TUNI2);
781
 
                break;
782
 
 
783
 
        case TCOR0:
784
 
                if (sh4->m[TSTR] & 1)
785
 
                {
786
 
                        sh4->m[TCNT0] = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->m[TCR0] & 7]);
787
 
                        sh4_timer_recompute(sh4, 0);
788
 
                }
789
 
                break;
790
 
        case TCNT0:
791
 
                if (sh4->m[TSTR] & 1)
792
 
                        sh4_timer_recompute(sh4, 0);
793
 
                break;
794
 
        case TCOR1:
795
 
                if (sh4->m[TSTR] & 2)
796
 
                {
797
 
                        sh4->m[TCNT1] = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->m[TCR1] & 7]);
798
 
                        sh4_timer_recompute(sh4, 1);
799
 
                }
800
 
                break;
801
 
        case TCNT1:
802
 
                if (sh4->m[TSTR] & 2)
803
 
                        sh4_timer_recompute(sh4, 1);
804
 
                break;
805
 
        case TCOR2:
806
 
                if (sh4->m[TSTR] & 4)
807
 
                {
808
 
                        sh4->m[TCNT2] = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->m[TCR2] & 7]);
809
 
                        sh4_timer_recompute(sh4, 2);
810
 
                }
811
 
                break;
812
 
        case TCNT2:
813
 
                if (sh4->m[TSTR] & 4)
814
 
                        sh4_timer_recompute(sh4, 2);
815
 
                break;
816
 
 
817
 
                // INTC
 
778
/*********************************************************************************************************************
 
779
        TMU (Timer Unit)
 
780
*********************************************************************************************************************/
 
781
        case SH4_TSTR_ADDR:     sh4_handle_tstr_addr_w(sh4,data,mem_mask);   break;
 
782
        case SH4_TCR0_ADDR:     sh4_handle_tcr0_addr_w(sh4,data,mem_mask);   break;
 
783
        case SH4_TCR1_ADDR: sh4_handle_tcr1_addr_w(sh4,data,mem_mask);   break;
 
784
        case SH4_TCR2_ADDR: sh4_handle_tcr2_addr_w(sh4,data,mem_mask);   break;
 
785
        case SH4_TCOR0_ADDR: sh4_handle_tcor0_addr_w(sh4,data,mem_mask); break;
 
786
        case SH4_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(sh4,data,mem_mask); break;
 
787
        case SH4_TCOR1_ADDR: sh4_handle_tcor1_addr_w(sh4,data,mem_mask); break;
 
788
        case SH4_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(sh4,data,mem_mask); break;
 
789
        case SH4_TCOR2_ADDR: sh4_handle_tcor2_addr_w(sh4,data,mem_mask); break;
 
790
        case SH4_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(sh4,data,mem_mask); break;
 
791
        case SH4_TOCR_ADDR: sh4_handle_tocr_addr_w(sh4,data,mem_mask);   break; // not supported
 
792
        case SH4_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(sh4,data,mem_mask); break; // not supported
 
793
/*********************************************************************************************************************
 
794
        INTC (Interrupt Controller)
 
795
*********************************************************************************************************************/
818
796
        case ICR:
819
797
                sh4->m[ICR] = (sh4->m[ICR] & 0x7fff) | (old & 0x8000);
820
798
                break;
821
 
        case IPRA:
822
 
                sh4->exception_priority[SH4_INTC_ATI] = INTPRI(sh4->m[IPRA] & 0x000f, SH4_INTC_ATI);
823
 
                sh4->exception_priority[SH4_INTC_PRI] = INTPRI(sh4->m[IPRA] & 0x000f, SH4_INTC_PRI);
824
 
                sh4->exception_priority[SH4_INTC_CUI] = INTPRI(sh4->m[IPRA] & 0x000f, SH4_INTC_CUI);
825
 
                sh4->exception_priority[SH4_INTC_TUNI2] = INTPRI((sh4->m[IPRA] & 0x00f0) >> 4, SH4_INTC_TUNI2);
826
 
                sh4->exception_priority[SH4_INTC_TICPI2] = INTPRI((sh4->m[IPRA] & 0x00f0) >> 4, SH4_INTC_TICPI2);
827
 
                sh4->exception_priority[SH4_INTC_TUNI1] = INTPRI((sh4->m[IPRA] & 0x0f00) >> 8, SH4_INTC_TUNI1);
828
 
                sh4->exception_priority[SH4_INTC_TUNI0] = INTPRI((sh4->m[IPRA] & 0xf000) >> 12, SH4_INTC_TUNI0);
829
 
                sh4_exception_recompute(sh4);
830
 
                break;
 
799
        case IPRA: sh4_handler_ipra_w(sh4, data, mem_mask); break;
831
800
        case IPRB:
832
801
                sh4->exception_priority[SH4_INTC_SCI1ERI] = INTPRI((sh4->m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1ERI);
833
802
                sh4->exception_priority[SH4_INTC_SCI1RXI] = INTPRI((sh4->m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1RXI);
852
821
                sh4->exception_priority[SH4_INTC_GPOI] = INTPRI((sh4->m[IPRC] & 0xf000) >> 12, SH4_INTC_GPOI);
853
822
                sh4_exception_recompute(sh4);
854
823
                break;
855
 
 
856
 
                // DMA
857
 
        case SAR0:
858
 
        case SAR1:
859
 
        case SAR2:
860
 
        case SAR3:
861
 
        case DAR0:
862
 
        case DAR1:
863
 
        case DAR2:
864
 
        case DAR3:
865
 
        case DMATCR0:
866
 
        case DMATCR1:
867
 
        case DMATCR2:
868
 
        case DMATCR3:
869
 
                break;
870
 
        case CHCR0:
871
 
                sh4_dmac_check(sh4, 0);
872
 
                break;
873
 
        case CHCR1:
874
 
                sh4_dmac_check(sh4, 1);
875
 
                break;
876
 
        case CHCR2:
877
 
                sh4_dmac_check(sh4, 2);
878
 
                break;
879
 
        case CHCR3:
880
 
                sh4_dmac_check(sh4, 3);
881
 
                break;
882
 
        case DMAOR:
883
 
                if ((sh4->m[DMAOR] & 4) && (~old & 4))
884
 
                        sh4->m[DMAOR] &= ~4;
885
 
                if ((sh4->m[DMAOR] & 2) && (~old & 2))
886
 
                        sh4->m[DMAOR] &= ~2;
887
 
                sh4_dmac_check(sh4, 0);
888
 
                sh4_dmac_check(sh4, 1);
889
 
                sh4_dmac_check(sh4, 2);
890
 
                sh4_dmac_check(sh4, 3);
891
 
                break;
892
 
 
893
 
                // Store Queues
 
824
/*********************************************************************************************************************
 
825
        DMAC (DMA Controller)
 
826
*********************************************************************************************************************/
 
827
        case SH4_SAR0_ADDR: sh4_handle_sar0_addr_w(sh4,data,mem_mask);   break;
 
828
        case SH4_SAR1_ADDR: sh4_handle_sar1_addr_w(sh4,data,mem_mask);   break;
 
829
        case SH4_SAR2_ADDR: sh4_handle_sar2_addr_w(sh4,data,mem_mask);   break;
 
830
        case SH4_SAR3_ADDR: sh4_handle_sar3_addr_w(sh4,data,mem_mask);   break;
 
831
        case SH4_DAR0_ADDR: sh4_handle_dar0_addr_w(sh4,data,mem_mask);   break;
 
832
        case SH4_DAR1_ADDR: sh4_handle_dar1_addr_w(sh4,data,mem_mask);   break;
 
833
        case SH4_DAR2_ADDR: sh4_handle_dar2_addr_w(sh4,data,mem_mask);   break;
 
834
        case SH4_DAR3_ADDR: sh4_handle_dar3_addr_w(sh4,data,mem_mask);   break;
 
835
        case SH4_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(sh4,data,mem_mask);   break;
 
836
        case SH4_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(sh4,data,mem_mask);   break;
 
837
        case SH4_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(sh4,data,mem_mask);   break;
 
838
        case SH4_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(sh4,data,mem_mask);   break;
 
839
        case SH4_CHCR0_ADDR: sh4_handle_chcr0_addr_w(sh4,data,mem_mask);   break;
 
840
        case SH4_CHCR1_ADDR: sh4_handle_chcr1_addr_w(sh4,data,mem_mask);   break;
 
841
        case SH4_CHCR2_ADDR: sh4_handle_chcr2_addr_w(sh4,data,mem_mask);   break;
 
842
        case SH4_CHCR3_ADDR: sh4_handle_chcr3_addr_w(sh4,data,mem_mask);   break;
 
843
        case SH4_DMAOR_ADDR: sh4_handle_dmaor_addr_w(sh4,data,mem_mask);   break;
 
844
/*********************************************************************************************************************
 
845
        Store Queues
 
846
*********************************************************************************************************************/
894
847
        case QACR0:
895
848
        case QACR1:
896
849
                break;
897
 
 
898
 
                // I/O ports
 
850
/*********************************************************************************************************************
 
851
        I/O
 
852
*********************************************************************************************************************/
899
853
        case PCTRA:
900
854
                sh4->ioport16_pullup = 0;
901
855
                sh4->ioport16_direction = 0;
932
886
        case SCBRR2:
933
887
                break;
934
888
 
 
889
        case SCSPTR2: //trips often in aristocrat mk-6
 
890
                break;
 
891
 
935
892
        default:
936
893
                logerror("sh4_internal_w:  Unmapped write %08x, %08x @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), data, mem_mask);
937
894
                break;
942
899
{
943
900
        sh4_state *sh4 = get_safe_token(&space->device());
944
901
 
 
902
        if (sh4->cpu_type != CPU_TYPE_SH4)
 
903
                fatalerror("sh4_internal_r uses sh4->m[] with SH3\n");
 
904
 
945
905
        UINT32 addr = (offset << 2) + 0xfe000000;
946
906
        offset = ((addr & 0xfc) >> 2) | ((addr & 0x1fe0000) >> 11);
947
907
 
950
910
        switch( offset )
951
911
        {
952
912
        case VERSION:
953
 
                return 0x040205c1;      // this is what a real SH7750 in a Dreamcast returns - the later Naomi BIOSes check and care!
 
913
                return PVR_SH7091;      // 0x040205c1, this is what a real SH7091 in a Dreamcast returns - the later Naomi BIOSes check and care!
 
914
                break;
 
915
        case PRR:
 
916
                return 0;
954
917
                break;
955
918
        case IPRD:
956
919
                return 0x00000000;      // SH7750 ignores writes here and always returns zero
966
929
                        return sh4->m[RTCNT];
967
930
                break;
968
931
 
969
 
        case TCNT0:
970
 
                if (sh4->m[TSTR] & 1)
971
 
                        return compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->m[TCR0] & 7]);
972
 
                else
973
 
                        return sh4->m[TCNT0];
974
 
                break;
975
 
        case TCNT1:
976
 
                if (sh4->m[TSTR] & 2)
977
 
                        return compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->m[TCR1] & 7]);
978
 
                else
979
 
                        return sh4->m[TCNT1];
980
 
                break;
981
 
        case TCNT2:
982
 
                if (sh4->m[TSTR] & 4)
983
 
                        return compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->m[TCR2] & 7]);
984
 
                else
985
 
                        return sh4->m[TCNT2];
986
 
                break;
987
 
 
988
 
                // I/O ports
 
932
/*********************************************************************************************************************
 
933
        INTC (Interrupt Controller)
 
934
*********************************************************************************************************************/
 
935
 
 
936
        case IPRA:
 
937
                return sh4->SH4_IPRA;
 
938
 
 
939
/*********************************************************************************************************************
 
940
        TMU (Timer Unit)
 
941
*********************************************************************************************************************/
 
942
        case SH4_TSTR_ADDR:  return sh4_handle_tstr_addr_r(sh4, mem_mask);
 
943
        case SH4_TCR0_ADDR:  return sh4_handle_tcr0_addr_r(sh4, mem_mask);
 
944
        case SH4_TCR1_ADDR:  return sh4_handle_tcr1_addr_r(sh4, mem_mask);
 
945
        case SH4_TCR2_ADDR:  return sh4_handle_tcr2_addr_r(sh4, mem_mask);
 
946
        case SH4_TCNT0_ADDR: return sh4_handle_tcnt0_addr_r(sh4, mem_mask);
 
947
        case SH4_TCNT1_ADDR: return sh4_handle_tcnt1_addr_r(sh4, mem_mask);
 
948
        case SH4_TCNT2_ADDR: return sh4_handle_tcnt2_addr_r(sh4, mem_mask);
 
949
        case SH4_TCOR0_ADDR: return sh4_handle_tcor0_addr_r(sh4, mem_mask);
 
950
        case SH4_TCOR1_ADDR: return sh4_handle_tcor1_addr_r(sh4, mem_mask);
 
951
        case SH4_TCOR2_ADDR: return sh4_handle_tcor2_addr_r(sh4, mem_mask);
 
952
        case SH4_TOCR_ADDR:  return sh4_handle_tocr_addr_r(sh4, mem_mask); // not supported
 
953
        case SH4_TCPR2_ADDR: return sh4_handle_tcpr2_addr_r(sh4, mem_mask); // not supported
 
954
/*********************************************************************************************************************
 
955
        DMAC (DMA Controller)
 
956
*********************************************************************************************************************/
 
957
        case SH4_SAR0_ADDR: return sh4_handle_sar0_addr_r(sh4,mem_mask);
 
958
        case SH4_SAR1_ADDR: return sh4_handle_sar1_addr_r(sh4,mem_mask);
 
959
        case SH4_SAR2_ADDR: return sh4_handle_sar2_addr_r(sh4,mem_mask);
 
960
        case SH4_SAR3_ADDR: return sh4_handle_sar3_addr_r(sh4,mem_mask);
 
961
        case SH4_DAR0_ADDR: return sh4_handle_dar0_addr_r(sh4,mem_mask);
 
962
        case SH4_DAR1_ADDR: return sh4_handle_dar1_addr_r(sh4,mem_mask);
 
963
        case SH4_DAR2_ADDR: return sh4_handle_dar2_addr_r(sh4,mem_mask);
 
964
        case SH4_DAR3_ADDR: return sh4_handle_dar3_addr_r(sh4,mem_mask);
 
965
        case SH4_DMATCR0_ADDR: return sh4_handle_dmatcr0_addr_r(sh4,mem_mask);
 
966
        case SH4_DMATCR1_ADDR: return sh4_handle_dmatcr1_addr_r(sh4,mem_mask);
 
967
        case SH4_DMATCR2_ADDR: return sh4_handle_dmatcr2_addr_r(sh4,mem_mask);
 
968
        case SH4_DMATCR3_ADDR: return sh4_handle_dmatcr3_addr_r(sh4,mem_mask);
 
969
        case SH4_CHCR0_ADDR: return sh4_handle_chcr0_addr_r(sh4,mem_mask);
 
970
        case SH4_CHCR1_ADDR: return sh4_handle_chcr1_addr_r(sh4,mem_mask);
 
971
        case SH4_CHCR2_ADDR: return sh4_handle_chcr2_addr_r(sh4,mem_mask);
 
972
        case SH4_CHCR3_ADDR: return sh4_handle_chcr3_addr_r(sh4,mem_mask);
 
973
        case SH4_DMAOR_ADDR: return sh4_handle_dmaor_addr_r(sh4,mem_mask);
 
974
/*********************************************************************************************************************
 
975
        I/O Ports
 
976
*********************************************************************************************************************/
 
977
 
989
978
        case PDTRA:
990
979
                if (sh4->m[BCR2] & 1)
991
980
                        return (sh4->io->read_dword(SH4_IOPORT_16) & ~sh4->ioport16_direction) | (sh4->m[PDTRA] & sh4->ioport16_direction);
1006
995
{
1007
996
        sh4_state *sh4 = get_safe_token(device);
1008
997
 
 
998
        if (sh4->cpu_type != CPU_TYPE_SH4)
 
999
                fatalerror("sh4_set_frt_input uses sh4->m[] with SH3\n");
 
1000
 
1009
1001
        if(state == PULSE_LINE)
1010
1002
        {
1011
1003
                sh4_set_frt_input(device, ASSERT_LINE);
1019
1011
 
1020
1012
        sh4->frt_input = state;
1021
1013
 
1022
 
        if(sh4->m[5] & 0x8000) {
1023
 
                if(state == CLEAR_LINE) {
1024
 
                        return;
1025
 
                }
1026
 
        } else {
1027
 
                if(state == ASSERT_LINE) {
1028
 
                        return;
1029
 
                }
 
1014
        if (sh4->cpu_type == CPU_TYPE_SH4)
 
1015
        {
 
1016
 
 
1017
                if(sh4->m[5] & 0x8000) {
 
1018
                        if(state == CLEAR_LINE) {
 
1019
                                return;
 
1020
                        }
 
1021
                } else {
 
1022
                        if(state == ASSERT_LINE) {
 
1023
                                return;
 
1024
                        }
 
1025
                }
 
1026
        }
 
1027
        else
 
1028
        {
 
1029
                fatalerror("sh4_set_frt_input uses sh4->m[] with SH3\n");
1030
1030
        }
1031
1031
 
1032
1032
#if 0
1051
1051
 
1052
1052
void sh4_set_irq_line(sh4_state *sh4, int irqline, int state) // set state of external interrupt line
1053
1053
{
1054
 
        int s;
 
1054
        if (sh4->cpu_type == CPU_TYPE_SH3)
 
1055
        {
 
1056
                /***** ASSUME THIS TO BE WRONG FOR NOW *****/
1055
1057
 
1056
 
        if (irqline == INPUT_LINE_NMI)
1057
 
    {
1058
 
                if (sh4->nmi_line_state == state)
1059
 
                        return;
1060
 
                if (sh4->m[ICR] & 0x100)
1061
 
                {
1062
 
                        if ((state == CLEAR_LINE) && (sh4->nmi_line_state == ASSERT_LINE))  // rising
1063
 
                        {
1064
 
                                LOG(("SH-4 '%s' assert nmi\n", sh4->device->tag()));
1065
 
                                sh4_exception_request(sh4, SH4_INTC_NMI);
1066
 
                                sh4_dmac_nmi(sh4);
1067
 
                        }
1068
 
                }
1069
 
                else
1070
 
                {
1071
 
                        if ((state == ASSERT_LINE) && (sh4->nmi_line_state == CLEAR_LINE)) // falling
1072
 
                        {
1073
 
                                LOG(("SH-4 '%s' assert nmi\n", sh4->device->tag()));
1074
 
                                sh4_exception_request(sh4, SH4_INTC_NMI);
1075
 
                                sh4_dmac_nmi(sh4);
1076
 
                        }
1077
 
                }
1078
 
                if (state == CLEAR_LINE)
1079
 
                        sh4->m[ICR] ^= 0x8000;
1080
 
                else
1081
 
                        sh4->m[ICR] |= 0x8000;
1082
 
                sh4->nmi_line_state = state;
1083
 
        }
1084
 
        else
1085
 
        {
1086
 
                if (sh4->m[ICR] & 0x80) // four independent external interrupt sources
1087
 
                {
1088
 
                        if (irqline > SH4_IRL3)
1089
 
                                return;
 
1058
                if (irqline == INPUT_LINE_NMI)
 
1059
                {
 
1060
                        fatalerror("SH3 NMI Unimplemented\n");
 
1061
                }
 
1062
                else
 
1063
                {
 
1064
                        //if (irqline > SH4_IRL3)
 
1065
                        //  return;
1090
1066
                        if (sh4->irq_line_state[irqline] == state)
1091
1067
                                return;
1092
1068
                        sh4->irq_line_state[irqline] = state;
1101
1077
                                LOG(("SH-4 '%s' assert external irq IRL%d\n", sh4->device->tag(), irqline));
1102
1078
                                sh4_exception_request(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0);
1103
1079
                        }
1104
 
                }
1105
 
                else // level-encoded interrupt
1106
 
                {
1107
 
                        if (irqline != SH4_IRLn)
1108
 
                                return;
1109
 
                        if ((sh4->irln > 15) || (sh4->irln < 0))
1110
 
                                return;
1111
 
                        for (s = 0; s < 15; s++)
1112
 
                                sh4_exception_unrequest(sh4, SH4_INTC_IRLn0+s);
1113
 
                        if (sh4->irln < 15)
1114
 
                                sh4_exception_request(sh4, SH4_INTC_IRLn0+sh4->irln);
1115
 
                        LOG(("SH-4 '%s' IRLn0-IRLn3 level #%d\n", sh4->device->tag(), sh4->irln));
1116
 
                }
1117
 
        }
1118
 
        if (sh4->test_irq && (!sh4->delay))
1119
 
                sh4_check_pending_irq(sh4, "sh4_set_irq_line");
 
1080
 
 
1081
                }
 
1082
 
 
1083
                /***** END ASSUME THIS TO BE WRONG FOR NOW *****/
 
1084
        }
 
1085
        else
 
1086
        {
 
1087
                int s;
 
1088
 
 
1089
                if (irqline == INPUT_LINE_NMI)
 
1090
                {
 
1091
                        if (sh4->nmi_line_state == state)
 
1092
                                return;
 
1093
                        if (sh4->m[ICR] & 0x100)
 
1094
                        {
 
1095
                                if ((state == CLEAR_LINE) && (sh4->nmi_line_state == ASSERT_LINE))  // rising
 
1096
                                {
 
1097
                                        LOG(("SH-4 '%s' assert nmi\n", sh4->device->tag()));
 
1098
                                        sh4_exception_request(sh4, SH4_INTC_NMI);
 
1099
                                        sh4_dmac_nmi(sh4);
 
1100
                                }
 
1101
                        }
 
1102
                        else
 
1103
                        {
 
1104
                                if ((state == ASSERT_LINE) && (sh4->nmi_line_state == CLEAR_LINE)) // falling
 
1105
                                {
 
1106
                                        LOG(("SH-4 '%s' assert nmi\n", sh4->device->tag()));
 
1107
                                        sh4_exception_request(sh4, SH4_INTC_NMI);
 
1108
                                        sh4_dmac_nmi(sh4);
 
1109
                                }
 
1110
                        }
 
1111
                        if (state == CLEAR_LINE)
 
1112
                                sh4->m[ICR] ^= 0x8000;
 
1113
                        else
 
1114
                                sh4->m[ICR] |= 0x8000;
 
1115
                        sh4->nmi_line_state = state;
 
1116
                }
 
1117
                else
 
1118
                {
 
1119
                        if (sh4->m[ICR] & 0x80) // four independent external interrupt sources
 
1120
                        {
 
1121
                                if (irqline > SH4_IRL3)
 
1122
                                        return;
 
1123
                                if (sh4->irq_line_state[irqline] == state)
 
1124
                                        return;
 
1125
                                sh4->irq_line_state[irqline] = state;
 
1126
 
 
1127
                                if( state == CLEAR_LINE )
 
1128
                                {
 
1129
                                        LOG(("SH-4 '%s' cleared external irq IRL%d\n", sh4->device->tag(), irqline));
 
1130
                                        sh4_exception_unrequest(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0);
 
1131
                                }
 
1132
                                else
 
1133
                                {
 
1134
                                        LOG(("SH-4 '%s' assert external irq IRL%d\n", sh4->device->tag(), irqline));
 
1135
                                        sh4_exception_request(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0);
 
1136
                                }
 
1137
                        }
 
1138
                        else // level-encoded interrupt
 
1139
                        {
 
1140
                                if (irqline != SH4_IRLn)
 
1141
                                        return;
 
1142
                                if ((sh4->irln > 15) || (sh4->irln < 0))
 
1143
                                        return;
 
1144
                                for (s = 0; s < 15; s++)
 
1145
                                        sh4_exception_unrequest(sh4, SH4_INTC_IRLn0+s);
 
1146
                                if (sh4->irln < 15)
 
1147
                                        sh4_exception_request(sh4, SH4_INTC_IRLn0+sh4->irln);
 
1148
                                LOG(("SH-4 '%s' IRLn0-IRLn3 level #%d\n", sh4->device->tag(), sh4->irln));
 
1149
                        }
 
1150
                }
 
1151
                if (sh4->test_irq && (!sh4->delay))
 
1152
                        sh4_check_pending_irq(sh4, "sh4_set_irq_line");
 
1153
        }
1120
1154
}
1121
1155
 
1122
1156
void sh4_parse_configuration(sh4_state *sh4, const struct sh4_config *conf)
1194
1228
        sh4->m = auto_alloc_array(device->machine(), UINT32, 16384);
1195
1229
}
1196
1230
 
1197
 
void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s)
1198
 
{
1199
 
        sh4_state *sh4 = get_safe_token(device);
1200
 
        UINT32 chcr;
1201
 
        UINT32 *p32bits;
1202
 
        UINT64 *p32bytes;
1203
 
        UINT32 pos,len,siz;
1204
 
 
1205
 
        if (sh4->dma_timer_active[s->channel])
1206
 
                return;
1207
 
        if (s->mode >= 0) {
1208
 
                switch (s->channel)
1209
 
                {
1210
 
                case 0:
1211
 
                        if (s->mode & 1)
1212
 
                                s->source = sh4->m[SAR0];
1213
 
                        if (s->mode & 2)
1214
 
                                sh4->m[SAR0] = s->source;
1215
 
                        if (s->mode & 4)
1216
 
                                s->destination = sh4->m[DAR0];
1217
 
                        if (s->mode & 8)
1218
 
                                sh4->m[DAR0] = s->destination;
1219
 
                        break;
1220
 
                case 1:
1221
 
                        if (s->mode & 1)
1222
 
                                s->source = sh4->m[SAR1];
1223
 
                        if (s->mode & 2)
1224
 
                                sh4->m[SAR1] = s->source;
1225
 
                        if (s->mode & 4)
1226
 
                                s->destination = sh4->m[DAR1];
1227
 
                        if (s->mode & 8)
1228
 
                                sh4->m[DAR1] = s->destination;
1229
 
                        break;
1230
 
                case 2:
1231
 
                        if (s->mode & 1)
1232
 
                                s->source = sh4->m[SAR2];
1233
 
                        if (s->mode & 2)
1234
 
                                sh4->m[SAR2] = s->source;
1235
 
                        if (s->mode & 4)
1236
 
                                s->destination = sh4->m[DAR2];
1237
 
                        if (s->mode & 8)
1238
 
                                sh4->m[DAR2] = s->destination;
1239
 
                        break;
1240
 
                case 3:
1241
 
                default:
1242
 
                        if (s->mode & 1)
1243
 
                                s->source = sh4->m[SAR3];
1244
 
                        if (s->mode & 2)
1245
 
                                sh4->m[SAR3] = s->source;
1246
 
                        if (s->mode & 4)
1247
 
                                s->destination = sh4->m[DAR3];
1248
 
                        if (s->mode & 8)
1249
 
                                sh4->m[DAR3] = s->destination;
1250
 
                        break;
1251
 
                }
1252
 
                switch (s->channel)
1253
 
                {
1254
 
                case 0:
1255
 
                        chcr = sh4->m[CHCR0];
1256
 
                        len = sh4->m[DMATCR0];
1257
 
                        break;
1258
 
                case 1:
1259
 
                        chcr = sh4->m[CHCR1];
1260
 
                        len = sh4->m[DMATCR1];
1261
 
                        break;
1262
 
                case 2:
1263
 
                        chcr = sh4->m[CHCR2];
1264
 
                        len = sh4->m[DMATCR2];
1265
 
                        break;
1266
 
                case 3:
1267
 
                default:
1268
 
                        chcr = sh4->m[CHCR3];
1269
 
                        len = sh4->m[DMATCR3];
1270
 
                        break;
1271
 
                }
1272
 
                if ((s->direction) == 0) {
1273
 
                        chcr = (chcr & 0xffff3fff) | ((s->mode & 0x30) << 10);
1274
 
                } else {
1275
 
                        chcr = (chcr & 0xffffcfff) | ((s->mode & 0x30) << 8);
1276
 
                }
1277
 
                siz = dmasize[(chcr >> 4) & 7];
1278
 
                if (siz && (s->size))
1279
 
                        if ((len * siz) != (s->length * s->size))
1280
 
                                return;
1281
 
                sh4_dma_transfer(sh4, s->channel, 0, chcr, &s->source, &s->destination, &len);
1282
 
        } else {
1283
 
                if (s->size == 4) {
1284
 
                        if ((s->direction) == 0) {
1285
 
                                len = s->length;
1286
 
                                p32bits = (UINT32 *)(s->buffer);
1287
 
                                for (pos = 0;pos < len;pos++) {
1288
 
                                        *p32bits = sh4->program->read_dword(s->source);
1289
 
                                        p32bits++;
1290
 
                                        s->source = s->source + 4;
1291
 
                                }
1292
 
                        } else {
1293
 
                                len = s->length;
1294
 
                                p32bits = (UINT32 *)(s->buffer);
1295
 
                                for (pos = 0;pos < len;pos++) {
1296
 
                                        sh4->program->write_dword(s->destination, *p32bits);
1297
 
                                        p32bits++;
1298
 
                                        s->destination = s->destination + 4;
1299
 
                                }
1300
 
                        }
1301
 
                }
1302
 
                if (s->size == 32) {
1303
 
                        if ((s->direction) == 0) {
1304
 
                                len = s->length * 4;
1305
 
                                p32bytes = (UINT64 *)(s->buffer);
1306
 
                                for (pos = 0;pos < len;pos++) {
1307
 
                                        *p32bytes = sh4->program->read_qword(s->source);
1308
 
                                        p32bytes++;
1309
 
                                        s->destination = s->destination + 8;
1310
 
                                }
1311
 
                        } else {
1312
 
                                len = s->length * 4;
1313
 
                                p32bytes = (UINT64 *)(s->buffer);
1314
 
                                for (pos = 0;pos < len;pos++) {
1315
 
                                        sh4->program->write_qword(s->destination, *p32bytes);
1316
 
                                        p32bytes++;
1317
 
                                        s->destination = s->destination + 8;
1318
 
                                }
1319
 
                        }
1320
 
                }
1321
 
        }
1322
 
}
1323
 
 
1324
1231
UINT32 sh4_getsqremap(sh4_state *sh4, UINT32 address)
1325
1232
{
1326
1233
        if (!sh4->sh4_mmu_enabled)