1
/***************************************************************************
3
Atari Missile Command hardware
11
******************************************************************************************
22
|---------------------------------------------------------------------|
24
| MC14584 MC14584 10MHz RESET_SW |
25
|J19 T_HSYNC T_R/W02 UM6502A |
29
| T_START2 MM5290J-3 X |
30
|-|J20 T_START1 T_GND T_GND MM5290J-3 035820-01.H1 |
31
|2 T_SLAM MM5290J-3 035821-01.JK1|
32
|2 T_COINR T_COINC MM5290J-3 035822-01.KL1|
33
|W T_TEST T_COINL T_GND |
34
|A T_AUD2 N82S25 MM5290J-3 035823-01.MN1|
35
|Y T_AUD1 035826-01.L6 MM5290J-3 X |
36
|-| LM324 T_VSYNC MM5290J-3 T_+12V |
37
| C012294B-01 MM5290J-3 035824-01.NP1|
38
|-|T_+5V DSW(8) DSW(8) X 035825-01.R1 |
39
|---------------------------------------------------------------------|
41
UM6502A - 6502 CPU, clock input is on pin 37. This is a little strange because it
42
measures 1.17240MHz. It was assumed to be 1.25MHz [10/8]. This might be
43
caused by old components that are out of spec now, but the PCB does run
44
flawlessly, and the other clocks measure correctly so I'm not sure what's going on.
45
C012294B-01 - 'Pokey' sound chip, clock 1.25MHz on pin 7 [10/8]
46
035826-01 - MMI 6331 bipolar PROM
47
MM5290J-3 - National Semiconductor MM5290J-3 16kx1 DRAM (=TMM416, uPD416, MK4116, TMS4116 etc)
48
MC14584 - Hex Schmitt Trigger
49
82S25 - Signetics 64-bit (16x4) bipolar scratch pad memory (=3101, 74S189, 7489, 9410 etc)
50
LM324 - Low Power Quad Operational Amplifier
51
J20 - 22-Way edge connector (for upright)
52
J19 - 12-Way edge connector (additional controls for cocktail)
54
X - Empty location for DIP24 device (no socket)
59
Edge Connector J20 Pinout
60
-------------------------
65
Audio 1 Out E | 5 Audio 2 Out
67
Start2 LED H | 7 Left Fire
68
Center Fire J | 8 Right Fire
69
Right Coin K | 9 Left Coin
70
Video Blue L | 10 Video Red
71
Video Green M | 11 Left Coin Counter
72
Center Coin Counter N | 12 Right Coin Counter
73
Start 1 LED P | 13 Start Button 1
74
Test Switch R | 14 Slam Switch
75
Center Coin Slot* S | 15 Start Button 2
76
Vert. Trackball Dir. T | 16 Vert. Trackball Clock
77
Horiz. Trackball Clk U | 17 Horiz. Trackball Dir.
85
Edge Connector J19 Pinout (Only used in cocktail version)
86
-------------------------
90
Right Fire Button 2 D | 4
91
Center Fire Button 2 E | 5 Left Fire Button 2
95
Horiz. Trkball Dir. 2 K | 9 Vert. Trackball Dir. 2
96
Horiz. Trkball Clock 2 L | 10 Vert. Trackball Clock 2
100
****************************************************************************
102
Horizontal sync chain:
104
A J/K flip flop @ D6 counts the 1H line, and cascades into a
105
4-bit binary counter @ D5, which counts the 2H,4H,8H,16H lines.
106
This counter cascades into a 4-bit BCD decade counter @ E5
107
which counts the 32H,64H,128H,HBLANK lines. The counter system
108
rolls over after counting to 320.
112
HBLANK begins at H = 256
113
HSYNC begins at H = 260
114
HSYNC ends at H = 288
119
The HSYNC signal clocks a 4-bit binary counter @ A4, which counts
120
the 1V,2V,4V,8V lines. This counter cascades into a second 4-bit
121
binary counter @ B4 which counts the 16V,32V,64V,128V lines. The
122
counter system rolls over after counting to 256.
124
if not flipped (V counts up):
125
VBLANK ends at V = 24
126
VBLANK begins at V = 0
127
VSYNC begins at V = 4
131
if flipped (V counts down):
133
VBLANK begins at V = 24
134
VSYNC begins at V = 20
140
/IRQ connected to Q on flip-flop @ F7, clocked by SYNC which
141
indicates an instruction opcode fetch. Input to the flip-flop
142
(D) comes from a second flip-flop @ F7, which is clocked by
143
/16V or 16V depending on whether or not we are flipped. Input
144
to this second flip-flop is 32V.
146
if not flipped (V counts up):
147
clock @ 0 -> 32V = 0 -> /IRQ = 0
148
clock @ 32 -> 32V = 1 -> /IRQ = 1
149
clock @ 64 -> 32V = 0 -> /IRQ = 0
150
clock @ 96 -> 32V = 1 -> /IRQ = 1
151
clock @ 128 -> 32V = 0 -> /IRQ = 0
152
clock @ 160 -> 32V = 1 -> /IRQ = 1
153
clock @ 192 -> 32V = 0 -> /IRQ = 0
154
clock @ 224 -> 32V = 1 -> /IRQ = 1
156
if flipped (V counts down):
157
clock @ 208 -> 32V = 0 -> /IRQ = 0
158
clock @ 176 -> 32V = 1 -> /IRQ = 1
159
clock @ 144 -> 32V = 0 -> /IRQ = 0
160
clock @ 112 -> 32V = 1 -> /IRQ = 1
161
clock @ 80 -> 32V = 0 -> /IRQ = 0
162
clock @ 48 -> 32V = 1 -> /IRQ = 1
163
clock @ 16 -> 32V = 0 -> /IRQ = 0
164
clock @ 240 -> 32V = 1 -> /IRQ = 1
166
****************************************************************************
169
_ _ _ _ _ _ _ _ _ _ _ _ _ _
170
_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| | 1H
171
___ ___ ___ ___ ___ ___ ___
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___| |___| |___| |___| |___| |___| |___| | 2H
173
_______ _______ _______
174
_______| |_______| |_______| |_______| 4H
175
_______ ___________ ___________ ___________
176
|___| |___| |___| /(4H & /2H)
178
|_______| |___________| |___________| |_________ /Q on FF @ A7
180
___________| |___________| |___________| |_______ Q on FF @ B8
183
___ ___ ___ ___ ___ ___ ___
184
___| |___| |___| |___| |___| |___| |___| | Sigma-X = 2H
188
___________| |___________| |___________| |_______ Sigma-X = Q on FF @ B8
190
****************************************************************************
192
Modified from original schematics...
196
HEX R/W D7 D6 D5 D4 D3 D2 D2 D0 function
197
---------+-----+------------------------+------------------------
198
0000-01FF R/W D D D D D D D D 512 bytes working ram
200
0200-05FF R/W D D D D D D D D 3rd color bit region
202
Each bit of every odd byte is the low color
203
bit for the bottom scanlines
204
The schematics say that its for the bottom
205
32 scanlines, although the code only accesses
206
$401-$5FF for the bottom 8 scanlines...
209
0600-063F R/W D D D D D D D D More working ram.
211
0640-3FFF R/W D D D D D D D D 2-color bit region of
213
Writes to 4 bytes each to effectively
216
1900-FFFF R/W D D 2-color bit region of
221
Those instructions take longer
224
---------+-----+------------------------+------------------------
225
4000-400F R/W D D D D D D D D POKEY ports.
226
-----------------------------------------------------------------
227
4008 R D D D D D D D D Game Option switches
228
-----------------------------------------------------------------
232
4800 R D 1 player start
233
4800 R D 2 player start
234
4800 R D 2nd player left fire(cocktail)
235
4800 R D 2nd player center fire "
236
4800 R D 2nd player right fire "
237
---------+-----+------------------------+------------------------
238
4800 R D D D D Horiz trackball displacement
240
4800 R D D D D Vert trackball displacement
242
---------+-----+------------------------+------------------------
245
4800 W D left coin counter
246
4800 W D center coin counter
247
4800 W D right coin counter
248
4800 W D 2 player start LED.
249
4800 W D 1 player start LED.
250
4800 W D CTRLD, 0=read switches,
252
---------+-----+------------------------+------------------------
254
4900 R D Self test switch input.
255
4900 R D SLAM switch input.
256
4900 R D Horiz trackball direction input.
257
4900 R D Vert trackball direction input.
258
4900 R D 1st player left fire.
259
4900 R D 1st player center fire.
260
4900 R D 1st player right fire.
261
---------+-----+------------------------+------------------------
262
4A00 R D D D D D D D D Pricing Option switches.
263
4B00-4B07 W D D D D Color RAM.
265
4D00 W Interrupt acknowledge.
266
---------+-----+------------------------+------------------------
267
5000-7FFF R D D D D D D D D Program.
268
---------+-----+------------------------+------------------------
271
MISSILE COMMAND SWITCH SETTINGS (Atari, 1980)
272
---------------------------------------------
276
(8-position switch at R8)
278
1 2 3 4 5 6 7 8 Meaning
279
-------------------------------------------------------------------------
280
Off Off Game starts with 7 cities
281
On On Game starts with 6 cities
282
On Off Game starts with 5 cities
283
Off On Game starts with 4 cities
285
Off 1 bonus credit for 4 successive coins
286
On Large trak-ball input
287
Off Mini Trak-ball input
288
On Off Off Bonus city every 8000 pts
289
On On On Bonus city every 10000 pts
290
Off On On Bonus city every 12000 pts
291
On Off On Bonus city every 14000 pts
292
Off Off On Bonus city every 15000 pts
293
On On Off Bonus city every 18000 pts
294
Off On Off Bonus city every 20000 pts
295
Off Off Off No bonus cities
302
(8-position switch at R10)
304
1 2 3 4 5 6 7 8 Meaning
305
-------------------------------------------------------------------------
308
On Off 2 coins 1 play
309
Off Off 1 coin 2 plays
310
On On Right coin mech * 1
311
Off On Right coin mech * 4
312
On Off Right coin mech * 5
313
Off Off Right coin mech * 6
314
On Center coin mech * 1
315
Off Center coin mech * 2
323
-there are 2 different versions of the Super Missile Attack board. It's not known if
324
the roms are different. The SMA manual mentions a set 3(035822-03E) that will work
325
as well as set 2. Missile Command set 1 will not work with the SMA board. It would
326
appear set 1 and set 2 as labeled by mame are reversed.
328
****************************************************************************
330
Super Missile Attack Board Layout
332
|-------------------------------|
334
A | 2716 74LS138 2716 |
336
B | 2716 63S141 63S141 2716 |
344
|-------------------------------|
348
*****************************************************************************************/
351
#include "cpu/m6502/m6502.h"
352
#include "sound/pokey.h"
355
class missile_state : public driver_device
358
missile_state(const machine_config &mconfig, device_type type, const char *tag)
359
: driver_device(mconfig, type, tag) { }
362
const UINT8 *m_writeprom;
363
emu_timer *m_irq_timer;
364
emu_timer *m_cpu_timer;
368
UINT8 m_madsel_delay;
369
UINT16 m_madsel_lastpc;
374
#define MASTER_CLOCK XTAL_10MHz
376
#define PIXEL_CLOCK (MASTER_CLOCK/2)
378
#define HBSTART (256)
381
#define VBSTART (256)
382
#define VBEND (25) /* 24 causes a garbage line at the top of the screen */
385
/*************************************
389
*************************************/
396
/*************************************
398
* VBLANK and IRQ generation
400
*************************************/
402
INLINE int scanline_to_v(missile_state *state, int scanline)
404
/* since the vertical sync counter counts backwards when flipped,
405
this function returns the current effective V value, given
406
that vpos() only counts forward */
407
return state->m_flipscreen ? (256 - scanline) : scanline;
411
INLINE int v_to_scanline(missile_state *state, int v)
413
/* same as a above, but the opposite transformation */
414
return state->m_flipscreen ? (256 - v) : v;
418
INLINE void schedule_next_irq(running_machine &machine, int curv)
420
missile_state *state = machine.driver_data<missile_state>();
421
/* IRQ = /32V, clocked by /16V ^ flip */
422
/* When not flipped, clocks on 0, 64, 128, 192 */
423
/* When flipped, clocks on 16, 80, 144, 208 */
424
if (state->m_flipscreen)
425
curv = ((curv - 32) & 0xff) | 0x10;
427
curv = ((curv + 32) & 0xff) & ~0x10;
429
/* next one at the start of this scanline */
430
state->m_irq_timer->adjust(machine.primary_screen->time_until_pos(v_to_scanline(state, curv)), curv);
434
static TIMER_CALLBACK( clock_irq )
436
missile_state *state = machine.driver_data<missile_state>();
439
/* assert the IRQ if not already asserted */
440
state->m_irq_state = (~curv >> 5) & 1;
441
cputag_set_input_line(machine, "maincpu", 0, state->m_irq_state ? ASSERT_LINE : CLEAR_LINE);
443
/* force an update while we're here */
444
machine.primary_screen->update_partial(v_to_scanline(state, curv));
446
/* find the next edge */
447
schedule_next_irq(machine, curv);
451
static CUSTOM_INPUT( get_vblank )
453
missile_state *state = field.machine().driver_data<missile_state>();
454
int v = scanline_to_v(state, field.machine().primary_screen->vpos());
460
/*************************************
464
*************************************/
466
static TIMER_CALLBACK( adjust_cpu_speed )
468
missile_state *state = machine.driver_data<missile_state>();
471
/* starting at scanline 224, the CPU runs at half speed */
473
machine.device("maincpu")->set_unscaled_clock(MASTER_CLOCK/16);
475
machine.device("maincpu")->set_unscaled_clock(MASTER_CLOCK/8);
477
/* scanline for the next run */
479
state->m_cpu_timer->adjust(machine.primary_screen->time_until_pos(v_to_scanline(state, curv)), curv);
483
DIRECT_UPDATE_HANDLER( missile_direct_handler )
485
/* offset accounts for lack of A15 decoding */
486
int offset = address & 0x8000;
490
if (address < 0x4000)
492
missile_state *state = direct.space().machine().driver_data<missile_state>();
493
direct.explicit_configure(0x0000 | offset, 0x3fff | offset, 0x3fff, state->m_videoram);
498
else if (address >= 0x5000)
500
direct.explicit_configure(0x5000 | offset, 0x7fff | offset, 0x7fff, direct.space().machine().region("maincpu")->base() + 0x5000);
504
/* anything else falls through */
509
static MACHINE_START( missile )
511
missile_state *state = machine.driver_data<missile_state>();
512
/* initialize globals */
513
state->m_writeprom = machine.region("proms")->base();
514
state->m_flipscreen = 0;
516
/* set up an opcode base handler since we use mapped handlers for RAM */
517
address_space *space = machine.device<m6502_device>("maincpu")->space(AS_PROGRAM);
518
space->set_direct_update_handler(direct_update_delegate(FUNC(missile_direct_handler), &machine));
520
/* create a timer to speed/slow the CPU */
521
state->m_cpu_timer = machine.scheduler().timer_alloc(FUNC(adjust_cpu_speed));
522
state->m_cpu_timer->adjust(machine.primary_screen->time_until_pos(v_to_scanline(state, 0), 0));
524
/* create a timer for IRQs and set up the first callback */
525
state->m_irq_timer = machine.scheduler().timer_alloc(FUNC(clock_irq));
526
state->m_irq_state = 0;
527
schedule_next_irq(machine, -32);
529
/* setup for save states */
530
state->save_item(NAME(state->m_irq_state));
531
state->save_item(NAME(state->m_ctrld));
532
state->save_item(NAME(state->m_flipscreen));
533
state->save_item(NAME(state->m_madsel_delay));
534
state->save_item(NAME(state->m_madsel_lastpc));
538
static MACHINE_RESET( missile )
540
missile_state *state = machine.driver_data<missile_state>();
541
cputag_set_input_line(machine, "maincpu", 0, CLEAR_LINE);
542
state->m_irq_state = 0;
547
/*************************************
549
* VRAM access override
551
*************************************/
553
INLINE int get_madsel(address_space *space)
555
missile_state *state = space->machine().driver_data<missile_state>();
556
UINT16 pc = cpu_get_previouspc(&space->device());
558
/* if we're at a different instruction than last time, reset our delay counter */
559
if (pc != state->m_madsel_lastpc)
560
state->m_madsel_delay = 0;
562
/* MADSEL signal disables standard address decoding and routes
563
writes to video RAM; it is enabled if the IRQ signal is clear
564
and the low 5 bits of the fetched opcode are 0x01 */
565
if (!state->m_irq_state && (space->direct().read_decrypted_byte(pc) & 0x1f) == 0x01)
567
/* the MADSEL signal goes high 5 cycles after the opcode is identified;
568
this effectively skips the indirect memory read. Since this is difficult
569
to do in MAME, we just ignore the first two positive hits on MADSEL
570
and only return TRUE on the third or later */
571
state->m_madsel_lastpc = pc;
572
return (++state->m_madsel_delay >= 4);
574
state->m_madsel_delay = 0;
579
INLINE offs_t get_bit3_addr(offs_t pixaddr)
581
/* the 3rd bit of video RAM is scattered about various areas
582
we take a 16-bit pixel address here and convert it into
583
a video RAM address based on logic in the schematics */
584
return (( pixaddr & 0x0800) >> 1) |
585
((~pixaddr & 0x0800) >> 2) |
586
(( pixaddr & 0x07f8) >> 2) |
587
(( pixaddr & 0x1000) >> 12);
591
static void write_vram(address_space *space, offs_t address, UINT8 data)
593
missile_state *state = space->machine().driver_data<missile_state>();
594
UINT8 *videoram = state->m_videoram;
595
static const UINT8 data_lookup[4] = { 0x00, 0x0f, 0xf0, 0xff };
600
/* basic 2 bit VRAM writes go to addr >> 2 */
601
/* data comes from bits 6 and 7 */
602
/* this should only be called if MADSEL == 1 */
603
vramaddr = address >> 2;
604
vramdata = data_lookup[data >> 6];
605
vrammask = state->m_writeprom[(address & 7) | 0x10];
606
videoram[vramaddr] = (videoram[vramaddr] & vrammask) | (vramdata & ~vrammask);
608
/* 3-bit VRAM writes use an extra clock to write the 3rd bit elsewhere */
609
/* on the schematics, this is the MUSHROOM == 1 case */
610
if ((address & 0xe000) == 0xe000)
612
vramaddr = get_bit3_addr(address);
613
vramdata = -((data >> 5) & 1);
614
vrammask = state->m_writeprom[(address & 7) | 0x18];
615
videoram[vramaddr] = (videoram[vramaddr] & vrammask) | (vramdata & ~vrammask);
617
/* account for the extra clock cycle */
618
device_adjust_icount(&space->device(), -1);
623
static UINT8 read_vram(address_space *space, offs_t address)
625
missile_state *state = space->machine().driver_data<missile_state>();
626
UINT8 *videoram = state->m_videoram;
632
/* basic 2 bit VRAM reads go to addr >> 2 */
633
/* data goes to bits 6 and 7 */
634
/* this should only be called if MADSEL == 1 */
635
vramaddr = address >> 2;
636
vrammask = 0x11 << (address & 3);
637
vramdata = videoram[vramaddr] & vrammask;
638
if ((vramdata & 0xf0) == 0)
640
if ((vramdata & 0x0f) == 0)
643
/* 3-bit VRAM reads use an extra clock to read the 3rd bit elsewhere */
644
/* on the schematics, this is the MUSHROOM == 1 case */
645
if ((address & 0xe000) == 0xe000)
647
vramaddr = get_bit3_addr(address);
648
vrammask = 1 << (address & 7);
649
vramdata = videoram[vramaddr] & vrammask;
653
/* account for the extra clock cycle */
654
device_adjust_icount(&space->device(), -1);
661
/*************************************
665
*************************************/
667
static SCREEN_UPDATE( missile )
669
missile_state *state = screen->machine().driver_data<missile_state>();
670
UINT8 *videoram = state->m_videoram;
673
/* draw the bitmap to the screen, looping over Y */
674
for (y = cliprect->min_y; y <= cliprect->max_y; y++)
676
UINT16 *dst = (UINT16 *)bitmap->base + y * bitmap->rowpixels;
678
int effy = state->m_flipscreen ? ((256+24 - y) & 0xff) : y;
679
UINT8 *src = &videoram[effy * 64];
682
/* compute the base of the 3rd pixel row */
684
src3 = &videoram[get_bit3_addr(effy << 8)];
687
for (x = cliprect->min_x; x <= cliprect->max_x; x++)
689
UINT8 pix = src[x / 4] >> (x & 3);
690
pix = ((pix >> 2) & 4) | ((pix << 1) & 2);
692
/* if we're in the lower region, get the 3rd bit */
694
pix |= (src3[(x / 8) * 2] >> (x & 7)) & 1;
704
/*************************************
706
* Global read/write handlers
708
*************************************/
710
static WRITE8_HANDLER( missile_w )
712
missile_state *state = space->machine().driver_data<missile_state>();
713
UINT8 *videoram = state->m_videoram;
714
/* if we're in MADSEL mode, write to video RAM */
715
if (get_madsel(space))
717
write_vram(space, offset, data);
721
/* otherwise, strip A15 and handle manually */
726
videoram[offset] = data;
729
else if (offset < 0x4800)
730
pokey_w(space->machine().device("pokey"), offset & 0x0f, data);
733
else if (offset < 0x4900)
735
state->m_flipscreen = ~data & 0x40;
736
coin_counter_w(space->machine(), 0, data & 0x20);
737
coin_counter_w(space->machine(), 1, data & 0x10);
738
coin_counter_w(space->machine(), 2, data & 0x08);
739
set_led_status(space->machine(), 1, ~data & 0x04);
740
set_led_status(space->machine(), 0, ~data & 0x02);
741
state->m_ctrld = data & 1;
745
else if (offset >= 0x4b00 && offset < 0x4c00)
746
palette_set_color_rgb(space->machine(), offset & 7, pal1bit(~data >> 3), pal1bit(~data >> 2), pal1bit(~data >> 1));
749
else if (offset >= 0x4c00 && offset < 0x4d00)
750
watchdog_reset(space->machine());
753
else if (offset >= 0x4d00 && offset < 0x4e00)
755
if (state->m_irq_state)
757
cputag_set_input_line(space->machine(), "maincpu", 0, CLEAR_LINE);
758
state->m_irq_state = 0;
764
logerror("%04X:Unknown write to %04X = %02X\n", cpu_get_pc(&space->device()), offset, data);
768
static READ8_HANDLER( missile_r )
770
missile_state *state = space->machine().driver_data<missile_state>();
771
UINT8 *videoram = state->m_videoram;
774
/* if we're in MADSEL mode, read from video RAM */
775
if (get_madsel(space))
776
return read_vram(space, offset);
778
/* otherwise, strip A15 and handle manually */
783
result = videoram[offset];
786
else if (offset >= 0x5000)
787
result = space->machine().region("maincpu")->base()[offset];
790
else if (offset < 0x4800)
791
result = pokey_r(space->machine().device("pokey"), offset & 0x0f);
794
else if (offset < 0x4900)
796
if (state->m_ctrld) /* trackball */
798
if (!state->m_flipscreen)
799
result = ((input_port_read(space->machine(), "TRACK0_Y") << 4) & 0xf0) | (input_port_read(space->machine(), "TRACK0_X") & 0x0f);
801
result = ((input_port_read(space->machine(), "TRACK1_Y") << 4) & 0xf0) | (input_port_read(space->machine(), "TRACK1_X") & 0x0f);
804
result = input_port_read(space->machine(), "IN0");
808
else if (offset < 0x4a00)
809
result = input_port_read(space->machine(), "IN1");
812
else if (offset < 0x4b00)
813
result = input_port_read(space->machine(), "R10");
817
logerror("%04X:Unknown read from %04X\n", cpu_get_pc(&space->device()), offset);
823
/*************************************
825
* Main CPU memory handlers
827
*************************************/
829
/* complete memory map derived from schematics (implemented above) */
830
static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8 )
831
AM_RANGE(0x0000, 0xffff) AM_READWRITE(missile_r, missile_w) AM_BASE_MEMBER(missile_state, m_videoram)
836
/*************************************
840
*************************************/
842
static INPUT_PORTS_START( missile )
843
PORT_START("IN0") /* IN0 */
844
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_COCKTAIL
845
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_COCKTAIL
846
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
847
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
848
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
849
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 )
850
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
851
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN3 )
853
PORT_START("IN1") /* IN1 */
854
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 )
855
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 )
856
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 )
857
PORT_BIT( 0x18, IP_ACTIVE_HIGH, IPT_SPECIAL )
858
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_TILT )
859
PORT_SERVICE( 0x40, IP_ACTIVE_LOW )
860
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(get_vblank, NULL)
862
PORT_START("R10") /* IN2 */
863
PORT_DIPNAME( 0x03, 0x00, DEF_STR( Coinage ) ) PORT_DIPLOCATION("R10:1,2")
864
PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
865
PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
866
PORT_DIPSETTING( 0x03, DEF_STR( 1C_2C ) )
867
PORT_DIPSETTING( 0x02, DEF_STR( Free_Play ) )
868
PORT_DIPNAME( 0x0c, 0x00, "Right Coin" ) PORT_DIPLOCATION("R10:3,4")
869
PORT_DIPSETTING( 0x00, "*1" )
870
PORT_DIPSETTING( 0x04, "*4" )
871
PORT_DIPSETTING( 0x08, "*5" )
872
PORT_DIPSETTING( 0x0c, "*6" )
873
PORT_DIPNAME( 0x10, 0x00, "Center Coin" ) PORT_DIPLOCATION("R10:5")
874
PORT_DIPSETTING( 0x00, "*1" )
875
PORT_DIPSETTING( 0x10, "*2" )
876
PORT_DIPNAME( 0x60, 0x00, DEF_STR( Language ) ) PORT_DIPLOCATION("R10:6,7")
877
PORT_DIPSETTING( 0x00, DEF_STR( English ) )
878
PORT_DIPSETTING( 0x20, DEF_STR( French ) )
879
PORT_DIPSETTING( 0x40, DEF_STR( German ) )
880
PORT_DIPSETTING( 0x60, DEF_STR( Spanish ) )
881
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("R10:8")
882
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
883
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
885
PORT_START("R8") /* IN3 */
886
PORT_DIPNAME( 0x03, 0x00, "Cities" ) PORT_DIPLOCATION("R8:1,2")
887
PORT_DIPSETTING( 0x02, "4" )
888
PORT_DIPSETTING( 0x01, "5" )
889
PORT_DIPSETTING( 0x03, "6" )
890
PORT_DIPSETTING( 0x00, "7" )
891
PORT_DIPNAME( 0x04, 0x04, "Bonus Credit for 4 Coins" ) PORT_DIPLOCATION("R8:3")
892
PORT_DIPSETTING( 0x04, DEF_STR( No ) )
893
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
894
PORT_DIPNAME( 0x08, 0x00, "Trackball Size" ) PORT_DIPLOCATION("R8:4")
895
PORT_DIPSETTING( 0x00, "Large" )
896
PORT_DIPSETTING( 0x08, "Mini" )
897
PORT_DIPNAME( 0x70, 0x70, "Bonus City" ) PORT_DIPLOCATION("R8:5,6,7")
898
PORT_DIPSETTING( 0x10, "8000" )
899
PORT_DIPSETTING( 0x70, "10000" )
900
PORT_DIPSETTING( 0x60, "12000" )
901
PORT_DIPSETTING( 0x50, "14000" )
902
PORT_DIPSETTING( 0x40, "15000" )
903
PORT_DIPSETTING( 0x30, "18000" )
904
PORT_DIPSETTING( 0x20, "20000" )
905
PORT_DIPSETTING( 0x00, DEF_STR( None ) )
906
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("R8:8")
907
PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
908
PORT_DIPSETTING( 0x80, DEF_STR( Cocktail ) )
910
PORT_START("TRACK0_X") /* FAKE */
911
PORT_BIT( 0x0f, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(20) PORT_KEYDELTA(10)
913
PORT_START("TRACK0_Y") /* FAKE */
914
PORT_BIT( 0x0f, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(20) PORT_KEYDELTA(10) PORT_REVERSE
916
PORT_START("TRACK1_X") /* FAKE */
917
PORT_BIT( 0x0f, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(20) PORT_KEYDELTA(10) PORT_REVERSE PORT_COCKTAIL
919
PORT_START("TRACK1_Y") /* FAKE */
920
PORT_BIT( 0x0f, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(20) PORT_KEYDELTA(10) PORT_REVERSE PORT_COCKTAIL
924
static INPUT_PORTS_START( suprmatk )
925
PORT_START("IN0") /* IN0 */
926
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_COCKTAIL
927
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_COCKTAIL
928
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
929
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
930
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
931
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN1 )
932
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN2 )
933
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN3 )
935
PORT_START("IN1") /* IN1 */
936
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON3 )
937
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 )
938
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON1 )
939
PORT_BIT( 0x18, IP_ACTIVE_HIGH, IPT_SPECIAL )
940
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_TILT )
941
PORT_SERVICE( 0x40, IP_ACTIVE_LOW )
942
PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(get_vblank, NULL)
944
PORT_START("R10") /* IN2 */
945
PORT_DIPNAME( 0x03, 0x00, DEF_STR( Coinage ) ) PORT_DIPLOCATION("R10:1,2")
946
PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
947
PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
948
PORT_DIPSETTING( 0x03, DEF_STR( 1C_2C ) )
949
PORT_DIPSETTING( 0x02, DEF_STR( Free_Play ) )
950
PORT_DIPNAME( 0x0c, 0x00, "Right Coin" ) PORT_DIPLOCATION("R10:3,4")
951
PORT_DIPSETTING( 0x00, "*1" )
952
PORT_DIPSETTING( 0x04, "*4" )
953
PORT_DIPSETTING( 0x08, "*5" )
954
PORT_DIPSETTING( 0x0c, "*6" )
955
PORT_DIPNAME( 0x10, 0x00, "Center Coin" ) PORT_DIPLOCATION("R10:5")
956
PORT_DIPSETTING( 0x00, "*1" )
957
PORT_DIPSETTING( 0x10, "*2" )
958
PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) PORT_DIPLOCATION("R10:6")
959
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
960
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
961
PORT_DIPNAME( 0xc0, 0x40, "Game" ) PORT_DIPLOCATION("R10:7,8")
962
PORT_DIPSETTING( 0x00, "Missile Command" )
963
PORT_DIPSETTING( 0x40, "Easy Super Missile Attack" )
964
PORT_DIPSETTING( 0x80, "Reg. Super Missile Attack" )
965
PORT_DIPSETTING( 0xc0, "Hard Super Missile Attack" )
967
PORT_START("R8") /* IN3 */
968
PORT_DIPNAME( 0x03, 0x00, "Cities" ) PORT_DIPLOCATION("R8:1,2")
969
PORT_DIPSETTING( 0x02, "4" )
970
PORT_DIPSETTING( 0x01, "5" )
971
PORT_DIPSETTING( 0x03, "6" )
972
PORT_DIPSETTING( 0x00, "7" )
973
PORT_DIPNAME( 0x04, 0x04, "Bonus Credit for 4 Coins" ) PORT_DIPLOCATION("R8:3")
974
PORT_DIPSETTING( 0x04, DEF_STR( No ) )
975
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
976
PORT_DIPNAME( 0x08, 0x00, "Trackball Size" ) PORT_DIPLOCATION("R8:4")
977
PORT_DIPSETTING( 0x00, "Large" )
978
PORT_DIPSETTING( 0x08, "Mini" )
979
PORT_DIPNAME( 0x70, 0x70, "Bonus City" ) PORT_DIPLOCATION("R8:5,6,7")
980
PORT_DIPSETTING( 0x10, "8000" )
981
PORT_DIPSETTING( 0x70, "10000" )
982
PORT_DIPSETTING( 0x60, "12000" )
983
PORT_DIPSETTING( 0x50, "14000" )
984
PORT_DIPSETTING( 0x40, "15000" )
985
PORT_DIPSETTING( 0x30, "18000" )
986
PORT_DIPSETTING( 0x20, "20000" )
987
PORT_DIPSETTING( 0x00, DEF_STR( None ) )
988
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("R8:8")
989
PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
990
PORT_DIPSETTING( 0x80, DEF_STR( Cocktail ) )
992
PORT_START("TRACK0_X") /* FAKE */
993
PORT_BIT( 0x0f, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(20) PORT_KEYDELTA(10)
995
PORT_START("TRACK0_Y") /* FAKE */
996
PORT_BIT( 0x0f, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(20) PORT_KEYDELTA(10) PORT_REVERSE
998
PORT_START("TRACK1_X") /* FAKE */
999
PORT_BIT( 0x0f, 0x00, IPT_TRACKBALL_X ) PORT_SENSITIVITY(20) PORT_KEYDELTA(10) PORT_REVERSE PORT_COCKTAIL
1001
PORT_START("TRACK1_Y") /* FAKE */
1002
PORT_BIT( 0x0f, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(20) PORT_KEYDELTA(10) PORT_REVERSE PORT_COCKTAIL
1007
/*************************************
1011
*************************************/
1013
static const pokey_interface pokey_config =
1016
DEVCB_INPUT_PORT("R8")
1021
/*************************************
1025
*************************************/
1027
static MACHINE_CONFIG_START( missile, missile_state )
1029
/* basic machine hardware */
1030
MCFG_CPU_ADD("maincpu", M6502, MASTER_CLOCK/8)
1031
MCFG_CPU_PROGRAM_MAP(main_map)
1033
MCFG_MACHINE_START(missile)
1034
MCFG_MACHINE_RESET(missile)
1035
MCFG_WATCHDOG_VBLANK_INIT(8)
1037
/* video hardware */
1038
MCFG_PALETTE_LENGTH(8)
1040
MCFG_SCREEN_ADD("screen", RASTER)
1041
MCFG_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
1042
MCFG_SCREEN_RAW_PARAMS(PIXEL_CLOCK, HTOTAL, HBEND, HBSTART, VTOTAL, VBEND, VBSTART)
1043
MCFG_SCREEN_UPDATE(missile)
1045
/* sound hardware */
1046
MCFG_SPEAKER_STANDARD_MONO("mono")
1048
MCFG_SOUND_ADD("pokey", POKEY, MASTER_CLOCK/8)
1049
MCFG_SOUND_CONFIG(pokey_config)
1050
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.0)
1055
/*************************************
1059
*************************************/
1061
ROM_START( missile )
1062
ROM_REGION( 0x8000, "maincpu", 0 )
1063
ROM_LOAD( "035820-02.h1", 0x5000, 0x0800, CRC(7a62ce6a) SHA1(9a39978138dc28fdefe193bfae1b226391e471db) )
1064
ROM_LOAD( "035821-02.jk1", 0x5800, 0x0800, CRC(df3bd57f) SHA1(0916925d3c94d766d33f0e4badf6b0add835d748) )
1065
ROM_LOAD( "035822-02.kl1", 0x6000, 0x0800, CRC(a1cd384a) SHA1(a1dd0953423750a0fbc6e3dccbf2ca64ef5a1f54) )
1066
ROM_LOAD( "035823-02.ln1", 0x6800, 0x0800, CRC(82e552bb) SHA1(d0f22894f779c74ceef644c9f03d840d9545efea) )
1067
ROM_LOAD( "035824-02.np1", 0x7000, 0x0800, CRC(606e42e0) SHA1(9718f84a73c66b4e8ef7805a7ab638a7380624e1) )
1068
ROM_LOAD( "035825-02.r1", 0x7800, 0x0800, CRC(f752eaeb) SHA1(0339a6ce6744d2091cc7e07675e509b202b0f380) )
1070
ROM_REGION( 0x0020, "proms", 0 )
1071
ROM_LOAD( "035826-01.l6", 0x0000, 0x0020, CRC(86a22140) SHA1(2beebf7855e29849ada1823eae031fc98220bc43) )
1075
ROM_START( missile2 )
1076
ROM_REGION( 0x8000, "maincpu", 0 )
1077
ROM_LOAD( "35820-01.h1", 0x5000, 0x0800, CRC(41cbb8f2) SHA1(5dcb58276c08d75d36baadb6cefe30d4916de9b0) )
1078
ROM_LOAD( "35821-01.jk1", 0x5800, 0x0800, CRC(728702c8) SHA1(6f25af7133d3ec79029117162649f94e93f36e0e) )
1079
ROM_LOAD( "35822-01.kl1", 0x6000, 0x0800, CRC(28f0999f) SHA1(eb52b11c6757c8dc3be88b276ea4dc7dfebf7cf7) )
1080
ROM_LOAD( "35823-01.ln1", 0x6800, 0x0800, CRC(bcc93c94) SHA1(f0daa5d2835a856e2038612e755dc7ded28fc923) )
1081
ROM_LOAD( "35824-01.np1", 0x7000, 0x0800, CRC(0ca089c8) SHA1(7f69ee990fd4fa1f2fceca7fc66fcaa02e4d2314) )
1082
ROM_LOAD( "35825-01.r1", 0x7800, 0x0800, CRC(428cf0d5) SHA1(03cabbef50c33852fbbf38dd3eecaf70a82df82f) )
1084
ROM_REGION( 0x0020, "proms", 0 )
1085
ROM_LOAD( "035826-01.l6", 0x0000, 0x0020, CRC(86a22140) SHA1(2beebf7855e29849ada1823eae031fc98220bc43) )
1089
ROM_START( suprmatk )
1090
ROM_REGION( 0x9000, "maincpu", 0 ) /* ROM's located on the enhancement board */
1091
ROM_LOAD( "035820-02.c1", 0x5000, 0x0800, CRC(7a62ce6a) SHA1(9a39978138dc28fdefe193bfae1b226391e471db) )
1092
ROM_LOAD( "035821-02.b1", 0x5800, 0x0800, CRC(df3bd57f) SHA1(0916925d3c94d766d33f0e4badf6b0add835d748) )
1093
ROM_LOAD( "035822-02.a1", 0x6000, 0x0800, CRC(a1cd384a) SHA1(a1dd0953423750a0fbc6e3dccbf2ca64ef5a1f54) )
1094
ROM_LOAD( "035823-02.a5", 0x6800, 0x0800, CRC(82e552bb) SHA1(d0f22894f779c74ceef644c9f03d840d9545efea) )
1095
ROM_LOAD( "035824-02.b5", 0x7000, 0x0800, CRC(606e42e0) SHA1(9718f84a73c66b4e8ef7805a7ab638a7380624e1) )
1096
ROM_LOAD( "035825-02.c5", 0x7800, 0x0800, CRC(f752eaeb) SHA1(0339a6ce6744d2091cc7e07675e509b202b0f380) )
1097
ROM_LOAD( "e0.d5", 0x8000, 0x0800, CRC(d0b20179) SHA1(e2a9855899b6ff96b8dba169e0ab83f00a95919f) )
1098
ROM_LOAD( "e1.e5", 0x8800, 0x0800, CRC(c6c818a3) SHA1(b9c92a85c07dd343d990e196d37b92d92a85a5e0) )
1100
ROM_REGION( 0x0020, "proms", 0 ) /* PROM located on the Missile Command board */
1101
ROM_LOAD( "035826-01.l6", 0x0000, 0x0020, CRC(86a22140) SHA1(2beebf7855e29849ada1823eae031fc98220bc43) )
1103
ROM_REGION( 0x0200, "proms2", 0 ) /* 63S141 PROMs located on the enhancement board */
1104
ROM_LOAD( "63s141.b2", 0x0000, 0x0100, CRC(2de8ee4d) SHA1(ff28c007df9c52227dfce76af6f7b1dfac3c2296) )
1105
ROM_LOAD( "63s141.b4", 0x0100, 0x0100, CRC(390fc532) SHA1(f9adde3f18f3db225ac3f3771c38ff139ef0a65e) )
1109
ROM_START( suprmatkd )
1110
ROM_REGION( 0x8000, "maincpu", 0 )
1111
ROM_LOAD( "035820.sma", 0x5000, 0x0800, CRC(75f01b87) SHA1(32ed71b6a869d7b361f244c384bbe6f407f6c6d7) )
1112
ROM_LOAD( "035821.sma", 0x5800, 0x0800, CRC(3320d67e) SHA1(5bb04b985421af6309818b94676298f4b90495cf) )
1113
ROM_LOAD( "035822.sma", 0x6000, 0x0800, CRC(e6be5055) SHA1(43912cc565cb43256a9193594cf36abab1c85d6f) )
1114
ROM_LOAD( "035823.sma", 0x6800, 0x0800, CRC(a6069185) SHA1(899cd8b378802eb6253d4bca7432797168595d53) )
1115
ROM_LOAD( "035824.sma", 0x7000, 0x0800, CRC(90a06be8) SHA1(f46fd6847bc9836d11ea0042df19fbf33ddab0db) )
1116
ROM_LOAD( "035825.sma", 0x7800, 0x0800, CRC(1298213d) SHA1(c8e4301704e3700c339557f2a833e70f6a068d5e) )
1118
ROM_REGION( 0x0020, "proms", 0 )
1119
ROM_LOAD( "035826-01.l6", 0x0000, 0x0020, CRC(86a22140) SHA1(2beebf7855e29849ada1823eae031fc98220bc43) )
1125
Missile Combat bootlegs by 'Videotron'
1128
1x AY-3-8912 (sound)
1131
PCB is marked: "VIDEOTRON BOLOGNA 002"
1135
ROM_START( mcombat )
1136
ROM_REGION( 0x8000, "maincpu", 0 )
1137
ROM_LOAD( "002-0-0.10a", 0x5000, 0x0800, CRC(589b81de) SHA1(06f18a837cedb0da5464dfaa04f92bd035db3752) )
1138
ROM_LOAD( "002-1-1.9a", 0x5800, 0x0800, CRC(08796a78) SHA1(e5aabe775889752ad1581098fcbf52ff1fa03b3b) )
1139
ROM_LOAD( "002-2-2.8a", 0x6000, 0x0800, CRC(59ab750c) SHA1(4555c27ddeb22ba895610a9c516fe574664a6f4b) )
1140
ROM_LOAD( "002-3-3.7a", 0x6800, 0x0800, CRC(3295cc3f) SHA1(2be0d492bd791df19d138d5bfe956361ee461989) )
1141
ROM_LOAD( "002-4-4.6a", 0x7000, 0x0800, CRC(aac71e95) SHA1(7daf115eb2cdde69b7c4de1e1a6ee68cd2fd0f2c) )
1142
ROM_LOAD( "002-5-5.5a", 0x7800, 0x0800, CRC(1b9a16e2) SHA1(03fb292bb6f815724b2fc4b2f561398000367373) )
1144
ROM_REGION( 0x0020, "proms", 0 )
1145
ROM_LOAD( "mmi6331.6f", 0x0000, 0x0020, CRC(86a22140) SHA1(2beebf7855e29849ada1823eae031fc98220bc43) )
1149
ROM_START( mcombata )
1150
ROM_REGION( 0x8000, "maincpu", 0 )
1151
ROM_LOAD( "002-0-0.10a", 0x5000, 0x0800, CRC(589b81de) SHA1(06f18a837cedb0da5464dfaa04f92bd035db3752) )
1152
ROM_LOAD( "002-1-1.9a", 0x5800, 0x0800, CRC(08796a78) SHA1(e5aabe775889752ad1581098fcbf52ff1fa03b3b) )
1153
ROM_LOAD( "002-2-2.8a", 0x6000, 0x0800, CRC(59ab750c) SHA1(4555c27ddeb22ba895610a9c516fe574664a6f4b) )
1154
ROM_LOAD( "3.bin", 0x6800, 0x0800, CRC(ddbfda20) SHA1(444daaa76751853f67a7c0e5bf620ae5623d2105) )
1155
ROM_LOAD( "4.bin", 0x7000, 0x0800, CRC(e3b5428d) SHA1(ac9eb459df68a117a49e92fbc5ed88faaf46a395) )
1156
ROM_LOAD( "002-5-5.5a", 0x7800, 0x0800, CRC(1b9a16e2) SHA1(03fb292bb6f815724b2fc4b2f561398000367373) )
1158
ROM_REGION( 0x0020, "proms", 0 )
1159
ROM_LOAD( "mmi6331.6f", 0x0000, 0x0020, CRC(86a22140) SHA1(2beebf7855e29849ada1823eae031fc98220bc43) )
1162
/*************************************
1164
* Driver initialization
1166
*************************************/
1168
static DRIVER_INIT( suprmatk )
1171
UINT8 *rom = machine.region("maincpu")->base();
1173
for (i = 0; i < 0x40; i++)
1175
rom[0x7CC0+i] = rom[0x8000+i];
1176
rom[0x5440+i] = rom[0x8040+i];
1177
rom[0x5B00+i] = rom[0x8080+i];
1178
rom[0x5740+i] = rom[0x80C0+i];
1179
rom[0x6000+i] = rom[0x8100+i];
1180
rom[0x6540+i] = rom[0x8140+i];
1181
rom[0x7500+i] = rom[0x8180+i];
1182
rom[0x7100+i] = rom[0x81C0+i];
1183
rom[0x7800+i] = rom[0x8200+i];
1184
rom[0x5580+i] = rom[0x8240+i];
1185
rom[0x5380+i] = rom[0x8280+i];
1186
rom[0x6900+i] = rom[0x82C0+i];
1187
rom[0x6E00+i] = rom[0x8300+i];
1188
rom[0x6CC0+i] = rom[0x8340+i];
1189
rom[0x7DC0+i] = rom[0x8380+i];
1190
rom[0x5B80+i] = rom[0x83C0+i];
1191
rom[0x5000+i] = rom[0x8400+i];
1192
rom[0x7240+i] = rom[0x8440+i];
1193
rom[0x7040+i] = rom[0x8480+i];
1194
rom[0x62C0+i] = rom[0x84C0+i];
1195
rom[0x6840+i] = rom[0x8500+i];
1196
rom[0x7EC0+i] = rom[0x8540+i];
1197
rom[0x7D40+i] = rom[0x8580+i];
1198
rom[0x66C0+i] = rom[0x85C0+i];
1199
rom[0x72C0+i] = rom[0x8600+i];
1200
rom[0x7080+i] = rom[0x8640+i];
1201
rom[0x7D00+i] = rom[0x8680+i];
1202
rom[0x5F00+i] = rom[0x86C0+i];
1203
rom[0x55C0+i] = rom[0x8700+i];
1204
rom[0x5A80+i] = rom[0x8740+i];
1205
rom[0x6080+i] = rom[0x8780+i];
1206
rom[0x7140+i] = rom[0x87C0+i];
1207
rom[0x7000+i] = rom[0x8800+i];
1208
rom[0x6100+i] = rom[0x8840+i];
1209
rom[0x5400+i] = rom[0x8880+i];
1210
rom[0x5BC0+i] = rom[0x88C0+i];
1211
rom[0x7E00+i] = rom[0x8900+i];
1212
rom[0x71C0+i] = rom[0x8940+i];
1213
rom[0x6040+i] = rom[0x8980+i];
1214
rom[0x6E40+i] = rom[0x89C0+i];
1215
rom[0x5800+i] = rom[0x8A00+i];
1216
rom[0x7D80+i] = rom[0x8A40+i];
1217
rom[0x7A80+i] = rom[0x8A80+i];
1218
rom[0x53C0+i] = rom[0x8AC0+i];
1219
rom[0x6140+i] = rom[0x8B00+i];
1220
rom[0x6700+i] = rom[0x8B40+i];
1221
rom[0x7280+i] = rom[0x8B80+i];
1222
rom[0x7F00+i] = rom[0x8BC0+i];
1223
rom[0x5480+i] = rom[0x8C00+i];
1224
rom[0x70C0+i] = rom[0x8C40+i];
1225
rom[0x7F80+i] = rom[0x8C80+i];
1226
rom[0x5780+i] = rom[0x8CC0+i];
1227
rom[0x6680+i] = rom[0x8D00+i];
1228
rom[0x7200+i] = rom[0x8D40+i];
1229
rom[0x7E40+i] = rom[0x8D80+i];
1230
rom[0x7AC0+i] = rom[0x8DC0+i];
1231
rom[0x6300+i] = rom[0x8E00+i];
1232
rom[0x7180+i] = rom[0x8E40+i];
1233
rom[0x7E80+i] = rom[0x8E80+i];
1234
rom[0x6280+i] = rom[0x8EC0+i];
1235
rom[0x7F40+i] = rom[0x8F00+i];
1236
rom[0x6740+i] = rom[0x8F40+i];
1237
rom[0x74C0+i] = rom[0x8F80+i];
1238
rom[0x7FC0+i] = rom[0x8FC0+i];
1243
/*************************************
1247
*************************************/
1249
GAME( 1980, missile, 0, missile, missile, 0, ROT0, "Atari", "Missile Command (set 1)", GAME_SUPPORTS_SAVE )
1250
GAME( 1980, missile2, missile, missile, missile, 0, ROT0, "Atari", "Missile Command (set 2)", GAME_SUPPORTS_SAVE )
1251
GAME( 1981, suprmatk, missile, missile, suprmatk, suprmatk, ROT0, "Atari / Gencomp", "Super Missile Attack (for set 2)", GAME_SUPPORTS_SAVE )
1252
GAME( 1981, suprmatkd,missile, missile, suprmatk, 0, ROT0, "Atari / Gencomp", "Super Missile Attack (not encrypted)", GAME_SUPPORTS_SAVE )
1254
/* the bootlegs are on different hardware and don't work */
1255
GAME( 198?, mcombat, missile, missile, missile, 0, ROT0, "bootleg (Videotron)", "Missile Combat (Videotron bootleg, set 1)", GAME_NOT_WORKING )
1256
GAME( 198?, mcombata, missile, missile, missile, 0, ROT0, "bootleg (Videotron)", "Missile Combat (Videotron bootleg, set 2)", GAME_NOT_WORKING )
added
removed
mess/src/mame/drivers/missile.c
