1
/***************************************************************************
5
***************************************************************************/
10
#include "includes/mcr.h"
13
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
16
/*************************************
20
*************************************/
22
UINT8 mcr_cocktail_flip;
25
UINT32 mcr_sprite_board;
29
/*************************************
33
*************************************/
35
static emu_timer *ipu_watchdog_timer;
38
/*************************************
42
*************************************/
44
static TIMER_CALLBACK( ipu_watchdog_reset );
45
static WRITE8_DEVICE_HANDLER( ipu_break_changed );
49
/*************************************
51
* Graphics declarations
53
*************************************/
55
const gfx_layout mcr_bg_layout =
60
{ STEP2(RGN_FRAC(1,2),1), STEP2(RGN_FRAC(0,2),1) },
67
const gfx_layout mcr_sprite_layout =
73
{ STEP2(RGN_FRAC(0,4)+0,4), STEP2(RGN_FRAC(1,4)+0,4), STEP2(RGN_FRAC(2,4)+0,4), STEP2(RGN_FRAC(3,4)+0,4),
74
STEP2(RGN_FRAC(0,4)+8,4), STEP2(RGN_FRAC(1,4)+8,4), STEP2(RGN_FRAC(2,4)+8,4), STEP2(RGN_FRAC(3,4)+8,4),
75
STEP2(RGN_FRAC(0,4)+16,4), STEP2(RGN_FRAC(1,4)+16,4), STEP2(RGN_FRAC(2,4)+16,4), STEP2(RGN_FRAC(3,4)+16,4),
76
STEP2(RGN_FRAC(0,4)+24,4), STEP2(RGN_FRAC(1,4)+24,4), STEP2(RGN_FRAC(2,4)+24,4), STEP2(RGN_FRAC(3,4)+24,4) },
83
/*************************************
85
* Generic MCR CTC interface
87
*************************************/
89
const z80_daisy_config mcr_daisy_chain[] =
96
const z80_daisy_config mcr_ipu_daisy_chain[] =
106
Z80CTC_INTERFACE( mcr_ctc_intf )
108
0, /* timer disables */
109
DEVCB_CPU_INPUT_LINE("maincpu", INPUT_LINE_IRQ0), /* interrupt handler */
110
DEVCB_LINE(z80ctc_trg1_w), /* ZC/TO0 callback */
111
DEVCB_NULL, /* ZC/TO1 callback */
112
DEVCB_NULL /* ZC/TO2 callback */
116
Z80CTC_INTERFACE( nflfoot_ctc_intf )
118
0, /* timer disables */
119
DEVCB_CPU_INPUT_LINE("ipu", INPUT_LINE_IRQ0), /* interrupt handler */
120
DEVCB_NULL, /* ZC/TO0 callback */
121
DEVCB_NULL, /* ZC/TO1 callback */
122
DEVCB_NULL /* ZC/TO2 callback */
126
Z80PIO_INTERFACE( nflfoot_pio_intf )
128
DEVCB_CPU_INPUT_LINE("ipu", INPUT_LINE_IRQ0), /* interrupt handler */
138
static WRITE_LINE_DEVICE_HANDLER( ipu_ctc_interrupt )
140
cputag_set_input_line(device->machine(), "ipu", 0, state);
144
const z80sio_interface nflfoot_sio_intf =
146
ipu_ctc_interrupt, /* interrupt handler */
147
0, /* DTR changed handler */
148
0, /* RTS changed handler */
149
ipu_break_changed, /* BREAK changed handler */
150
mcr_ipu_sio_transmit/* transmit handler */
155
/*************************************
157
* Generic MCR machine initialization
159
*************************************/
163
state_save_register_global(machine, mcr_cocktail_flip);
167
MACHINE_START( nflfoot )
169
/* allocate a timer for the IPU watchdog */
170
ipu_watchdog_timer = machine.scheduler().timer_alloc(FUNC(ipu_watchdog_reset));
176
/* reset cocktail flip */
177
mcr_cocktail_flip = 0;
179
/* initialize the sound */
180
mcr_sound_reset(machine);
185
/*************************************
187
* Generic MCR interrupt handler
189
*************************************/
191
INTERRUPT_GEN( mcr_interrupt )
193
device_t *ctc = device->machine().device("ctc");
195
/* CTC line 2 is connected to VBLANK, which is once every 1/2 frame */
196
/* for the 30Hz interlaced display */
197
z80ctc_trg2_w(ctc, 1);
198
z80ctc_trg2_w(ctc, 0);
200
/* CTC line 3 is connected to 493, which is signalled once every */
202
if (cpu_getiloops(device) == 0)
204
z80ctc_trg3_w(ctc, 1);
205
z80ctc_trg3_w(ctc, 0);
210
INTERRUPT_GEN( mcr_ipu_interrupt )
212
device_t *ctc = device->machine().device("ipu_ctc");
214
/* CTC line 3 is connected to 493, which is signalled once every */
216
if (cpu_getiloops(device) == 0)
218
z80ctc_trg3_w(ctc, 1);
219
z80ctc_trg3_w(ctc, 0);
224
/*************************************
226
* Generic MCR port write handlers
228
*************************************/
230
WRITE8_HANDLER( mcr_control_port_w )
233
Bit layout is as follows:
244
coin_counter_w(space->machine(), 0, (data >> 0) & 1);
245
coin_counter_w(space->machine(), 1, (data >> 1) & 1);
246
coin_counter_w(space->machine(), 2, (data >> 2) & 1);
247
mcr_cocktail_flip = (data >> 6) & 1;
251
/*************************************
253
* NFL Football IPU board
255
*************************************/
257
static WRITE8_DEVICE_HANDLER( ipu_break_changed )
259
/* channel B is connected to the CED player */
262
logerror("DTR changed -> %d\n", data);
264
z80sio_receive_data(device, 1, 0);
269
WRITE8_HANDLER( mcr_ipu_laserdisk_w )
271
/* bit 3 enables (1) LD video regardless of PIX SW */
272
/* bit 2 enables (1) LD right channel audio */
273
/* bit 1 enables (1) LD left channel audio */
274
/* bit 0 enables (1) LD video if PIX SW == 1 */
276
logerror("%04X:mcr_ipu_laserdisk_w(%d) = %02X\n", cpu_get_pc(&space->device()), offset, data);
280
static TIMER_CALLBACK( ipu_watchdog_reset )
282
logerror("ipu_watchdog_reset\n");
283
cputag_set_input_line(machine, "ipu", INPUT_LINE_RESET, PULSE_LINE);
284
devtag_reset(machine, "ipu_ctc");
285
devtag_reset(machine, "ipu_pio0");
286
devtag_reset(machine, "ipu_pio1");
287
devtag_reset(machine, "ipu_sio");
291
READ8_HANDLER( mcr_ipu_watchdog_r )
293
/* watchdog counter is clocked by 7.3728MHz crystal / 16 */
294
/* watchdog is tripped when 14-bit counter overflows => / 32768 = 14.0625Hz*/
295
ipu_watchdog_timer->adjust(attotime::from_hz(7372800 / 16 / 32768));
300
WRITE8_HANDLER( mcr_ipu_watchdog_w )
302
mcr_ipu_watchdog_r(space,0);