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  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Jordi Mallach, Emmanuel Kasper
  • Date: 2011-12-19 22:56:27 UTC
  • mfrom: (0.1.2)
  • Revision ID: package-import@ubuntu.com-20111219225627-ub5oga1oys4ogqzm
Tags: 0.144-1
http://bugs.debian.org/651538
[ Jordi Mallach ]
* Fix syntax errors in DEP5 copyright file (lintian).
* Use a versioned copyright Format specification field.
* Update Vcs-* URLs.
* Move transitional packages to the new metapackages section, and make
  them priority extra.
* Remove references to GNU/Linux and MESS sources from copyright.
* Add build variables for s390x.
* Use .xz tarballs as it cuts 4MB for the upstream sources.
* Add nplayers.ini as a patch. Update copyright file to add CC-BY-SA-3.0.

[ Emmanuel Kasper ]
* New upstream release. Closes: #651538.
* Add Free Desktop compliant png icons of various sizes taken from
  the hydroxygen iconset
* Mess is now built from a new source package, to avoid possible source
  incompatibilities between mame and the mess overlay.
* Mame-tools are not built from the mame source package anymore, but
  from the mess source package

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mess/src/emu/cpu/sc61860/scops.c
1
 
/*****************************************************************************
2
 
 *
3
 
 *   scops.c
4
 
 *   portable sharp 61860 emulator interface
5
 
 *   (sharp pocket computers)
6
 
 *
7
 
 *   Copyright Peter Trauner, all rights reserved.
8
 
 *
9
 
 *   - This source code is released as freeware for non-commercial purposes.
10
 
 *   - You are free to use and redistribute this code in modified or
11
 
 *     unmodified form, provided you list me in the credits.
12
 
 *   - If you modify this source code, you must add a notice to each modified
13
 
 *     source file that it has been changed.  If you're a nice person, you
14
 
 *     will clearly mark each change too.  :)
15
 
 *   - If you wish to use this for commercial purposes, please contact me at
16
 
 *     peter.trauner@jk.uni-linz.ac.at
17
 
 *   - The author of this copywritten work reserves the right to change the
18
 
 *     terms of its usage and license at any time, including retroactively
19
 
 *   - This entire notice must remain in the source code.
20
 
 *
21
 
 * History of changes:
22
 
 * 21.07.2001 Several changes listed below were made by Mario Konegger
23
 
 *            (konegger@itp.tu-graz.ac.at)
24
 
 *        replaced buggy BCD-commands add_bcd, sub_bcd, add_bcd_a,
25
 
 *            sub_bcd_a and changed out_c, to implement HLT-mode of the CPU.
26
 
 *
27
 
 *****************************************************************************/
28
 
 
29
 
INLINE UINT8 READ_OP(sc61860_state *cpustate)
30
 
{
31
 
        return cpustate->direct->read_decrypted_byte(cpustate->pc++);
32
 
}
33
 
 
34
 
INLINE UINT8 READ_OP_ARG(sc61860_state *cpustate)
35
 
{
36
 
        return cpustate->direct->read_raw_byte(cpustate->pc++);
37
 
}
38
 
 
39
 
INLINE UINT16 READ_OP_ARG_WORD(sc61860_state *cpustate)
40
 
{
41
 
        UINT16 t=cpustate->direct->read_decrypted_byte(cpustate->pc++)<<8;
42
 
        t|=cpustate->direct->read_decrypted_byte(cpustate->pc++);
43
 
        return t;
44
 
}
45
 
 
46
 
INLINE UINT8 READ_BYTE(sc61860_state *cpustate, UINT16 adr)
47
 
{
48
 
        return cpustate->program->read_byte(adr);
49
 
}
50
 
 
51
 
INLINE void WRITE_BYTE(sc61860_state *cpustate, UINT16 a, UINT8 v)
52
 
{
53
 
        cpustate->program->write_byte(a, v);
54
 
}
55
 
 
56
 
INLINE UINT8 READ_RAM(sc61860_state *cpustate, int r)
57
 
{
58
 
        return cpustate->ram[r];
59
 
}
60
 
 
61
 
INLINE void WRITE_RAM(sc61860_state *cpustate, int r, UINT8 v)
62
 
{
63
 
        cpustate->ram[r] = v;
64
 
}
65
 
 
66
 
INLINE void PUSH(sc61860_state *cpustate, UINT8 v)
67
 
{
68
 
        cpustate->r--;
69
 
        WRITE_RAM(cpustate, cpustate->r, v);
70
 
}
71
 
 
72
 
INLINE UINT8 POP(sc61860_state *cpustate)
73
 
{
74
 
        UINT8 t = READ_RAM(cpustate, cpustate->r);
75
 
        cpustate->r++;
76
 
        return t;
77
 
}
78
 
 
79
 
INLINE void sc61860_load_imm(sc61860_state *cpustate, int r, UINT8 v)
80
 
{
81
 
        WRITE_RAM(cpustate, r, v);
82
 
}
83
 
 
84
 
INLINE void sc61860_load(sc61860_state *cpustate)
85
 
{
86
 
        WRITE_RAM(cpustate, A, READ_RAM(cpustate, cpustate->p));
87
 
}
88
 
 
89
 
INLINE void sc61860_load_imm_p(sc61860_state *cpustate, UINT8 v)
90
 
{
91
 
        cpustate->p=v&0x7f;
92
 
}
93
 
 
94
 
INLINE void sc61860_load_imm_q(sc61860_state *cpustate, UINT8 v)
95
 
{
96
 
        cpustate->q=v&0x7f;
97
 
}
98
 
 
99
 
INLINE void sc61860_load_r(sc61860_state *cpustate)
100
 
{
101
 
        cpustate->r = READ_RAM(cpustate, A) & 0x7f;
102
 
}
103
 
 
104
 
INLINE void sc61860_load_ext(sc61860_state *cpustate, int r)
105
 
{
106
 
        WRITE_RAM(cpustate, r, READ_BYTE(cpustate, cpustate->dp));
107
 
}
108
 
 
109
 
INLINE void sc61860_load_dp(sc61860_state *cpustate)
110
 
{
111
 
        cpustate->dp=READ_OP_ARG_WORD(cpustate);
112
 
}
113
 
 
114
 
INLINE void sc61860_load_dl(sc61860_state *cpustate)
115
 
{
116
 
        cpustate->dp=(cpustate->dp&~0xff)|READ_OP_ARG(cpustate);
117
 
}
118
 
 
119
 
INLINE void sc61860_store_p(sc61860_state *cpustate)
120
 
{
121
 
        WRITE_RAM(cpustate, A, cpustate->p);
122
 
}
123
 
 
124
 
INLINE void sc61860_store_q(sc61860_state *cpustate)
125
 
{
126
 
        WRITE_RAM(cpustate, A, cpustate->q);
127
 
}
128
 
 
129
 
INLINE void sc61860_store_r(sc61860_state *cpustate)
130
 
{
131
 
        WRITE_RAM(cpustate, A, cpustate->r);
132
 
}
133
 
 
134
 
INLINE void sc61860_store_ext(sc61860_state *cpustate, int r)
135
 
{
136
 
        WRITE_BYTE(cpustate, cpustate->dp, READ_RAM(cpustate, r));
137
 
}
138
 
 
139
 
INLINE void sc61860_exam(sc61860_state *cpustate, int a, int b)
140
 
{
141
 
        UINT8 t = READ_RAM(cpustate, a);
142
 
        WRITE_RAM(cpustate, a, READ_RAM(cpustate, b));
143
 
        WRITE_RAM(cpustate, b, t);
144
 
}
145
 
 
146
 
INLINE void sc61860_test(sc61860_state *cpustate, int reg, UINT8 value)
147
 
{
148
 
        cpustate->zero=(READ_RAM(cpustate, reg) & value)==0;
149
 
}
150
 
 
151
 
INLINE void sc61860_test_ext(sc61860_state *cpustate)
152
 
{
153
 
        cpustate->zero=(READ_BYTE(cpustate, cpustate->dp)&READ_OP_ARG(cpustate))==0;
154
 
}
155
 
 
156
 
INLINE void sc61860_and(sc61860_state *cpustate, int reg, UINT8 value)
157
 
{
158
 
        UINT8 t = READ_RAM(cpustate, reg) & value;
159
 
        WRITE_RAM(cpustate, reg,  t);
160
 
        cpustate->zero=t==0;
161
 
}
162
 
 
163
 
INLINE void sc61860_and_ext(sc61860_state *cpustate)
164
 
{
165
 
        UINT8 t = READ_BYTE(cpustate, cpustate->dp) & READ_OP_ARG(cpustate);
166
 
        cpustate->zero=t==0;
167
 
        WRITE_BYTE(cpustate, cpustate->dp, t);
168
 
}
169
 
 
170
 
INLINE void sc61860_or(sc61860_state *cpustate, int reg, UINT8 value)
171
 
{
172
 
        UINT8 t = READ_RAM(cpustate, reg) | value;
173
 
        WRITE_RAM(cpustate, reg, t);
174
 
        cpustate->zero=t==0;
175
 
}
176
 
 
177
 
INLINE void sc61860_or_ext(sc61860_state *cpustate)
178
 
{
179
 
        UINT8 t=READ_BYTE(cpustate, cpustate->dp)|READ_OP_ARG(cpustate);
180
 
        cpustate->zero=t==0;
181
 
        WRITE_BYTE(cpustate, cpustate->dp, t);
182
 
}
183
 
 
184
 
INLINE void sc61860_rotate_right(sc61860_state *cpustate)
185
 
{
186
 
        int t = READ_RAM(cpustate, A);
187
 
        if (cpustate->carry) t|=0x100;
188
 
        cpustate->carry=t&1;
189
 
        WRITE_RAM(cpustate, A, t>>1);
190
 
}
191
 
 
192
 
INLINE void sc61860_rotate_left(sc61860_state *cpustate)
193
 
{
194
 
        int t = READ_RAM(cpustate, A) << 1;
195
 
        if (cpustate->carry) t|=1;
196
 
        cpustate->carry=t&0x100;
197
 
        WRITE_RAM(cpustate, A, t);
198
 
}
199
 
 
200
 
INLINE void sc61860_swap(sc61860_state *cpustate)
201
 
{
202
 
        int t = READ_RAM(cpustate, A);
203
 
        WRITE_RAM(cpustate, A, (t<<4)|((t>>4)&0xf));
204
 
}
205
 
 
206
 
// q=reg sideeffect
207
 
INLINE void sc61860_inc(sc61860_state *cpustate, int reg)
208
 
{
209
 
        UINT8 t = READ_RAM(cpustate, reg) + 1;
210
 
        cpustate->q=reg;
211
 
        WRITE_RAM(cpustate, reg, t);
212
 
        cpustate->zero=t==0;
213
 
        cpustate->carry=t==0;
214
 
}
215
 
 
216
 
INLINE void sc61860_inc_p(sc61860_state *cpustate)
217
 
{
218
 
        cpustate->p++;
219
 
}
220
 
 
221
 
// q=reg sideeffect
222
 
INLINE void sc61860_dec(sc61860_state *cpustate, int reg)
223
 
{
224
 
        UINT8 t = READ_RAM(cpustate, reg) - 1;
225
 
        cpustate->q=reg;
226
 
        WRITE_RAM(cpustate, reg, t);
227
 
        cpustate->zero=t==0;
228
 
        cpustate->carry=t==0xff;
229
 
}
230
 
 
231
 
INLINE void sc61860_dec_p(sc61860_state *cpustate)
232
 
{
233
 
        cpustate->p--;
234
 
}
235
 
 
236
 
INLINE void sc61860_add(sc61860_state *cpustate, int reg, UINT8 value)
237
 
{
238
 
        int t = READ_RAM(cpustate, reg) + value;
239
 
        WRITE_RAM(cpustate, reg, t);
240
 
        cpustate->zero=(t&0xff)==0;
241
 
        cpustate->carry=t>=0x100;
242
 
}
243
 
 
244
 
INLINE void sc61860_add_carry(sc61860_state *cpustate)
245
 
{
246
 
        int t = READ_RAM(cpustate, cpustate->p) + READ_RAM(cpustate, A);
247
 
        if (cpustate->carry) t++;
248
 
        WRITE_RAM(cpustate, cpustate->p, t);
249
 
        cpustate->zero=(t&0xff)==0;
250
 
        cpustate->carry=t>=0x100;
251
 
}
252
 
 
253
 
// p++ sideeffect
254
 
INLINE void sc61860_add_word(sc61860_state *cpustate)
255
 
{
256
 
        int t = READ_RAM(cpustate, cpustate->p) + READ_RAM(cpustate, A), t2;
257
 
        WRITE_RAM(cpustate, cpustate->p, t);
258
 
        cpustate->p++;
259
 
        t2 = READ_RAM(cpustate, cpustate->p) + READ_RAM(cpustate, B);
260
 
        if (t>=0x100) t2++;
261
 
        WRITE_RAM(cpustate, cpustate->p, t2);
262
 
        cpustate->zero=(t2&0xff)==0 &&(t&0xff)==0;
263
 
        cpustate->carry=t2>=0x100;
264
 
}
265
 
 
266
 
 
267
 
INLINE void sc61860_sub(sc61860_state *cpustate, int reg, UINT8 value)
268
 
{
269
 
        int t = READ_RAM(cpustate, reg) - value;
270
 
        WRITE_RAM(cpustate, reg, t);
271
 
        cpustate->zero=(t&0xff)==0;
272
 
        cpustate->carry=t<0;
273
 
}
274
 
 
275
 
INLINE void sc61860_sub_carry(sc61860_state *cpustate)
276
 
{
277
 
        int t = READ_RAM(cpustate, cpustate->p) - READ_RAM(cpustate, A);
278
 
        if (cpustate->carry) t--;
279
 
        WRITE_RAM(cpustate, cpustate->p, t);
280
 
        cpustate->zero=(t&0xff)==0;
281
 
        cpustate->carry=t<0;
282
 
}
283
 
 
284
 
 
285
 
// p++ sideeffect
286
 
INLINE void sc61860_sub_word(sc61860_state *cpustate)
287
 
{
288
 
        int t = READ_RAM(cpustate, cpustate->p) - READ_RAM(cpustate, A), t2;
289
 
        WRITE_RAM(cpustate, cpustate->p, t);
290
 
        cpustate->p++;
291
 
        t2 = READ_RAM(cpustate, cpustate->p) - READ_RAM(cpustate, B);
292
 
        if (t<0) t2--;
293
 
        WRITE_RAM(cpustate, cpustate->p, t2);
294
 
        cpustate->zero=(t2&0xff)==0 && (t&0xff)==0;
295
 
        cpustate->carry=t2<0;
296
 
}
297
 
 
298
 
INLINE void sc61860_cmp(sc61860_state *cpustate, int reg, UINT8 value)
299
 
{
300
 
        int t = READ_RAM(cpustate, reg) - value;
301
 
        cpustate->zero=t==0;
302
 
        cpustate->carry=t<0;
303
 
}
304
 
 
305
 
INLINE void sc61860_pop(sc61860_state *cpustate)
306
 
{
307
 
        WRITE_RAM(cpustate, A, POP(cpustate));
308
 
}
309
 
 
310
 
INLINE void sc61860_push(sc61860_state *cpustate)
311
 
{
312
 
        PUSH(cpustate, READ_RAM(cpustate, A));
313
 
}
314
 
 
315
 
INLINE void sc61860_prepare_table_call(sc61860_state *cpustate)
316
 
{
317
 
        int adr;
318
 
        cpustate->h=READ_OP(cpustate);
319
 
        adr=READ_OP_ARG_WORD(cpustate);
320
 
        PUSH(cpustate, adr>>8);
321
 
        PUSH(cpustate, adr&0xff);
322
 
}
323
 
 
324
 
INLINE void sc61860_execute_table_call(sc61860_state *cpustate)
325
 
{
326
 
        int i, v, adr;
327
 
        for (i=0; i<cpustate->h; i++) {
328
 
                v=READ_OP(cpustate);
329
 
                adr=READ_OP_ARG_WORD(cpustate);
330
 
                cpustate->zero=v==READ_RAM(cpustate, A);
331
 
                if (cpustate->zero) {
332
 
                        cpustate->pc=adr;
333
 
                        return;
334
 
                }
335
 
        }
336
 
        cpustate->pc=READ_OP_ARG_WORD(cpustate);
337
 
}
338
 
 
339
 
 
340
 
INLINE void sc61860_call(sc61860_state *cpustate, UINT16 adr)
341
 
{
342
 
        PUSH(cpustate, cpustate->pc>>8);
343
 
        PUSH(cpustate, cpustate->pc&0xff);
344
 
        cpustate->pc=adr;
345
 
}
346
 
 
347
 
INLINE void sc61860_return(sc61860_state *cpustate)
348
 
{
349
 
        UINT16 t=POP(cpustate);
350
 
        t|=POP(cpustate)<<8;
351
 
        cpustate->pc=t;
352
 
}
353
 
 
354
 
INLINE void sc61860_jump(sc61860_state *cpustate, int yes)
355
 
{
356
 
        UINT16 adr = READ_OP_ARG_WORD(cpustate);
357
 
        if (yes) {
358
 
                cpustate->pc=adr;
359
 
        }
360
 
}
361
 
 
362
 
INLINE void sc61860_jump_rel_plus(sc61860_state *cpustate, int yes)
363
 
{
364
 
        UINT16 adr = cpustate->pc + READ_OP_ARG(cpustate);
365
 
        if (yes) {
366
 
                cpustate->pc=adr;
367
 
                cpustate->icount-=3;
368
 
        }
369
 
}
370
 
 
371
 
INLINE void sc61860_jump_rel_minus(sc61860_state *cpustate, int yes)
372
 
{
373
 
        UINT16 adr = cpustate->pc - READ_OP_ARG(cpustate);
374
 
        if (yes) {
375
 
                cpustate->pc=adr;
376
 
                cpustate->icount-=3;
377
 
        }
378
 
}
379
 
 
380
 
INLINE void sc61860_loop(sc61860_state *cpustate)
381
 
{
382
 
        UINT16 adr = cpustate->pc - READ_OP_ARG(cpustate);
383
 
        UINT8 t = READ_RAM(cpustate, cpustate->r) - 1;
384
 
        WRITE_RAM(cpustate, cpustate->r, t);
385
 
        cpustate->zero=t==0;
386
 
        cpustate->carry=t==0xff;
387
 
        if (!cpustate->carry) {
388
 
                cpustate->pc=adr;
389
 
                adr=POP(cpustate);
390
 
                cpustate->icount-=3;
391
 
        }
392
 
}
393
 
 
394
 
INLINE void sc61860_leave(sc61860_state *cpustate)
395
 
{
396
 
        WRITE_RAM(cpustate, cpustate->r, 0);
397
 
}
398
 
 
399
 
INLINE void sc61860_wait(sc61860_state *cpustate)
400
 
{
401
 
        int t=READ_OP(cpustate);
402
 
        cpustate->icount-=t;
403
 
        cpustate->icount-=t;
404
 
        cpustate->icount-=3;
405
 
}
406
 
 
407
 
INLINE void sc61860_set_carry(sc61860_state *cpustate)
408
 
{
409
 
        cpustate->carry=1;
410
 
        cpustate->zero=1;
411
 
}
412
 
 
413
 
INLINE void sc61860_reset_carry(sc61860_state *cpustate)
414
 
{
415
 
        cpustate->carry=0;
416
 
        cpustate->zero=1;
417
 
}
418
 
 
419
 
INLINE void sc61860_out_a(sc61860_state *cpustate)
420
 
{
421
 
        cpustate->q=IA;
422
 
        if (cpustate->config&&cpustate->config->outa)
423
 
                cpustate->config->outa(cpustate->device, READ_RAM(cpustate, IA));
424
 
}
425
 
 
426
 
INLINE void sc61860_out_b(sc61860_state *cpustate)
427
 
{
428
 
        cpustate->q=IB;
429
 
        if (cpustate->config&&cpustate->config->outb)
430
 
                cpustate->config->outb(cpustate->device, READ_RAM(cpustate, IB));
431
 
}
432
 
 
433
 
INLINE void sc61860_out_f(sc61860_state *cpustate)
434
 
{
435
 
        cpustate->q=F0;
436
 
        /*READ_RAM(cpustate, F0); */
437
 
}
438
 
 
439
 
 
440
 
/*   c0 display on
441
 
   c1 counter reset
442
 
   c2 cpu halt
443
 
   c3 computer off
444
 
   c4 beeper frequency (1 4khz, 0 2khz), or (c5=0) membran pos1/pos2
445
 
   c5 beeper on
446
 
   c6 beeper steuerung*/
447
 
INLINE void sc61860_out_c(sc61860_state *cpustate)
448
 
{
449
 
        cpustate->q=C;
450
 
        if (cpustate->config&&cpustate->config->outc)
451
 
                cpustate->config->outc(cpustate->device, READ_RAM(cpustate, C));
452
 
        cpustate->c = READ_RAM(cpustate, C);
453
 
}
454
 
 
455
 
INLINE void sc61860_in_a(sc61860_state *cpustate)
456
 
{
457
 
        int data=0;
458
 
        if (cpustate->config&&cpustate->config->ina) data=cpustate->config->ina(cpustate->device);
459
 
        WRITE_RAM(cpustate, A, data);
460
 
        cpustate->zero=data==0;
461
 
}
462
 
 
463
 
INLINE void sc61860_in_b(sc61860_state *cpustate)
464
 
{
465
 
        int data=0;
466
 
        if (cpustate->config&&cpustate->config->inb) data=cpustate->config->inb(cpustate->device);
467
 
        WRITE_RAM(cpustate, A, data);
468
 
        cpustate->zero=data==0;
469
 
}
470
 
 
471
 
/* 0 systemclock 512ms
472
 
   1 systemclock 2ms
473
 
   2 ?
474
 
   3 brk/on key
475
 
   4 ?
476
 
   5 ?
477
 
   6 reset
478
 
   7 cassette input */
479
 
INLINE void sc61860_test_special(sc61860_state *cpustate)
480
 
{
481
 
        int t=0;
482
 
        if (cpustate->timer.t512ms) t|=1;
483
 
        if (cpustate->timer.t2ms) t|=2;
484
 
        if (cpustate->config&&cpustate->config->brk&&cpustate->config->brk(cpustate->device)) t|=8;
485
 
        if (cpustate->config&&cpustate->config->reset&&cpustate->config->reset(cpustate->device)) t|=0x40;
486
 
        if (cpustate->config&&cpustate->config->x&&cpustate->config->x(cpustate->device)) t|=0x80;
487
 
 
488
 
        cpustate->zero=(t&READ_OP(cpustate))==0;
489
 
}
490
 
 
491
 
/************************************************************************************
492
 
 "string" operations
493
 
***********************************************************************************/
494
 
 
495
 
// p-=I+1 sideeffect
496
 
INLINE void sc61860_add_bcd_a(sc61860_state *cpustate)
497
 
{
498
 
        UINT8 help = READ_RAM(cpustate, A);
499
 
        int i, hlp, hlp1 = 0;
500
 
        cpustate->zero=1;
501
 
        for (i=0; i <= READ_RAM(cpustate, I); i++) {
502
 
                int t = READ_RAM(cpustate, cpustate->p);
503
 
                hlp1 = (t & 0x0f) + (help & 0x0f) + hlp1;
504
 
                if (hlp1 > 9) { hlp = hlp1 - 0x0a; hlp1 = 0x10; }
505
 
                else { hlp = hlp1; hlp1 = 0x00; }
506
 
                hlp1 = (t & 0xf0) + (help & 0xf0) + hlp1;
507
 
                if (hlp1 > 0x90) { WRITE_RAM(cpustate, cpustate->p, hlp1 - 0xa0 + hlp); hlp1 = 1; }
508
 
                else { WRITE_RAM(cpustate, cpustate->p, hlp1 + hlp); hlp1 = 0; }
509
 
                if ( READ_RAM(cpustate, cpustate->p) != 0 ) cpustate->zero = 0;
510
 
                cpustate->p--;
511
 
                help = 0;
512
 
        }
513
 
        cpustate->carry= ( hlp1 ) ? 1 : 0;
514
 
        cpustate->icount-=3*(READ_RAM(cpustate, I)+1);
515
 
}
516
 
 
517
 
 
518
 
// p-=I+1, q-=I+2 sideeffect
519
 
INLINE void sc61860_add_bcd(sc61860_state *cpustate)
520
 
{
521
 
        int i, hlp, hlp1 = 0;
522
 
        cpustate->zero=1;
523
 
        for (i=0; i <= READ_RAM(cpustate, I); i++) {
524
 
                int t = READ_RAM(cpustate, cpustate->p);
525
 
                int t2 = READ_RAM(cpustate, cpustate->q);
526
 
                hlp1 = (t & 0x0f) + (t2 & 0x0f) + hlp1;
527
 
                if (hlp1 > 9) { hlp = hlp1 - 0x0a; hlp1 = 0x10; }
528
 
                else { hlp = hlp1; hlp1 = 0x00; }
529
 
                hlp1 = (t & 0xf0) + (t2 & 0xf0) + hlp1;
530
 
                cpustate->q--;
531
 
                if (hlp1 > 0x90) { WRITE_RAM(cpustate, cpustate->p, hlp1 - 0xa0 + hlp); hlp1 = 1; }
532
 
                else { WRITE_RAM(cpustate, cpustate->p, hlp1 + hlp); hlp1 = 0; }
533
 
                if ( READ_RAM(cpustate, cpustate->p) != 0 ) cpustate->zero = 0;
534
 
                cpustate->p--;
535
 
        }
536
 
        cpustate->carry= ( hlp1 ) ? 1 : 0;
537
 
        cpustate->icount-=3*(READ_RAM(cpustate, I)+1);
538
 
        cpustate->q--;
539
 
}
540
 
 
541
 
 
542
 
// p-=I+1 sideeffect
543
 
INLINE void sc61860_sub_bcd_a(sc61860_state *cpustate)
544
 
{
545
 
        UINT8 help = READ_RAM(cpustate, A);
546
 
        int i, hlp, hlp1 = 0;
547
 
        cpustate->zero=1;
548
 
        for (i=0; i <= READ_RAM(cpustate, I); i++) {
549
 
                int t = READ_RAM(cpustate, cpustate->p);
550
 
                hlp1 = (t & 0x0f) - (help & 0x0f) - hlp1;
551
 
                if ( hlp1 < 0 ) { hlp = hlp1 + 0x0a; hlp1 = 0x10; }
552
 
                else { hlp = hlp1; hlp1 = 0x00; }
553
 
                hlp1 = (t & 0xf0) - (help & 0xf0) - hlp1;
554
 
                if ( hlp1 < 0 ) { WRITE_RAM(cpustate, cpustate->p, hlp1 + 0xa0 + hlp); hlp1 = 1; }
555
 
                else { WRITE_RAM(cpustate, cpustate->p, hlp1 + hlp); hlp1 = 0; }
556
 
                if ( READ_RAM(cpustate, cpustate->p) != 0 ) cpustate->zero = 0;
557
 
                cpustate->p--;
558
 
                help = 0;
559
 
        }
560
 
        cpustate->carry= ( hlp1 ) ? 1 : 0;
561
 
        cpustate->icount-=3*(READ_RAM(cpustate, I)+1);
562
 
}
563
 
 
564
 
 
565
 
// p-=I+1, q-=I+2 sideeffect
566
 
INLINE void sc61860_sub_bcd(sc61860_state *cpustate)
567
 
{
568
 
        int i, hlp, hlp1 = 0;
569
 
        cpustate->zero=1;
570
 
        for (i=0; i <= READ_RAM(cpustate, I); i++) {
571
 
                int t = READ_RAM(cpustate, cpustate->p);
572
 
                int t2 = READ_RAM(cpustate, cpustate->q);
573
 
                hlp1 = (t & 0x0f) - (t2 & 0x0f) - hlp1;
574
 
                if ( hlp1 < 0 ) { hlp = hlp1 + 0x0a; hlp1 = 0x10; }
575
 
                else { hlp = hlp1; hlp1 = 0x00; }
576
 
                hlp1 = (t & 0xf0) - (t2 & 0xf0) - hlp1;
577
 
                cpustate->q--;
578
 
                if ( hlp1 < 0 ) { WRITE_RAM(cpustate, cpustate->p, hlp1 + 0xa0 + hlp); hlp1 = 1; }
579
 
                else { WRITE_RAM(cpustate, cpustate->p, hlp1 + hlp); hlp1 = 0; }
580
 
                if ( READ_RAM(cpustate, cpustate->p) != 0 ) cpustate->zero = 0;
581
 
                cpustate->p--;
582
 
        }
583
 
        cpustate->carry= ( hlp1 ) ? 1 : 0;
584
 
        cpustate->icount-=3*(READ_RAM(cpustate, I)+1);
585
 
        cpustate->q--;
586
 
}
587
 
 
588
 
/* side effect p-i-1 -> p correct! */
589
 
INLINE void sc61860_shift_left_nibble(sc61860_state *cpustate)
590
 
{
591
 
        int i,t=0;
592
 
        for (i=0; i<=READ_RAM(cpustate, I); i++) {
593
 
                t |= READ_RAM(cpustate, cpustate->p)<<4;
594
 
                WRITE_RAM(cpustate, cpustate->p, t);
595
 
                cpustate->p--;
596
 
                t>>=8;
597
 
                cpustate->icount--;
598
 
        }
599
 
}
600
 
 
601
 
/* side effect p+i+1 -> p correct! */
602
 
INLINE void sc61860_shift_right_nibble(sc61860_state *cpustate)
603
 
{
604
 
        int i,t=0;
605
 
        for (i=0; i<=READ_RAM(cpustate, I); i++) {
606
 
                t |= READ_RAM(cpustate, cpustate->p);
607
 
                WRITE_RAM(cpustate, cpustate->p, t>>4);
608
 
                cpustate->p++;
609
 
                t=(t<<8)&0xf00;
610
 
                cpustate->icount--;
611
 
        }
612
 
}
613
 
 
614
 
// q=reg+1 sideeffect
615
 
INLINE void sc61860_inc_load_dp(sc61860_state *cpustate, int reg)
616
 
{
617
 
        UINT8 t = READ_RAM(cpustate, reg) + 1;
618
 
        UINT8 t2 = READ_RAM(cpustate, reg + 1);
619
 
        WRITE_RAM(cpustate, reg, t);
620
 
        if (t == 0) { t2++; WRITE_RAM(cpustate, reg + 1, t2); }
621
 
        cpustate->dp=t|(t2<<8);
622
 
        cpustate->q=reg+1;
623
 
}
624
 
 
625
 
// q=reg+1 sideeffect
626
 
INLINE void sc61860_dec_load_dp(sc61860_state *cpustate, int reg)
627
 
{
628
 
        UINT8 t = READ_RAM(cpustate, reg) - 1;
629
 
        UINT8 t2 = READ_RAM(cpustate, reg + 1);
630
 
        WRITE_RAM(cpustate, reg, t);
631
 
        if (t == 0xff) { t2--; WRITE_RAM(cpustate, reg + 1, t2); }
632
 
        cpustate->dp=t|(t2<<8);
633
 
        cpustate->q=reg+1;
634
 
}
635
 
 
636
 
// q=XH sideeffect
637
 
INLINE void sc61860_inc_load_dp_load(sc61860_state *cpustate)
638
 
{
639
 
        sc61860_inc_load_dp(cpustate, XL);
640
 
        WRITE_RAM(cpustate, A, READ_BYTE(cpustate, cpustate->dp));
641
 
}
642
 
 
643
 
// q=XH sideeffect
644
 
INLINE void sc61860_dec_load_dp_load(sc61860_state *cpustate)
645
 
{
646
 
        sc61860_dec_load_dp(cpustate, XL);
647
 
        WRITE_RAM(cpustate, A, READ_BYTE(cpustate, cpustate->dp));
648
 
}
649
 
 
650
 
// q=YH sideeffect
651
 
INLINE void sc61860_inc_load_dp_store(sc61860_state *cpustate)
652
 
{
653
 
        sc61860_inc_load_dp(cpustate, YL);
654
 
        WRITE_BYTE(cpustate, cpustate->dp, READ_RAM(cpustate, A));
655
 
}
656
 
 
657
 
// q=YH sideeffect
658
 
INLINE void sc61860_dec_load_dp_store(sc61860_state *cpustate)
659
 
{
660
 
        sc61860_dec_load_dp(cpustate, YL);
661
 
        WRITE_BYTE(cpustate, cpustate->dp, READ_RAM(cpustate, A));
662
 
}
663
 
 
664
 
INLINE void sc61860_fill(sc61860_state *cpustate)
665
 
{
666
 
        int i;
667
 
        for (i=0;i<=READ_RAM(cpustate, I);i++) {
668
 
                WRITE_RAM(cpustate, cpustate->p, READ_RAM(cpustate, A)); /* could be overwritten? */
669
 
                cpustate->p++;
670
 
                cpustate->icount--;
671
 
        }
672
 
}
673
 
 
674
 
INLINE void sc61860_fill_ext(sc61860_state *cpustate)
675
 
{
676
 
        int i;
677
 
        for (i=0;i<=READ_RAM(cpustate, I);i++) {
678
 
                WRITE_BYTE(cpustate, cpustate->dp, READ_RAM(cpustate, A));
679
 
                if (i!=READ_RAM(cpustate, I)) cpustate->dp++;
680
 
                cpustate->icount-=3;
681
 
        }
682
 
}
683
 
 
684
 
// p+=count+1, q+=count+1 sideeffects
685
 
INLINE void sc61860_copy(sc61860_state *cpustate, int count)
686
 
{
687
 
        int i;
688
 
        for (i=0; i<=count; i++) {
689
 
                WRITE_RAM(cpustate, cpustate->p, READ_RAM(cpustate, cpustate->q));
690
 
                cpustate->p++;
691
 
                cpustate->q++;
692
 
                cpustate->icount-=2;
693
 
        }
694
 
 
695
 
}
696
 
 
697
 
// p+=count+1, dp+=count sideeffects
698
 
INLINE void sc61860_copy_ext(sc61860_state *cpustate, int count)
699
 
{
700
 
        int i;
701
 
        for (i=0; i<=count; i++) {
702
 
                WRITE_RAM(cpustate, cpustate->p, READ_BYTE(cpustate, cpustate->dp));
703
 
                cpustate->p++;
704
 
                if (i!=count) cpustate->dp++;
705
 
                cpustate->icount-=4;
706
 
        }
707
 
}
708
 
 
709
 
INLINE void sc61860_copy_int(sc61860_state *cpustate, int count)
710
 
{
711
 
        int i;
712
 
        for (i=0; i<=count; i++) {
713
 
                UINT8 t = READ_BYTE(cpustate, (READ_RAM(cpustate, A)|(READ_RAM(cpustate, B)<<8))); /* internal rom! */
714
 
                WRITE_RAM(cpustate, cpustate->p, t);
715
 
                cpustate->p++;
716
 
                if (i!=count) {
717
 
                        t = READ_RAM(cpustate, A) + 1;
718
 
                        WRITE_RAM(cpustate, A, t);
719
 
                        if (t==0) {
720
 
                                t = READ_RAM(cpustate, B) + 1;
721
 
                                WRITE_RAM(cpustate, B, t);
722
 
                        }
723
 
                }
724
 
                cpustate->icount-=4;
725
 
        }
726
 
}
727
 
 
728
 
INLINE void sc61860_exchange(sc61860_state *cpustate, int count)
729
 
{
730
 
        int i;
731
 
        UINT8 t;
732
 
        for (i=0; i<=count; i++) {
733
 
                t = READ_RAM(cpustate, cpustate->p);
734
 
                WRITE_RAM(cpustate, cpustate->p, READ_RAM(cpustate, cpustate->q));
735
 
                WRITE_RAM(cpustate, cpustate->q, t);
736
 
                cpustate->p++;
737
 
                cpustate->q++;
738
 
                cpustate->icount-=3;
739
 
        }
740
 
}
741
 
 
742
 
INLINE void sc61860_exchange_ext(sc61860_state *cpustate, int count)
743
 
{
744
 
        int i;
745
 
        UINT8 t;
746
 
        for (i=0; i<=count; i++) {
747
 
                t = READ_RAM(cpustate, cpustate->p);
748
 
                WRITE_RAM(cpustate, cpustate->p, READ_BYTE(cpustate, cpustate->dp));
749
 
                cpustate->p++;
750
 
                WRITE_BYTE(cpustate, cpustate->dp, t);
751
 
                if (i!=count) cpustate->dp++;
752
 
                cpustate->icount-=6;
753
 
        }
754
 
}
755
 
 
756
 
// undocumented
757
 
// only 1 opcode working in pc1403
758
 
// both opcodes working in pc1350
759
 
INLINE void sc61860_wait_x(sc61860_state *cpustate, int level)
760
 
{
761
 
        int c;
762
 
        cpustate->zero=level;
763
 
 
764
 
        if (cpustate->config&&cpustate->config->x) {
765
 
                for (c=READ_RAM(cpustate, I); c>=0; c--) {
766
 
                        UINT8 t = (READ_RAM(cpustate, cpustate->p)+1)&0x7f;
767
 
                        WRITE_RAM(cpustate, cpustate->p, t);
768
 
                        cpustate->zero=cpustate->config->x(cpustate->device);
769
 
                        cpustate->icount-=4;
770
 
                        if (level != cpustate->zero) break;
771
 
                }
772
 
        }
773
 
}