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Viewing changes to mess/src/mame/video/vertigo.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Jordi Mallach, Emmanuel Kasper
  • Date: 2011-12-19 22:56:27 UTC
  • mfrom: (0.1.2)
  • Revision ID: package-import@ubuntu.com-20111219225627-ub5oga1oys4ogqzm
Tags: 0.144-1
http://bugs.debian.org/651538
[ Jordi Mallach ]
* Fix syntax errors in DEP5 copyright file (lintian).
* Use a versioned copyright Format specification field.
* Update Vcs-* URLs.
* Move transitional packages to the new metapackages section, and make
  them priority extra.
* Remove references to GNU/Linux and MESS sources from copyright.
* Add build variables for s390x.
* Use .xz tarballs as it cuts 4MB for the upstream sources.
* Add nplayers.ini as a patch. Update copyright file to add CC-BY-SA-3.0.

[ Emmanuel Kasper ]
* New upstream release. Closes: #651538.
* Add Free Desktop compliant png icons of various sizes taken from
  the hydroxygen iconset
* Mess is now built from a new source package, to avoid possible source
  incompatibilities between mame and the mess overlay.
* Mame-tools are not built from the mame source package anymore, but
  from the mess source package

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mess/src/mame/video/vertigo.c
1
 
/*************************************************************************
2
 
 
3
 
 Exidy Vertigo hardware
4
 
 
5
 
 The Vertigo vector CPU consists of four AMD 2901 bit slice
6
 
 processors, logic to control microcode program flow and a digital
7
 
 vector generator. The microcode for the bit slice CPUs is stored in 13
8
 
 bipolar proms for a total of 512 52bit wide micro instructions. The
9
 
 microcode not only crontrols the 2901s but also loading and storing
10
 
 of operands and results, program flow control and vector generation.
11
 
 
12
 
 +----+----+----+----+----+----+-------+-----+-----+------+-----+----+---+
13
 
 |VUC |VUC |VUC |VUC |VUC |VUC |  VUC  | VUC | VUC | VUC  | VUC |VUC |VUC| labels
14
 
 | 10 | 13 | 9  | 8  | 7  | 6  |   5   |  12 |  11 |  2   |  1  | 4  | 3 |
15
 
 +----+----+----+----+----+----+-------+-----+-----+------+-----+----+---+
16
 
 |    |    |    |    |    |    |       |     |     |      |     |PR5/|R5/| schematics
17
 
 |J5/4|G5/1|K5/5|L5/6|M5/7|N5/8| P5/9  |H5/2 |HJ5/3|S5/12 |T5/13| 10 |11 |
18
 
 +----+----+----+----+----+----+-------+-----+-----+------+-----+----+---+
19
 
 55 44|4444|4444|3333|3333|3322|2 2 2 2|2 222|11 11|1 1 11|110 0|0000|0000
20
 
 21 98|7654|3210|9876|5432|1098|7 6 5 4|3 210|98 76|5 4 32|109 8|7654|3210
21
 
 
22
 
    xx|xxxx|aaaa|bbbb|iiii|iiii|i c m r|r ooo|ii oo|  j jj|jjj m|mmmm|mmmm
23
 
    54|3210|3210|3210|8765|4321|0 n r s|w fff|ff aa|  p 43|210 a|aaaa|aaaa
24
 
                                    e e|r 210|10 10|  o   |    8|7654|3210
25
 
                                    q l i             s
26
 
                                        t
27
 
                                        e
28
 
 x:    address for 64 words of 16 bit wide SRAM
29
 
 a:    A register index
30
 
 b:    B register index
31
 
 i:    2901 instruction
32
 
 cn:   carry bit
33
 
 mreq, rsel, rwrite: signals for memory access
34
 
 of:   vector generator
35
 
 if:   vector RAM/ROM data select
36
 
 oa:   vector RAM/ROM address select
37
 
 jpos: jump condition inverted
38
 
 j:    jump condition and type
39
 
 m:    jump address
40
 
 
41
 
 Variables, enums and defines are named as in the schematics (pp. 6, 7)
42
 
 where possible.
43
 
 
44
 
*************************************************************************/
45
 
 
46
 
#include "emu.h"
47
 
#include "profiler.h"
48
 
#include "video/vector.h"
49
 
#include "includes/vertigo.h"
50
 
 
51
 
 
52
 
/*************************************
53
 
 *
54
 
 *  Macros and enums
55
 
 *
56
 
 *************************************/
57
 
 
58
 
#define V_ADDPOINT(m,h,v,c,i) \
59
 
        vector_add_point (m, ((h) & 0x7ff) << 14, (0x6ff - ((v) & 0x7ff)) << 14, VECTOR_COLOR444(c), (i))
60
 
 
61
 
#define ADD(r,s,c)      (((r)  + (s) + (c)) & 0xffff)
62
 
#define SUBR(r,s,c) ((~(r) + (s) + (c)) & 0xffff)
63
 
#define SUBS(r,s,c) (((r) + ~(s) + (c)) & 0xffff)
64
 
#define OR(r,s)         ((r) | (s))
65
 
#define AND(r,s)        ((r) & (s))
66
 
#define NOTRS(r,s)      (~(r) & (s))
67
 
#define EXOR(r,s)       ((r) ^ (s))
68
 
#define EXNOR(r,s)      (~((r) ^ (s)))
69
 
 
70
 
/* values for MC_DST */
71
 
enum {
72
 
        QREG = 0,
73
 
        NOP,
74
 
        RAMA,
75
 
        RAMF,
76
 
        RAMQD,
77
 
        RAMD,
78
 
        RAMQU,
79
 
        RAMU
80
 
};
81
 
 
82
 
/* values for MC_IF */
83
 
enum {
84
 
        S_ROMDE = 0,
85
 
        S_RAMDE
86
 
};
87
 
 
88
 
/* values for MC_OA */
89
 
enum {
90
 
        S_SREG = 0,
91
 
        S_ROMA,
92
 
        S_RAMD
93
 
};
94
 
 
95
 
/* values for MC_JMP */
96
 
enum {
97
 
        S_JBK = 0,
98
 
        S_CALL,
99
 
        S_OPT,
100
 
        S_RETURN
101
 
};
102
 
 
103
 
/* values for MC_JCON */
104
 
enum {
105
 
        S_ALWAYS = 0,
106
 
        S_MSB,
107
 
        S_FEQ0,
108
 
        S_Y10,
109
 
        S_VFIN,
110
 
        S_FPOS,
111
 
        S_INTL4
112
 
};
113
 
 
114
 
 
115
 
/*************************************
116
 
 *
117
 
 *  Vector processor initialization
118
 
 *
119
 
 *************************************/
120
 
 
121
 
void vertigo_vproc_init(running_machine &machine)
122
 
{
123
 
        vertigo_state *state = machine.driver_data<vertigo_state>();
124
 
        state_save_register_item_array(machine, "vector_proc", NULL, 0, state->m_vs.sram);
125
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vs.ramlatch);
126
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vs.rom_adr);
127
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vs.pc);
128
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vs.ret);
129
 
 
130
 
        state_save_register_item_array(machine, "vector_proc", NULL, 0, state->m_bsp.ram);
131
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_bsp.d);
132
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_bsp.q);
133
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_bsp.f);
134
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_bsp.y);
135
 
 
136
 
        state->m_vgen.set_machine(machine);
137
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.sreg);
138
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.l1);
139
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.l2);
140
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.c_v);
141
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.c_h);
142
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.c_l);
143
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.adder_s);
144
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.adder_a);
145
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.color);
146
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.intensity);
147
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.brez);
148
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.vfin);
149
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.hud1);
150
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.hud2);
151
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.vud1);
152
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.vud2);
153
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.hc1);
154
 
        state_save_register_item(machine, "vector_proc", NULL, 0, state->m_vgen.ven);
155
 
}
156
 
 
157
 
 
158
 
void vertigo_vproc_reset(running_machine &machine)
159
 
{
160
 
        vertigo_state *state = machine.driver_data<vertigo_state>();
161
 
        int i;
162
 
        UINT64 *mcode;
163
 
 
164
 
        state->m_vectorrom = (UINT16 *)machine.region("user1")->base();
165
 
        mcode = (UINT64 *)machine.region("proms")->base();
166
 
 
167
 
        /* Decode microcode */
168
 
        for (i = 0; i < MC_LENGTH; i++)
169
 
        {
170
 
                state->m_mc[i].x = (mcode[i] >> 44) & 0x3f;
171
 
                state->m_mc[i].a = (mcode[i] >> 40) & 0xf;
172
 
                state->m_mc[i].b = (mcode[i] >> 36) & 0xf;
173
 
                state->m_mc[i].inst = (mcode[i] >> 27) & 077;
174
 
                state->m_mc[i].dest = (mcode[i] >> 33) & 07;
175
 
                state->m_mc[i].cn = (mcode[i] >> 26) & 0x1;
176
 
                state->m_mc[i].mreq = (mcode[i] >> 25) & 0x1;
177
 
                state->m_mc[i].rwrite = (mcode[i] >> 23) & 0x1;
178
 
                state->m_mc[i].rsel = state->m_mc[i].rwrite & ((mcode[i] >> 24) & 0x1);
179
 
                state->m_mc[i].of =  (mcode[i] >> 20) & 0x7;
180
 
                state->m_mc[i].iif = (mcode[i] >> 18) & 0x3;
181
 
                state->m_mc[i].oa = (mcode[i] >> 16) & 0x3;
182
 
                state->m_mc[i].jpos = (mcode[i] >> 14) & 0x1;
183
 
                state->m_mc[i].jmp = (mcode[i] >> 12) & 0x3;
184
 
                state->m_mc[i].jcon = (mcode[i] >> 9) & 0x7;
185
 
                state->m_mc[i].ma = mcode[i] & 0x1ff;
186
 
        }
187
 
 
188
 
        memset(&state->m_vs, 0, sizeof(state->m_vs));
189
 
        memset(&state->m_bsp, 0, sizeof(state->m_bsp));
190
 
        memset(&state->m_vgen, 0, sizeof(state->m_vgen));
191
 
}
192
 
 
193
 
 
194
 
/********************************************
195
 
 *
196
 
 *  4 x AM2901 bit slice processors
197
 
 *  Q3 and IN3 are hardwired
198
 
 *
199
 
 ********************************************/
200
 
 
201
 
static void am2901x4 (am2901 *bsp, microcode *mc)
202
 
{
203
 
        switch (mc->inst)
204
 
        {
205
 
        case 000: bsp->f = ADD(bsp->ram[mc->a], bsp->q, mc->cn); break;
206
 
        case 001: bsp->f = ADD(bsp->ram[mc->a], bsp->ram[mc->b], mc->cn); break;
207
 
        case 002: bsp->f = ADD(0, bsp->q, mc->cn); break;
208
 
        case 003: bsp->f = ADD(0, bsp->ram[mc->b], mc->cn); break;
209
 
        case 004: bsp->f = ADD(0, bsp->ram[mc->a], mc->cn); break;
210
 
        case 005: bsp->f = ADD(bsp->d, bsp->ram[mc->a], mc->cn); break;
211
 
        case 006: bsp->f = ADD(bsp->d, bsp->q, mc->cn); break;
212
 
        case 007: bsp->f = ADD(bsp->d, 0, mc->cn); break;
213
 
 
214
 
        case 010: bsp->f = SUBR(bsp->ram[mc->a], bsp->q, mc->cn); break;
215
 
        case 011: bsp->f = SUBR(bsp->ram[mc->a], bsp->ram[mc->b], mc->cn); break;
216
 
        case 012: bsp->f = SUBR(0, bsp->q, mc->cn); break;
217
 
        case 013: bsp->f = SUBR(0, bsp->ram[mc->b], mc->cn); break;
218
 
        case 014: bsp->f = SUBR(0, bsp->ram[mc->a], mc->cn); break;
219
 
        case 015: bsp->f = SUBR(bsp->d, bsp->ram[mc->a], mc->cn); break;
220
 
        case 016: bsp->f = SUBR(bsp->d, bsp->q, mc->cn); break;
221
 
        case 017: bsp->f = SUBR(bsp->d, 0, mc->cn); break;
222
 
 
223
 
        case 020: bsp->f = SUBS(bsp->ram[mc->a], bsp->q, mc->cn); break;
224
 
        case 021: bsp->f = SUBS(bsp->ram[mc->a], bsp->ram[mc->b], mc->cn); break;
225
 
        case 022: bsp->f = SUBS(0, bsp->q, mc->cn); break;
226
 
        case 023: bsp->f = SUBS(0, bsp->ram[mc->b], mc->cn); break;
227
 
        case 024: bsp->f = SUBS(0, bsp->ram[mc->a], mc->cn); break;
228
 
        case 025: bsp->f = SUBS(bsp->d, bsp->ram[mc->a], mc->cn); break;
229
 
        case 026: bsp->f = SUBS(bsp->d, bsp->q, mc->cn); break;
230
 
        case 027: bsp->f = SUBS(bsp->d, 0, mc->cn); break;
231
 
 
232
 
        case 030: bsp->f = OR(bsp->ram[mc->a], bsp->q); break;
233
 
        case 031: bsp->f = OR(bsp->ram[mc->a], bsp->ram[mc->b]); break;
234
 
        case 032: bsp->f = OR(0, bsp->q); break;
235
 
        case 033: bsp->f = OR(0, bsp->ram[mc->b]); break;
236
 
        case 034: bsp->f = OR(0, bsp->ram[mc->a]); break;
237
 
        case 035: bsp->f = OR(bsp->d, bsp->ram[mc->a]); break;
238
 
        case 036: bsp->f = OR(bsp->d, bsp->q); break;
239
 
        case 037: bsp->f = OR(bsp->d, 0); break;
240
 
 
241
 
        case 040: bsp->f = AND(bsp->ram[mc->a], bsp->q); break;
242
 
        case 041: bsp->f = AND(bsp->ram[mc->a], bsp->ram[mc->b]); break;
243
 
        case 042: bsp->f = AND(0, bsp->q); break;
244
 
        case 043: bsp->f = AND(0, bsp->ram[mc->b]); break;
245
 
        case 044: bsp->f = AND(0, bsp->ram[mc->a]); break;
246
 
        case 045: bsp->f = AND(bsp->d, bsp->ram[mc->a]); break;
247
 
        case 046: bsp->f = AND(bsp->d, bsp->q); break;
248
 
        case 047: bsp->f = AND(bsp->d, 0); break;
249
 
 
250
 
        case 050: bsp->f = NOTRS(bsp->ram[mc->a], bsp->q); break;
251
 
        case 051: bsp->f = NOTRS(bsp->ram[mc->a], bsp->ram[mc->b]); break;
252
 
        case 052: bsp->f = NOTRS(0, bsp->q); break;
253
 
        case 053: bsp->f = NOTRS(0, bsp->ram[mc->b]); break;
254
 
        case 054: bsp->f = NOTRS(0, bsp->ram[mc->a]); break;
255
 
        case 055: bsp->f = NOTRS(bsp->d, bsp->ram[mc->a]); break;
256
 
        case 056: bsp->f = NOTRS(bsp->d, bsp->q); break;
257
 
        case 057: bsp->f = NOTRS(bsp->d, 0); break;
258
 
 
259
 
        case 060: bsp->f = EXOR(bsp->ram[mc->a], bsp->q); break;
260
 
        case 061: bsp->f = EXOR(bsp->ram[mc->a], bsp->ram[mc->b]); break;
261
 
        case 062: bsp->f = EXOR(0, bsp->q); break;
262
 
        case 063: bsp->f = EXOR(0, bsp->ram[mc->b]); break;
263
 
        case 064: bsp->f = EXOR(0, bsp->ram[mc->a]); break;
264
 
        case 065: bsp->f = EXOR(bsp->d, bsp->ram[mc->a]); break;
265
 
        case 066: bsp->f = EXOR(bsp->d, bsp->q); break;
266
 
        case 067: bsp->f = EXOR(bsp->d, 0); break;
267
 
 
268
 
        case 070: bsp->f = EXNOR(bsp->ram[mc->a], bsp->q); break;
269
 
        case 071: bsp->f = EXNOR(bsp->ram[mc->a], bsp->ram[mc->b]); break;
270
 
        case 072: bsp->f = EXNOR(0, bsp->q); break;
271
 
        case 073: bsp->f = EXNOR(0, bsp->ram[mc->b]); break;
272
 
        case 074: bsp->f = EXNOR(0, bsp->ram[mc->a]); break;
273
 
        case 075: bsp->f = EXNOR(bsp->d, bsp->ram[mc->a]); break;
274
 
        case 076: bsp->f = EXNOR(bsp->d, bsp->q); break;
275
 
        case 077: bsp->f = EXNOR(bsp->d, 0); break;
276
 
        }
277
 
 
278
 
        switch (mc->dest)
279
 
        {
280
 
        case QREG:
281
 
                bsp->q = bsp->f;
282
 
                bsp->y = bsp->f;
283
 
                break;
284
 
        case NOP:
285
 
                bsp->y = bsp->f;
286
 
                break;
287
 
        case RAMA:
288
 
                bsp->y = bsp->ram[mc->a];
289
 
                bsp->ram[mc->b] = bsp->f;
290
 
                break;
291
 
        case RAMF:
292
 
                bsp->y = bsp->f;
293
 
                bsp->ram[mc->b] = bsp->f;
294
 
                break;
295
 
        case RAMQD:
296
 
                bsp->y = bsp->f;
297
 
                bsp->q = (bsp->q >> 1) & 0x7fff;                  /* Q3 is low */
298
 
                bsp->ram[mc->b] = (bsp->f >> 1) | 0x8000; /* IN3 is high! */
299
 
                break;
300
 
        case RAMD:
301
 
                bsp->y = bsp->f;
302
 
                bsp->ram[mc->b] = (bsp->f >> 1) | 0x8000; /* IN3 is high! */
303
 
                break;
304
 
        case RAMQU:
305
 
                bsp->y = bsp->f;
306
 
                bsp->ram[mc->b] = (bsp->f << 1) & 0xffff;
307
 
                bsp->q = (bsp->q << 1) & 0xffff;
308
 
                break;
309
 
        case RAMU:
310
 
                bsp->y = bsp->f;
311
 
                bsp->ram[mc->b] = (bsp->f << 1) & 0xffff;
312
 
                break;
313
 
        }
314
 
}
315
 
 
316
 
 
317
 
/********************************************
318
 
 *
319
 
 *  Vector Generator
320
 
 *
321
 
 *  This part of the hardware draws vectors
322
 
 *  under control of the bit slice processors.
323
 
 *  It is just a bunch of counters, latches
324
 
 *  and DACs.
325
 
 *
326
 
 ********************************************/
327
 
 
328
 
static void vertigo_vgen (vector_generator *vg)
329
 
{
330
 
        if (vg->c_l & 0x800)
331
 
        {
332
 
                vg->vfin = 1;
333
 
                vg->c_l = (vg->c_l+1) & 0xfff;
334
 
 
335
 
                if ((vg->c_l & 0x800) == 0)
336
 
                {
337
 
                        vg->brez = 0;
338
 
                        vg->vfin = 0;
339
 
                }
340
 
 
341
 
                if (vg->brez) /* H/V counter enabled */
342
 
                {
343
 
                        /* Depending on MSB of adder only one or both
344
 
               counters are de-/incremented. This is all
345
 
               defined by the shift register which is
346
 
               latched in bits 12-15 of L1/L2.
347
 
            */
348
 
                        if (vg->adder_s & 0x800)
349
 
                        {
350
 
                                if (vg->hc1)
351
 
                                        vg->c_h += vg->hud1? -1: 1;
352
 
                                else
353
 
                                        vg->c_v += vg->vud1? -1: 1;
354
 
                                vg->adder_a = vg->l1;
355
 
                        }
356
 
                        else
357
 
                        {
358
 
                                vg->c_h += vg->hud2? -1: 1;
359
 
                                vg->c_v += vg->vud2? -1: 1;
360
 
                                vg->adder_a = vg->l2;
361
 
                        }
362
 
 
363
 
                        /* H/V counters are 12 bit */
364
 
                        vg->c_v &= 0xfff;
365
 
                        vg->c_h &= 0xfff;
366
 
                }
367
 
 
368
 
                vg->adder_s = (vg->adder_s + vg->adder_a) & 0xfff;
369
 
        }
370
 
 
371
 
        if (vg->brez ^ vg->ven)
372
 
        {
373
 
                if (vg->brez)
374
 
                V_ADDPOINT (vg->machine(), vg->c_h, vg->c_v, 0, 0);
375
 
                else
376
 
                        V_ADDPOINT (vg->machine(), vg->c_h, vg->c_v, vg->color, vg->intensity);
377
 
                vg->ven = vg->brez;
378
 
        }
379
 
}
380
 
 
381
 
/*************************************
382
 
 *
383
 
 *  Vector processor
384
 
 *
385
 
 *************************************/
386
 
 
387
 
void vertigo_vproc(running_machine &machine, int cycles, int irq4)
388
 
{
389
 
        vertigo_state *state = machine.driver_data<vertigo_state>();
390
 
        int jcond;
391
 
        microcode *cmc;
392
 
 
393
 
        if (irq4) vector_clear_list();
394
 
 
395
 
        g_profiler.start(PROFILER_USER1);
396
 
 
397
 
        while (cycles--)
398
 
        {
399
 
                /* Microcode at current PC */
400
 
                cmc = &state->m_mc[state->m_vs.pc];
401
 
 
402
 
                /* Load data */
403
 
                if (cmc->iif == S_RAMDE)
404
 
                {
405
 
                        state->m_bsp.d = state->m_vs.ramlatch;
406
 
                }
407
 
                else if (cmc->iif == S_ROMDE)
408
 
                {
409
 
                        if (state->m_vs.rom_adr < 0x2000)
410
 
                        {
411
 
                                state->m_bsp.d = state->m_vectorram[state->m_vs.rom_adr & 0xfff];
412
 
                        }
413
 
                        else
414
 
                        {
415
 
                                state->m_bsp.d = state->m_vectorrom[state->m_vs.rom_adr & 0x7fff];
416
 
                        }
417
 
                }
418
 
 
419
 
                /* SRAM selected ? */
420
 
                if (cmc->rsel == 0)
421
 
                {
422
 
                        if (cmc->rwrite)
423
 
                        {
424
 
                                state->m_bsp.d = state->m_vs.sram[cmc->x];
425
 
                        }
426
 
                        else
427
 
                        {
428
 
                                /* Data can be transferred between vector ROM/RAM
429
 
                   and SRAM without going through the 2901 */
430
 
                                state->m_vs.sram[cmc->x] = state->m_bsp.d;
431
 
                        }
432
 
                }
433
 
 
434
 
                am2901x4 (&state->m_bsp, cmc);
435
 
 
436
 
                /* Store data */
437
 
                switch (cmc->oa)
438
 
                {
439
 
                case S_RAMD:
440
 
                        state->m_vs.ramlatch = state->m_bsp.y;
441
 
                        if (cmc->iif==S_RAMDE && (cmc->rsel == 0) && (cmc->rwrite == 0))
442
 
                                state->m_vs.sram[cmc->x] = state->m_vs.ramlatch;
443
 
                        break;
444
 
                case S_ROMA:
445
 
                        state->m_vs.rom_adr = state->m_bsp.y;
446
 
                        break;
447
 
                case S_SREG:
448
 
                        /* FPOS is shifted into sreg */
449
 
                        state->m_vgen.sreg = (state->m_vgen.sreg >> 1) | ((state->m_bsp.f >> 9) & 4);
450
 
                        break;
451
 
                default:
452
 
                        break;
453
 
                }
454
 
 
455
 
                /* Vector generator setup */
456
 
                switch (cmc->of)
457
 
                {
458
 
                case 0:
459
 
                        state->m_vgen.color = state->m_bsp.y & 0xfff;
460
 
                        break;
461
 
                case 1:
462
 
                        state->m_vgen.intensity = state->m_bsp.y & 0xff;
463
 
                        break;
464
 
                case 2:
465
 
                        state->m_vgen.l1 = state->m_bsp.y & 0xfff;
466
 
                        state->m_vgen.adder_s = 0;
467
 
                        state->m_vgen.adder_a = state->m_vgen.l2;
468
 
                        state->m_vgen.hud1 = state->m_vgen.sreg & 1;
469
 
                        state->m_vgen.vud1 = state->m_vgen.sreg & 2;
470
 
                        state->m_vgen.hc1  = state->m_vgen.sreg & 4;
471
 
                        state->m_vgen.brez = 1;
472
 
                        break;
473
 
                case 3:
474
 
                        state->m_vgen.l2 = state->m_bsp.y & 0xfff;
475
 
                        state->m_vgen.adder_s = (state->m_vgen.adder_s + state->m_vgen.adder_a) & 0xfff;
476
 
                        if (state->m_vgen.adder_s & 0x800)
477
 
                                state->m_vgen.adder_a = state->m_vgen.l1;
478
 
                        else
479
 
                                state->m_vgen.adder_a = state->m_vgen.l2;
480
 
                        state->m_vgen.hud2 = state->m_vgen.sreg & 1;
481
 
                        state->m_vgen.vud2 = state->m_vgen.sreg & 2;
482
 
                        break;
483
 
                case 4:
484
 
                        state->m_vgen.c_v = state->m_bsp.y & 0xfff;
485
 
                        break;
486
 
                case 5:
487
 
                        state->m_vgen.c_h = state->m_bsp.y & 0xfff;
488
 
                        break;
489
 
                case 6:
490
 
                        /* Loading the c_l counter starts
491
 
             * the vector counters if MSB is set
492
 
             */
493
 
                        state->m_vgen.c_l = state->m_bsp.y & 0xfff;
494
 
                        break;
495
 
                }
496
 
 
497
 
                vertigo_vgen (&state->m_vgen);
498
 
 
499
 
                /* Microcode program flow */
500
 
                switch (cmc->jcon)
501
 
                {
502
 
                case S_MSB:
503
 
                        /* ALU most significant bit */
504
 
                        jcond = (state->m_bsp.f >> 15) & 1;
505
 
                        break;
506
 
                case S_FEQ0:
507
 
                        /* ALU is 0 */
508
 
                        jcond = (state->m_bsp.f == 0)? 1 : 0;
509
 
                        break;
510
 
                case S_Y10:
511
 
                        jcond = (state->m_bsp.y >> 10) & 1;
512
 
                        break;
513
 
                case S_VFIN:
514
 
                        jcond = state->m_vgen.vfin;
515
 
                        break;
516
 
                case S_FPOS:
517
 
                        /* FPOS is bit 11 */
518
 
                        jcond = (state->m_bsp.f >> 11) & 1;
519
 
                        break;
520
 
                case S_INTL4:
521
 
                        jcond = irq4;
522
 
                        /* Detect idle loop. If the code takes a jump
523
 
             on irq4 or !irq4 the destination is a idle loop
524
 
             waiting for irq4 state change. We then take a short
525
 
             cut and run for just 100 cycles to make sure the
526
 
             loop is actually entered.
527
 
            */
528
 
                        if ((cmc->jpos != irq4) && cycles > 100)
529
 
                        {
530
 
                                cycles=100;
531
 
                        }
532
 
                        break;
533
 
                default:
534
 
                        jcond = 1;
535
 
                        break;
536
 
                }
537
 
 
538
 
                if (jcond ^ cmc->jpos)
539
 
                {
540
 
                        /* Except for JBK, address bit 8 isn't changed
541
 
               in program flow. */
542
 
                        switch (cmc->jmp)
543
 
                        {
544
 
                        case S_JBK:
545
 
                                /* JBK is the only jump where MA8 is used */
546
 
                                state->m_vs.pc = cmc->ma;
547
 
                                break;
548
 
                        case S_CALL:
549
 
                                /* call and store return address */
550
 
                                state->m_vs.ret = (state->m_vs.pc + 1) & 0xff;
551
 
                                state->m_vs.pc = (state->m_vs.pc & 0x100) | (cmc->ma & 0xff);
552
 
                                break;
553
 
                        case S_OPT:
554
 
                                /* OPT is used for microcode jump tables. The first
555
 
                   four address bits are defined by bits 12-15
556
 
                   of 2901 input (D) */
557
 
                                state->m_vs.pc = (state->m_vs.pc & 0x100) | (cmc->ma & 0xf0) | ((state->m_bsp.d >> 12) & 0xf);
558
 
                                break;
559
 
                        case S_RETURN:
560
 
                                /* return from call */
561
 
                                state->m_vs.pc = (state->m_vs.pc & 0x100) | state->m_vs.ret;
562
 
                                break;
563
 
                        }
564
 
                }
565
 
                else
566
 
                {
567
 
                        state->m_vs.pc = (state->m_vs.pc & 0x100) | ((state->m_vs.pc + 1) & 0xff);
568
 
                }
569
 
        }
570
 
 
571
 
        g_profiler.stop();
572
 
}