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  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Jordi Mallach, Emmanuel Kasper
  • Date: 2011-12-19 22:56:27 UTC
  • mfrom: (0.1.2)
  • Revision ID: package-import@ubuntu.com-20111219225627-ub5oga1oys4ogqzm
Tags: 0.144-1
http://bugs.debian.org/651538
[ Jordi Mallach ]
* Fix syntax errors in DEP5 copyright file (lintian).
* Use a versioned copyright Format specification field.
* Update Vcs-* URLs.
* Move transitional packages to the new metapackages section, and make
  them priority extra.
* Remove references to GNU/Linux and MESS sources from copyright.
* Add build variables for s390x.
* Use .xz tarballs as it cuts 4MB for the upstream sources.
* Add nplayers.ini as a patch. Update copyright file to add CC-BY-SA-3.0.

[ Emmanuel Kasper ]
* New upstream release. Closes: #651538.
* Add Free Desktop compliant png icons of various sizes taken from
  the hydroxygen iconset
* Mess is now built from a new source package, to avoid possible source
  incompatibilities between mame and the mess overlay.
* Mame-tools are not built from the mame source package anymore, but
  from the mess source package

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mess/src/emu/cpu/alph8201/alph8201.c
1
 
/****************************************************************************
2
 
                         Alpha8201 Emulator
3
 
 
4
 
                      Copyright Tatsuyuki Satoh
5
 
                   Originally written for the MAME project.
6
 
 
7
 
 
8
 
The Alpha8201/830x isn't a real CPU. It is a Hitachi HD44801 4-bit MCU,
9
 
programmed to interpret an external program using a custom instruction set.
10
 
Alpha8301 has an expanded instruction set, backwards compatible with Alpha8201
11
 
 
12
 
The internal ROM hasn't been read (yet), so here we provide a simulation of
13
 
the behaviour.
14
 
 
15
 
 
16
 
Game                      Year  MCU
17
 
------------------------  ----  ----
18
 
Shougi                    1982? 8201 (pcb)
19
 
Shougi 2                  1982? 8201 (pcb)
20
 
Talbot                    1982  8201?
21
 
Champion Base Ball        1983  8201 (schematics)
22
 
Exciting Soccer           1983  8302 (pcb)
23
 
Champion Base Ball II     1983  8302 (pcb, unofficial schematics)
24
 
Exciting Soccer II        1984  8303 (uses 8303+ opcodes)
25
 
Equites                   1984  8303 (post)
26
 
Bull Fighter              1984  8303 (post)
27
 
Splendor Blast            1985  8303 (post)
28
 
Gekisou                   1985  8304 (post)
29
 
The Koukouyakyuh          1985  8304 (post)
30
 
High Voltage              1985  8404?(post says 8404, but readme says 8304)
31
 
 
32
 
alpha8201: "44801A75" -> HD44801 , ROM code = A75
33
 
ALPHA8302: "44801B35" -> HD44801 , ROM code = B35
34
 
ALPHA8303: "44801B42" -> HD44801 , ROM code = B42
35
 
ALPHA8304: ?
36
 
 
37
 
 
38
 
    Notes :
39
 
      some unknown instruction are not emulated.
40
 
 
41
 
      Because there was no information, opcode-syntax was created.
42
 
 
43
 
    TODO:
44
 
        verify with real chip or analyze more.
45
 
            -A lot of 8301 opcode.
46
 
            -memory address 000 specification
47
 
            -memory address 001 bit 7-5 specification
48
 
            -write value after HALT operation to ODD of vector memory.
49
 
            -operation cycle(execution speed).
50
 
 
51
 
****************************************************************************/
52
 
 
53
 
/****************************************************************************
54
 
 
55
 
-----------------------
56
 
package / pin assign
57
 
-----------------------
58
 
ALPHA 8201 DIP 42
59
 
 
60
 
pin    HD44801  Alpha
61
 
---    -------  -----
62
 
1    : D3       WR
63
 
2-4  : D4-D6    n.c.
64
 
5-7  : D7-D9    GND in shougi , n.c. in champbas
65
 
8-13 : D10-D15  n.c.
66
 
14   : n.c.     n.c.
67
 
15   : RESET    RESET
68
 
16   : GND      GND
69
 
17   : OSC1     (champbas=384KHz)
70
 
18   : OSC2     n.c.
71
 
19   : !HLT     Vcc
72
 
20   : !TEST    Vcc
73
 
21   : Vcc      Vcc
74
 
22-25: R00-R03  DB4-DB7
75
 
26-29: R10-R13  DB0-DB3
76
 
30   : INT0     GO (input)
77
 
31   : INT1     n.c.
78
 
32-35: R20-R23  A4-A7
79
 
36-39: R30-R33  A0-A3
80
 
40-41: D0-D1    A8-A9
81
 
42   : D2       /RD
82
 
 
83
 
 
84
 
-----------------------
85
 
Register Set
86
 
-----------------------
87
 
 
88
 
PC      : 10bit Program Pointer
89
 
          A lower 8bits are loaded from the immidate.
90
 
          A higher 2bits are loaded from the MB register.
91
 
 
92
 
MB      : 2bit memory bank register, load PC[9:8] after branch
93
 
          load high to higher 2bit of PC after branch.
94
 
 
95
 
RB      : 3bit register bank select register
96
 
 
97
 
R0-R7   : internal? RAM register 8bitx8 (x8 bank)
98
 
 
99
 
A       : 8bit
100
 
 
101
 
cpustate->IX0/1   : memory indirect 'read' access pointer
102
 
 
103
 
cpustate->IX2     : memory indirect 'write' access pointer
104
 
 
105
 
RXB     : unknown , looks index register
106
 
 
107
 
cpustate->LP0/1/2 : loop count register used by DJNZ operation
108
 
 
109
 
cpustate->cf      : carry flag
110
 
cpustate->zf      : zero flag
111
 
 
112
 
-----------------------
113
 
Memoy Space
114
 
-----------------------
115
 
 
116
 
000     : unknown ...
117
 
001     : bit4..0 = pointer of current entry , bit7..6 = unknown
118
 
002-003 : entrypoint1  vector
119
 
004-005 : entrypoint2  vector
120
 
006-007 : entrypoint3  vector
121
 
008-009 : entrypoint4  vector
122
 
00A-00B : entrypoint5  vector
123
 
00C-00D : entrypoint6  vector
124
 
00E-00F : entrypoint7  vector
125
 
010-011 : entrypoint8  vector
126
 
012-013 : entrypoint9  vector
127
 
014-015 : entrypoint10 vector
128
 
016-017 : entrypoint11 vector
129
 
018-019 : entrypoint12 vector
130
 
01A-01B : entrypoint13 vector
131
 
01C-01D : entrypoint14 vector
132
 
01E-01F : entrypoint15 vector
133
 
020-0FF : bank 0, program / data memory
134
 
100-1FF : bank 1, program / data memory
135
 
200-2FF : bank 2, program / data memory
136
 
300-3FF : bank 3, program / data memory
137
 
 
138
 
The even address is the lower byte of the entry address.
139
 
The odd-address of entry point is a MB and status.
140
 
  Bit 0 and 1 are a memory bank.
141
 
  Bit 2 is HALT.At the time of set, it doesn't execute entry address.
142
 
  After EXIT operation, Bit2 is set.
143
 
 
144
 
-----------------------
145
 
Timming
146
 
-----------------------
147
 
 
148
 
****************************************************************************/
149
 
 
150
 
#include "emu.h"
151
 
#include "debugger.h"
152
 
#include "alph8201.h"
153
 
 
154
 
/* instruction cycle count */
155
 
#define C1 16
156
 
#define C2 32
157
 
 
158
 
/* debug option */
159
 
#define TRACE_PC 0
160
 
#define SHOW_ENTRY_POINT 0
161
 
#define SHOW_MESSAGE_CONSOLE 0
162
 
#define BREAK_ON_UNKNOWN_OPCODE 0
163
 
#define BREAK_ON_UNCERTAIN_OPCODE 0
164
 
 
165
 
/* MAME is unnecessary */
166
 
#define HANDLE_HALT_LINE 0
167
 
 
168
 
#define M_RDMEM(A)              cpustate->program->read_byte(A)
169
 
#define M_WRMEM(A,V)    cpustate->program->write_byte(A, V)
170
 
#define M_RDOP(A)               cpustate->direct->read_decrypted_byte(A)
171
 
#define M_RDOP_ARG(A)   cpustate->direct->read_raw_byte(A)
172
 
 
173
 
typedef struct _alpha8201_state alpha8201_state;
174
 
struct _alpha8201_state
175
 
{
176
 
        UINT8 RAM[8*8];  /* internal GP register 8 * 8bank       */
177
 
        unsigned PREVPC;
178
 
        PAIR  retptr;   /* for 8301, return address of CALL       */
179
 
        PAIR  pc;       /* 2bit+8bit program counter              */
180
 
        UINT8 regPtr;   /* RB register base                       */
181
 
        UINT8 mb;       /* MB memory bank reg. latch after Branch */
182
 
        UINT8 cf;       /* C flag                                 */
183
 
        UINT8 zf;       /* Z flag                                 */
184
 
        UINT8 savec;    /* for 8301, save flags                   */
185
 
        UINT8 savez;    /* for 8301, save flags                   */
186
 
//
187
 
        PAIR ix0;               /* 8bit memory read index reg. */
188
 
        PAIR ix1;               /* 8bitmemory read index reg.  */
189
 
        PAIR ix2;               /* 8bitmemory write index reg. */
190
 
        UINT8 lp0;       /* 8bit loop reg.             */
191
 
        UINT8 lp1;       /* 8bit loop reg.             */
192
 
        UINT8 lp2;       /* 8bit loop reg.             */
193
 
        UINT8 A;         /* 8bit accumerator           */
194
 
        UINT8 B;         /* 8bit regiser               */
195
 
//
196
 
#if HANDLE_HALT_LINE
197
 
        UINT8 halt;     /* halt input line                        */
198
 
#endif
199
 
 
200
 
        legacy_cpu_device *device;
201
 
        address_space *program;
202
 
        direct_read_data *direct;
203
 
        int icount;
204
 
        int inst_cycles;
205
 
};
206
 
 
207
 
/* The opcode table now is a combination of cycle counts and function pointers */
208
 
typedef struct {
209
 
        unsigned cycles;
210
 
        void (*function) (alpha8201_state *cpustate);
211
 
}       s_opcode;
212
 
 
213
 
 
214
 
#define PC                              pc.w.l
215
 
#define PCL                             pc.b.l
216
 
#define RD_REG(x)               cpustate->RAM[(cpustate->regPtr<<3)+(x)]
217
 
#define WR_REG(x,d)             cpustate->RAM[(cpustate->regPtr<<3)+(x)]=(d)
218
 
#define IX0                             ix0.b.l
219
 
#define IX1                             ix1.b.l
220
 
#define IX2                             ix2.b.l
221
 
#define BIX0                    ix0.w.l
222
 
#define BIX1                    ix1.w.l
223
 
#define BIX2                    ix2.w.l
224
 
#define LP0                             lp0
225
 
#define LP1                             lp1
226
 
#define LP2                             lp2
227
 
 
228
 
INLINE alpha8201_state *get_safe_token(device_t *device)
229
 
{
230
 
        assert(device != NULL);
231
 
        assert(device->type() == ALPHA8201 ||
232
 
                   device->type() == ALPHA8301);
233
 
        return (alpha8201_state *)downcast<legacy_cpu_device *>(device)->token();
234
 
}
235
 
 
236
 
/* Get next opcode argument and increment program counter */
237
 
INLINE unsigned M_RDMEM_OPCODE (alpha8201_state *cpustate)
238
 
{
239
 
        unsigned retval;
240
 
        retval=M_RDOP_ARG(cpustate->PC);
241
 
        cpustate->PCL++;
242
 
        return retval;
243
 
}
244
 
 
245
 
INLINE void M_ADD(alpha8201_state *cpustate, UINT8 dat)
246
 
{
247
 
        UINT16 temp = cpustate->A + dat;
248
 
        cpustate->A = temp & 0xff;
249
 
        cpustate->zf = (cpustate->A==0);
250
 
        cpustate->cf = temp>>8;
251
 
}
252
 
 
253
 
INLINE void M_ADDB(alpha8201_state *cpustate, UINT8 dat)
254
 
{
255
 
        UINT16 temp = cpustate->B + dat;
256
 
        cpustate->B = temp & 0xff;
257
 
        cpustate->zf = (cpustate->B==0);
258
 
        cpustate->cf = temp>>8;
259
 
}
260
 
 
261
 
INLINE void M_SUB(alpha8201_state *cpustate, UINT8 dat)
262
 
{
263
 
        cpustate->cf = (cpustate->A>=dat);      // cpustate->cf is No Borrow
264
 
        cpustate->A -= dat;
265
 
        cpustate->zf = (cpustate->A==0);
266
 
}
267
 
 
268
 
INLINE void M_AND(alpha8201_state *cpustate, UINT8 dat)
269
 
{
270
 
        cpustate->A &= dat;
271
 
        cpustate->zf = (cpustate->A==0);
272
 
}
273
 
 
274
 
INLINE void M_OR(alpha8201_state *cpustate, UINT8 dat)
275
 
{
276
 
        cpustate->A |= dat;
277
 
        cpustate->zf = (cpustate->A==0);
278
 
}
279
 
 
280
 
INLINE void M_XOR(alpha8201_state *cpustate, UINT8 dat)
281
 
{
282
 
        cpustate->A ^= dat;
283
 
        cpustate->zf = (cpustate->A==0);
284
 
        cpustate->cf = 0;
285
 
}
286
 
 
287
 
INLINE void M_JMP(alpha8201_state *cpustate, UINT8 dat)
288
 
{
289
 
        cpustate->PCL = dat;
290
 
        /* update pc page */
291
 
        cpustate->pc.b.h  = cpustate->ix0.b.h = cpustate->ix1.b.h = cpustate->ix2.b.h = cpustate->mb & 3;
292
 
}
293
 
 
294
 
INLINE void M_UNDEFINED(alpha8201_state *cpustate)
295
 
{
296
 
        logerror("alpha8201:  cpustate->PC = %03x,  Unimplemented opcode = %02x\n", cpustate->PC-1, M_RDMEM(cpustate->PC-1));
297
 
#if SHOW_MESSAGE_CONSOLE
298
 
        mame_printf_debug("alpha8201:  cpustate->PC = %03x,  Unimplemented opcode = %02x\n", cpustate->PC-1, M_RDMEM(cpustate->PC-1));
299
 
#endif
300
 
#if BREAK_ON_UNKNOWN_OPCODE
301
 
        debugger_break(cpustate->device->machine());
302
 
#endif
303
 
}
304
 
 
305
 
INLINE void M_UNDEFINED2(alpha8201_state *cpustate)
306
 
{
307
 
        UINT8 op  = M_RDOP(cpustate->PC-1);
308
 
        UINT8 imm = M_RDMEM_OPCODE(cpustate);
309
 
        logerror("alpha8201:  cpustate->PC = %03x,  Unimplemented opcode = %02x,%02x\n", cpustate->PC-2, op,imm);
310
 
#if SHOW_MESSAGE_CONSOLE
311
 
        mame_printf_debug("alpha8201:  cpustate->PC = %03x,  Unimplemented opcode = %02x,%02x\n", cpustate->PC-2, op,imm);
312
 
#endif
313
 
#if BREAK_ON_UNKNOWN_OPCODE
314
 
        debugger_break(cpustate->device->machine());
315
 
#endif
316
 
}
317
 
 
318
 
static void undefined(alpha8201_state *cpustate)        { M_UNDEFINED(cpustate); }
319
 
static void undefined2(alpha8201_state *cpustate)       { M_UNDEFINED2(cpustate); }
320
 
 
321
 
static void nop(alpha8201_state *cpustate)               { }
322
 
static void rora(alpha8201_state *cpustate)              { cpustate->cf = cpustate->A &1;     cpustate->A = (cpustate->A>>1) | (cpustate->A<<7); }
323
 
static void rola(alpha8201_state *cpustate)              { cpustate->cf = (cpustate->A>>7)&1; cpustate->A = (cpustate->A<<1) | (cpustate->A>>7); }
324
 
static void inc_b(alpha8201_state *cpustate)             { M_ADDB(cpustate, 0x02); }
325
 
static void dec_b(alpha8201_state *cpustate)             { M_ADDB(cpustate, 0xfe); }
326
 
static void inc_a(alpha8201_state *cpustate)             { M_ADD(cpustate, 0x01); }
327
 
static void dec_a(alpha8201_state *cpustate)             { M_ADD(cpustate, 0xff); }
328
 
static void cpl(alpha8201_state *cpustate)               { cpustate->A ^= 0xff; };
329
 
 
330
 
static void ld_a_ix0_0(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+0); }
331
 
static void ld_a_ix0_1(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+1); }
332
 
static void ld_a_ix0_2(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+2); }
333
 
static void ld_a_ix0_3(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+3); }
334
 
static void ld_a_ix0_4(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+4); }
335
 
static void ld_a_ix0_5(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+5); }
336
 
static void ld_a_ix0_6(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+6); }
337
 
static void ld_a_ix0_7(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+7); }
338
 
 
339
 
static void ld_a_ix1_0(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+0); }
340
 
static void ld_a_ix1_1(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+1); }
341
 
static void ld_a_ix1_2(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+2); }
342
 
static void ld_a_ix1_3(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+3); }
343
 
static void ld_a_ix1_4(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+4); }
344
 
static void ld_a_ix1_5(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+5); }
345
 
static void ld_a_ix1_6(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+6); }
346
 
static void ld_a_ix1_7(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX1+7); }
347
 
 
348
 
static void ld_ix2_0_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+0,cpustate->A); }
349
 
static void ld_ix2_1_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+1,cpustate->A); }
350
 
static void ld_ix2_2_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+2,cpustate->A); }
351
 
static void ld_ix2_3_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+3,cpustate->A); }
352
 
static void ld_ix2_4_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+4,cpustate->A); }
353
 
static void ld_ix2_5_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+5,cpustate->A); }
354
 
static void ld_ix2_6_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+6,cpustate->A); }
355
 
static void ld_ix2_7_a(alpha8201_state *cpustate) { M_WRMEM(cpustate->BIX2+7,cpustate->A); }
356
 
 
357
 
static void ld_ix0_0_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+0); }
358
 
static void ld_ix0_1_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+1); }
359
 
static void ld_ix0_2_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+2); }
360
 
static void ld_ix0_3_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+3); }
361
 
static void ld_ix0_4_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+4); }
362
 
static void ld_ix0_5_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+5); }
363
 
static void ld_ix0_6_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+6); }
364
 
static void ld_ix0_7_b(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0+7); }
365
 
 
366
 
static void bit_r0_0(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<0)?0:1; }
367
 
static void bit_r0_1(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<1)?0:1; }
368
 
static void bit_r0_2(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<2)?0:1; }
369
 
static void bit_r0_3(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<3)?0:1; }
370
 
static void bit_r0_4(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<4)?0:1; }
371
 
static void bit_r0_5(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<5)?0:1; }
372
 
static void bit_r0_6(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<6)?0:1; }
373
 
static void bit_r0_7(alpha8201_state *cpustate)  { cpustate->zf = RD_REG(0)&(1<<7)?0:1; }
374
 
 
375
 
static void ld_a_n(alpha8201_state *cpustate)    { cpustate->A = M_RDMEM_OPCODE(cpustate); }
376
 
 
377
 
static void ld_a_r0(alpha8201_state *cpustate)   { cpustate->A = RD_REG(0); cpustate->zf = (cpustate->A==0); }
378
 
static void ld_a_r1(alpha8201_state *cpustate)   { cpustate->A = RD_REG(1); cpustate->zf = (cpustate->A==0); }
379
 
static void ld_a_r2(alpha8201_state *cpustate)   { cpustate->A = RD_REG(2); cpustate->zf = (cpustate->A==0); }
380
 
static void ld_a_r3(alpha8201_state *cpustate)   { cpustate->A = RD_REG(3); cpustate->zf = (cpustate->A==0); }
381
 
static void ld_a_r4(alpha8201_state *cpustate)   { cpustate->A = RD_REG(4); cpustate->zf = (cpustate->A==0); }
382
 
static void ld_a_r5(alpha8201_state *cpustate)   { cpustate->A = RD_REG(5); cpustate->zf = (cpustate->A==0); }
383
 
static void ld_a_r6(alpha8201_state *cpustate)   { cpustate->A = RD_REG(6); cpustate->zf = (cpustate->A==0); }
384
 
static void ld_a_r7(alpha8201_state *cpustate)   { cpustate->A = RD_REG(7); cpustate->zf = (cpustate->A==0); }
385
 
 
386
 
static void ld_r0_a(alpha8201_state *cpustate)   { WR_REG(0,cpustate->A); }
387
 
static void ld_r1_a(alpha8201_state *cpustate)   { WR_REG(1,cpustate->A); }
388
 
static void ld_r2_a(alpha8201_state *cpustate)   { WR_REG(2,cpustate->A); }
389
 
static void ld_r3_a(alpha8201_state *cpustate)   { WR_REG(3,cpustate->A); }
390
 
static void ld_r4_a(alpha8201_state *cpustate)   { WR_REG(4,cpustate->A); }
391
 
static void ld_r5_a(alpha8201_state *cpustate)   { WR_REG(5,cpustate->A); }
392
 
static void ld_r6_a(alpha8201_state *cpustate)   { WR_REG(6,cpustate->A); }
393
 
static void ld_r7_a(alpha8201_state *cpustate)   { WR_REG(7,cpustate->A); }
394
 
 
395
 
static void add_a_n(alpha8201_state *cpustate)   { M_ADD(cpustate, M_RDMEM_OPCODE(cpustate)); }
396
 
 
397
 
static void add_a_r0(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(0)); }
398
 
static void add_a_r1(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(1)); }
399
 
static void add_a_r2(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(2)); }
400
 
static void add_a_r3(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(3)); }
401
 
static void add_a_r4(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(4)); }
402
 
static void add_a_r5(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(5)); }
403
 
static void add_a_r6(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(6)); }
404
 
static void add_a_r7(alpha8201_state *cpustate)  { M_ADD(cpustate, RD_REG(7)); }
405
 
 
406
 
static void sub_a_n(alpha8201_state *cpustate)   { M_SUB(cpustate, M_RDMEM_OPCODE(cpustate)); }
407
 
 
408
 
static void sub_a_r0(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(0)); }
409
 
static void sub_a_r1(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(1)); }
410
 
static void sub_a_r2(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(2)); }
411
 
static void sub_a_r3(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(3)); }
412
 
static void sub_a_r4(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(4)); }
413
 
static void sub_a_r5(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(5)); }
414
 
static void sub_a_r6(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(6)); }
415
 
static void sub_a_r7(alpha8201_state *cpustate)  { M_SUB(cpustate, RD_REG(7)); }
416
 
 
417
 
static void and_a_n(alpha8201_state *cpustate)   { M_AND(cpustate, M_RDMEM_OPCODE(cpustate)); }
418
 
 
419
 
static void and_a_r0(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(0)); }
420
 
static void and_a_r1(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(1)); }
421
 
static void and_a_r2(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(2)); }
422
 
static void and_a_r3(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(3)); }
423
 
static void and_a_r4(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(4)); }
424
 
static void and_a_r5(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(5)); }
425
 
static void and_a_r6(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(6)); }
426
 
static void and_a_r7(alpha8201_state *cpustate)  { M_AND(cpustate, RD_REG(7)); }
427
 
 
428
 
static void or_a_n(alpha8201_state *cpustate)    { M_OR(cpustate, M_RDMEM_OPCODE(cpustate)); }
429
 
 
430
 
static void or_a_r0(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(0)); }
431
 
static void or_a_r1(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(1)); }
432
 
static void or_a_r2(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(2)); }
433
 
static void or_a_r3(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(3)); }
434
 
static void or_a_r4(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(4)); }
435
 
static void or_a_r5(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(5)); }
436
 
static void or_a_r6(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(6)); }
437
 
static void or_a_r7(alpha8201_state *cpustate)   { M_OR(cpustate, RD_REG(7)); }
438
 
 
439
 
static void add_ix0_0(alpha8201_state *cpustate)         { }
440
 
static void add_ix0_1(alpha8201_state *cpustate)         { cpustate->IX0 += 1; }
441
 
static void add_ix0_2(alpha8201_state *cpustate)         { cpustate->IX0 += 2; }
442
 
static void add_ix0_3(alpha8201_state *cpustate)         { cpustate->IX0 += 3; }
443
 
static void add_ix0_4(alpha8201_state *cpustate)         { cpustate->IX0 += 4; }
444
 
static void add_ix0_5(alpha8201_state *cpustate)         { cpustate->IX0 += 5; }
445
 
static void add_ix0_6(alpha8201_state *cpustate)         { cpustate->IX0 += 6; }
446
 
static void add_ix0_7(alpha8201_state *cpustate)         { cpustate->IX0 += 7; }
447
 
static void add_ix0_8(alpha8201_state *cpustate)         { cpustate->IX0 += 8; }
448
 
static void add_ix0_9(alpha8201_state *cpustate)         { cpustate->IX0 += 9; }
449
 
static void add_ix0_a(alpha8201_state *cpustate)         { cpustate->IX0 += 10; }
450
 
static void add_ix0_b(alpha8201_state *cpustate)         { cpustate->IX0 += 11; }
451
 
static void add_ix0_c(alpha8201_state *cpustate)         { cpustate->IX0 += 12; }
452
 
static void add_ix0_d(alpha8201_state *cpustate)         { cpustate->IX0 += 13; }
453
 
static void add_ix0_e(alpha8201_state *cpustate)         { cpustate->IX0 += 14; }
454
 
static void add_ix0_f(alpha8201_state *cpustate)         { cpustate->IX0 += 15; }
455
 
 
456
 
static void add_ix1_0(alpha8201_state *cpustate)         { }
457
 
static void add_ix1_1(alpha8201_state *cpustate)         { cpustate->IX1 += 1; }
458
 
static void add_ix1_2(alpha8201_state *cpustate)         { cpustate->IX1 += 2; }
459
 
static void add_ix1_3(alpha8201_state *cpustate)         { cpustate->IX1 += 3; }
460
 
static void add_ix1_4(alpha8201_state *cpustate)         { cpustate->IX1 += 4; }
461
 
static void add_ix1_5(alpha8201_state *cpustate)         { cpustate->IX1 += 5; }
462
 
static void add_ix1_6(alpha8201_state *cpustate)         { cpustate->IX1 += 6; }
463
 
static void add_ix1_7(alpha8201_state *cpustate)         { cpustate->IX1 += 7; }
464
 
static void add_ix1_8(alpha8201_state *cpustate)         { cpustate->IX1 += 8; }
465
 
static void add_ix1_9(alpha8201_state *cpustate)         { cpustate->IX1 += 9; }
466
 
static void add_ix1_a(alpha8201_state *cpustate)         { cpustate->IX1 += 10; }
467
 
static void add_ix1_b(alpha8201_state *cpustate)         { cpustate->IX1 += 11; }
468
 
static void add_ix1_c(alpha8201_state *cpustate)         { cpustate->IX1 += 12; }
469
 
static void add_ix1_d(alpha8201_state *cpustate)         { cpustate->IX1 += 13; }
470
 
static void add_ix1_e(alpha8201_state *cpustate)         { cpustate->IX1 += 14; }
471
 
static void add_ix1_f(alpha8201_state *cpustate)         { cpustate->IX1 += 15; }
472
 
 
473
 
static void add_ix2_0(alpha8201_state *cpustate)         { }
474
 
static void add_ix2_1(alpha8201_state *cpustate)         { cpustate->IX2 += 1; }
475
 
static void add_ix2_2(alpha8201_state *cpustate)         { cpustate->IX2 += 2; }
476
 
static void add_ix2_3(alpha8201_state *cpustate)         { cpustate->IX2 += 3; }
477
 
static void add_ix2_4(alpha8201_state *cpustate)         { cpustate->IX2 += 4; }
478
 
static void add_ix2_5(alpha8201_state *cpustate)         { cpustate->IX2 += 5; }
479
 
static void add_ix2_6(alpha8201_state *cpustate)         { cpustate->IX2 += 6; }
480
 
static void add_ix2_7(alpha8201_state *cpustate)         { cpustate->IX2 += 7; }
481
 
static void add_ix2_8(alpha8201_state *cpustate)         { cpustate->IX2 += 8; }
482
 
static void add_ix2_9(alpha8201_state *cpustate)         { cpustate->IX2 += 9; }
483
 
static void add_ix2_a(alpha8201_state *cpustate)         { cpustate->IX2 += 10; }
484
 
static void add_ix2_b(alpha8201_state *cpustate)         { cpustate->IX2 += 11; }
485
 
static void add_ix2_c(alpha8201_state *cpustate)         { cpustate->IX2 += 12; }
486
 
static void add_ix2_d(alpha8201_state *cpustate)         { cpustate->IX2 += 13; }
487
 
static void add_ix2_e(alpha8201_state *cpustate)         { cpustate->IX2 += 14; }
488
 
static void add_ix2_f(alpha8201_state *cpustate)         { cpustate->IX2 += 15; }
489
 
 
490
 
static void ld_base_0(alpha8201_state *cpustate)         { cpustate->regPtr = 0; }
491
 
static void ld_base_1(alpha8201_state *cpustate)         { cpustate->regPtr = 1; }
492
 
static void ld_base_2(alpha8201_state *cpustate)         { cpustate->regPtr = 2; }
493
 
static void ld_base_3(alpha8201_state *cpustate)         { cpustate->regPtr = 3; }
494
 
static void ld_base_4(alpha8201_state *cpustate)         { cpustate->regPtr = 4; }
495
 
static void ld_base_5(alpha8201_state *cpustate)         { cpustate->regPtr = 5; }
496
 
static void ld_base_6(alpha8201_state *cpustate)         { cpustate->regPtr = 6; }
497
 
static void ld_base_7(alpha8201_state *cpustate)         { cpustate->regPtr = 7; }
498
 
 
499
 
static void ld_bank_0(alpha8201_state *cpustate)         { cpustate->mb = 0; }
500
 
static void ld_bank_1(alpha8201_state *cpustate)         { cpustate->mb = 1; }
501
 
static void ld_bank_2(alpha8201_state *cpustate)         { cpustate->mb = 2; }
502
 
static void ld_bank_3(alpha8201_state *cpustate)         { cpustate->mb = 3; }
503
 
 
504
 
static void stop(alpha8201_state *cpustate)
505
 
{
506
 
        UINT8 pcptr = M_RDMEM(0x001) & 0x1f;
507
 
        M_WRMEM(pcptr,(M_RDMEM(pcptr)&0xf)+0x08); /* mark entry point ODD to HALT */
508
 
        cpustate->mb |= 0x08;        /* mark internal HALT state */
509
 
}
510
 
 
511
 
static void ld_ix0_n(alpha8201_state *cpustate)  { cpustate->IX0 = M_RDMEM_OPCODE(cpustate); }
512
 
static void ld_ix1_n(alpha8201_state *cpustate)  { cpustate->IX1 = M_RDMEM_OPCODE(cpustate); }
513
 
static void ld_ix2_n(alpha8201_state *cpustate)  { cpustate->IX2 = M_RDMEM_OPCODE(cpustate); }
514
 
static void ld_lp0_n(alpha8201_state *cpustate)  { cpustate->LP0 = M_RDMEM_OPCODE(cpustate); }
515
 
static void ld_lp1_n(alpha8201_state *cpustate)  { cpustate->LP1 = M_RDMEM_OPCODE(cpustate); }
516
 
static void ld_lp2_n(alpha8201_state *cpustate)  { cpustate->LP2 = M_RDMEM_OPCODE(cpustate); }
517
 
static void ld_b_n(alpha8201_state *cpustate)    { cpustate->B = M_RDMEM_OPCODE(cpustate); }
518
 
 
519
 
static void djnz_lp0(alpha8201_state *cpustate) { UINT8 i=M_RDMEM_OPCODE(cpustate); cpustate->LP0--; if (cpustate->LP0 != 0) M_JMP(cpustate, i); }
520
 
static void djnz_lp1(alpha8201_state *cpustate) { UINT8 i=M_RDMEM_OPCODE(cpustate); cpustate->LP1--; if (cpustate->LP1 != 0) M_JMP(cpustate, i); }
521
 
static void djnz_lp2(alpha8201_state *cpustate) { UINT8 i=M_RDMEM_OPCODE(cpustate); cpustate->LP2--; if (cpustate->LP2 != 0) M_JMP(cpustate, i); }
522
 
static void jnz(alpha8201_state *cpustate)      { UINT8 i=M_RDMEM_OPCODE(cpustate); if (!cpustate->zf) M_JMP(cpustate, i); }
523
 
static void jnc(alpha8201_state *cpustate)      { UINT8 i=M_RDMEM_OPCODE(cpustate); if (!cpustate->cf) M_JMP(cpustate, i);}
524
 
static void jz(alpha8201_state *cpustate)       { UINT8 i=M_RDMEM_OPCODE(cpustate); if ( cpustate->zf) M_JMP(cpustate, i); }
525
 
static void jc(alpha8201_state *cpustate)       { UINT8 i=M_RDMEM_OPCODE(cpustate); if ( cpustate->cf) M_JMP(cpustate, i);}
526
 
static void jmp(alpha8201_state *cpustate)      { M_JMP(cpustate,  M_RDMEM_OPCODE(cpustate) ); }
527
 
 
528
 
static const s_opcode opcode_8201[256]=
529
 
{
530
 
        {C1, nop        },{C1,rora      },{C1, rola      },{C1,inc_b     },{C1,dec_b     },{C1, inc_a    },{C1, dec_a    },{C1, cpl      },
531
 
        {C2,ld_a_ix0_0  },{C2,ld_a_ix0_1},{C2, ld_a_ix0_2},{C2,ld_a_ix0_3},{C2,ld_a_ix0_4},{C2,ld_a_ix0_5},{C2,ld_a_ix0_6},{C2,ld_a_ix0_7},
532
 
        {C2,ld_a_ix1_0  },{C2,ld_a_ix1_1},{C2, ld_a_ix1_2},{C2,ld_a_ix1_3},{C2,ld_a_ix1_4},{C2,ld_a_ix1_5},{C2,ld_a_ix1_6},{C2,ld_a_ix1_7},
533
 
        {C2,ld_ix2_0_a  },{C2,ld_ix2_1_a},{C2, ld_ix2_2_a},{C2,ld_ix2_3_a},{C2,ld_ix2_4_a},{C2,ld_ix2_5_a},{C2,ld_ix2_6_a},{C2,ld_ix2_7_a},
534
 
/* 20 */
535
 
        {C2,ld_ix0_0_b  },{C2,ld_ix0_1_b},{C2, ld_ix0_2_b},{C2,ld_ix0_3_b},{C2,ld_ix0_4_b},{C2,ld_ix0_5_b},{C2,ld_ix0_6_b},{C2,ld_ix0_7_b},
536
 
        {C2,undefined   },{C2,undefined },{C2, undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },
537
 
        {C2,undefined   },{C2,undefined },{C2, undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },
538
 
        {C2,bit_r0_0    },{C2,bit_r0_1  },{C2, bit_r0_2 },{C2, bit_r0_3 },{C2, bit_r0_4 },{C2, bit_r0_5 },{C2, bit_r0_6 },{C2, bit_r0_7 },
539
 
/* 40 : 8201 */
540
 
        {C2, ld_a_r0    },{C2, ld_r0_a  },{C2, ld_a_r1  },{C2, ld_r1_a  },{C2, ld_a_r2  },{C2, ld_r2_a  },{C2, ld_a_r3  },{C2, ld_r3_a  },
541
 
        {C2, ld_a_r4    },{C2, ld_r4_a  },{C2, ld_a_r5  },{C2, ld_r5_a  },{C2, ld_a_r6  },{C2, ld_r6_a  },{C2, ld_a_r7  },{C2, ld_r7_a  },
542
 
        {C1, add_a_r0   },{C1, sub_a_r0 },{C1, add_a_r1 },{C1, sub_a_r1 },{C1, add_a_r2 },{C1, sub_a_r2 },{C1, add_a_r3 },{C1, sub_a_r3 },
543
 
        {C1, add_a_r4   },{C1, sub_a_r4 },{C1, add_a_r5 },{C1, sub_a_r5 },{C1, add_a_r6 },{C1, sub_a_r6 },{C1, add_a_r7 },{C1, sub_a_r7 },
544
 
        {C1, and_a_r0   },{C1, or_a_r0  },{C1, and_a_r1 },{C1, or_a_r1  },{C1, and_a_r2 },{C1, or_a_r2  },{C1, and_a_r3 },{C1, or_a_r3  },
545
 
        {C1, and_a_r4   },{C1, or_a_r4  },{C1, and_a_r5 },{C1, or_a_r5  },{C1, and_a_r6 },{C1, or_a_r6  },{C1, and_a_r7 },{C1, or_a_r7  },
546
 
        {C1, add_ix0_0  },{C1, add_ix0_1},{C1, add_ix0_2},{C1, add_ix0_3},{C1, add_ix0_4},{C1, add_ix0_5},{C1, add_ix0_6},{C1, add_ix0_7},
547
 
        {C1, add_ix0_8  },{C1, add_ix0_9},{C1, add_ix0_a},{C1, add_ix0_b},{C1, add_ix0_c},{C1, add_ix0_d},{C1, add_ix0_e},{C1, add_ix0_f},
548
 
/* 80 : 8201 */
549
 
        {C1, add_ix1_0  },{C1, add_ix1_1},{C1, add_ix1_2},{C1, add_ix1_3},{C1, add_ix1_4},{C1, add_ix1_5},{C1, add_ix1_6},{C1, add_ix1_7},
550
 
        {C1, add_ix1_8  },{C1, add_ix1_9},{C1, add_ix1_a},{C1, add_ix1_b},{C1, add_ix1_c},{C1, add_ix1_d},{C1, add_ix1_e},{C1, add_ix1_f},
551
 
        {C1, add_ix2_0  },{C1, add_ix2_1},{C1, add_ix2_2},{C1, add_ix2_3},{C1, add_ix2_4},{C1, add_ix2_5},{C1, add_ix2_6},{C1, add_ix2_7},
552
 
        {C1, add_ix2_8  },{C1, add_ix2_9},{C1, add_ix2_a},{C1, add_ix2_b},{C1, add_ix2_c},{C1, add_ix2_d},{C1, add_ix2_e},{C1, add_ix2_f},
553
 
        {C1, ld_base_0  },{C1, ld_base_1},{C1, ld_base_2},{C1, ld_base_3},{C1, ld_base_4},{C1, ld_base_5},{C1, ld_base_6},{C1, ld_base_7},
554
 
        {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},
555
 
        {C1, ld_bank_0  },{C1, ld_bank_1},{C1, ld_bank_2},{C1, ld_bank_3},{C2, stop     },{C1, undefined},{C1, undefined},{C1, undefined},
556
 
        {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},
557
 
/* c0 : 8201 */
558
 
        {C2, ld_ix0_n   },{C2, ld_ix1_n },{C2, ld_ix2_n },{C2, ld_a_n   },{C2, ld_lp0_n },{C2, ld_lp1_n },{C2, ld_lp2_n },{C2, ld_b_n   },
559
 
        {C2, add_a_n    },{C2, sub_a_n  },{C2, and_a_n  },{C2, or_a_n   },{C2, djnz_lp0 },{C2, djnz_lp1 },{C2, djnz_lp2 },{C2, jnz              },
560
 
        {C2, jnc                },{C2, jz               },{C2, jmp              },{C2,undefined2},{C2,undefined2},{C2,undefined2},{C2,undefined2},{C2, undefined2},
561
 
        {C2, undefined2 },{C2,undefined2},{C2,undefined2},{C2,undefined2},{C2,undefined2},{C2,undefined2},{C2,undefined2},{C2, undefined2},
562
 
/* E0 : 8201*/
563
 
        {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},
564
 
        {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},
565
 
        {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},
566
 
        {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined }
567
 
};
568
 
 
569
 
 
570
 
/* ALPHA 8301 : added instruction */
571
 
static void exg_a_ix0(alpha8201_state *cpustate)  { UINT8 t=cpustate->A; cpustate->A = cpustate->IX0; cpustate->IX0 = t; }
572
 
static void exg_a_ix1(alpha8201_state *cpustate)  { UINT8 t=cpustate->A; cpustate->A = cpustate->IX1; cpustate->IX1 = t; }
573
 
static void exg_a_ix2(alpha8201_state *cpustate)  { UINT8 t=cpustate->A; cpustate->A = cpustate->IX2; cpustate->IX2 = t; }
574
 
static void exg_a_lp0(alpha8201_state *cpustate)  { UINT8 t=cpustate->A; cpustate->A = cpustate->LP0; cpustate->LP0 = t; }
575
 
static void exg_a_lp1(alpha8201_state *cpustate)  { UINT8 t=cpustate->A; cpustate->A = cpustate->LP1; cpustate->LP1 = t; }
576
 
static void exg_a_lp2(alpha8201_state *cpustate)  { UINT8 t=cpustate->A; cpustate->A = cpustate->LP2; cpustate->LP2 = t; }
577
 
static void exg_a_b(alpha8201_state *cpustate)    { UINT8 t=cpustate->A; cpustate->A = cpustate->B; cpustate->B = t; }
578
 
static void exg_a_rb(alpha8201_state *cpustate)   { UINT8 t=cpustate->A; cpustate->A = cpustate->regPtr; cpustate->regPtr = t; }
579
 
 
580
 
static void ld_ix0_a(alpha8201_state *cpustate)    { cpustate->IX0 = cpustate->A; }
581
 
static void ld_ix1_a(alpha8201_state *cpustate)    { cpustate->IX1 = cpustate->A; }
582
 
static void ld_ix2_a(alpha8201_state *cpustate)    { cpustate->IX2 = cpustate->A; }
583
 
static void ld_lp0_a(alpha8201_state *cpustate)    { cpustate->LP0 = cpustate->A; }
584
 
static void ld_lp1_a(alpha8201_state *cpustate)    { cpustate->LP1 = cpustate->A; }
585
 
static void ld_lp2_a(alpha8201_state *cpustate)    { cpustate->LP2 = cpustate->A; }
586
 
static void ld_b_a(alpha8201_state *cpustate)      { cpustate->B = cpustate->A; }
587
 
static void ld_rb_a(alpha8201_state *cpustate)     { cpustate->regPtr = cpustate->A; }
588
 
 
589
 
static void exg_ix0_ix1(alpha8201_state *cpustate)  { UINT8 t=cpustate->IX1; cpustate->IX1 = cpustate->IX0; cpustate->IX0 = t; }
590
 
static void exg_ix0_ix2(alpha8201_state *cpustate)  { UINT8 t=cpustate->IX2; cpustate->IX2 = cpustate->IX0; cpustate->IX0 = t; }
591
 
 
592
 
static void op_d4(alpha8201_state *cpustate) { cpustate->A = M_RDMEM( ((cpustate->RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE(cpustate) ); }
593
 
static void op_d5(alpha8201_state *cpustate) { M_WRMEM( ((cpustate->RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE(cpustate), cpustate->A ); }
594
 
static void op_d6(alpha8201_state *cpustate) { cpustate->LP0 = M_RDMEM( ((cpustate->RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE(cpustate) ); }
595
 
static void op_d7(alpha8201_state *cpustate) { M_WRMEM( ((cpustate->RAM[(7<<3)+7] & 3) << 8) | M_RDMEM_OPCODE(cpustate), cpustate->LP0 ); }
596
 
 
597
 
static void ld_a_abs(alpha8201_state *cpustate) { cpustate->A = M_RDMEM( ((cpustate->mb & 3) << 8) | M_RDMEM_OPCODE(cpustate) ); }
598
 
static void ld_abs_a(alpha8201_state *cpustate) { M_WRMEM( ((cpustate->mb & 3) << 8) | M_RDMEM_OPCODE(cpustate), cpustate->A ); }
599
 
 
600
 
static void ld_a_r(alpha8201_state *cpustate) { cpustate->A = cpustate->RAM[(M_RDMEM_OPCODE(cpustate)>>1)&0x3f]; }
601
 
static void ld_r_a(alpha8201_state *cpustate) { cpustate->RAM[(M_RDMEM_OPCODE(cpustate)>>1)&0x3f] = cpustate->A; }
602
 
static void op_rep_ld_ix2_b(alpha8201_state *cpustate) { do { M_WRMEM(cpustate->BIX2, cpustate->RAM[(cpustate->B>>1)&0x3f]); cpustate->IX2++; cpustate->B+=2; cpustate->LP0--; } while (cpustate->LP0 != 0); }
603
 
static void op_rep_ld_b_ix0(alpha8201_state *cpustate) { do { cpustate->RAM[(cpustate->B>>1)&0x3f] = M_RDMEM(cpustate->BIX0); cpustate->IX0++; cpustate->B+=2; cpustate->LP0--; } while (cpustate->LP0 != 0); }
604
 
static void ld_rxb_a(alpha8201_state *cpustate) { cpustate->RAM[(cpustate->B>>1)&0x3f] = cpustate->A; }
605
 
static void ld_a_rxb(alpha8201_state *cpustate) { cpustate->A = cpustate->RAM[(cpustate->B>>1)&0x3f]; }
606
 
static void cmp_a_rxb(alpha8201_state *cpustate) { UINT8 i=cpustate->RAM[(cpustate->B>>1)&0x3f];  cpustate->zf = (cpustate->A==i); cpustate->cf = (cpustate->A>=i); }
607
 
static void xor_a_rxb(alpha8201_state *cpustate) { M_XOR(cpustate, cpustate->RAM[(cpustate->B>>1)&0x3f] ); }
608
 
 
609
 
static void add_a_cf(alpha8201_state *cpustate) { if (cpustate->cf) inc_a(cpustate); }
610
 
static void sub_a_cf(alpha8201_state *cpustate) { if (cpustate->cf) dec_a(cpustate); }
611
 
static void tst_a(alpha8201_state *cpustate)     { cpustate->zf = (cpustate->A==0); }
612
 
static void clr_a(alpha8201_state *cpustate)     { cpustate->A = 0; cpustate->zf = (cpustate->A==0); }
613
 
static void cmp_a_n(alpha8201_state *cpustate)  { UINT8 i=M_RDMEM_OPCODE(cpustate);  cpustate->zf = (cpustate->A==i); cpustate->cf = (cpustate->A>=i); }
614
 
static void xor_a_n(alpha8201_state *cpustate)  { M_XOR(cpustate, M_RDMEM_OPCODE(cpustate) ); }
615
 
static void call(alpha8201_state *cpustate) { UINT8 i=M_RDMEM_OPCODE(cpustate); cpustate->retptr.w.l = cpustate->PC; M_JMP(cpustate, i); };
616
 
static void ld_a_ix0_a(alpha8201_state *cpustate) { cpustate->A = M_RDMEM(cpustate->BIX0+cpustate->A); }
617
 
static void ret(alpha8201_state *cpustate) { cpustate->mb = cpustate->retptr.b.h; M_JMP(cpustate,  cpustate->retptr.b.l ); };
618
 
static void save_zc(alpha8201_state *cpustate) { cpustate->savez = cpustate->zf; cpustate->savec = cpustate->cf; };
619
 
static void rest_zc(alpha8201_state *cpustate) { cpustate->zf = cpustate->savez; cpustate->cf = cpustate->savec; };
620
 
 
621
 
static const s_opcode opcode_8301[256]=
622
 
{
623
 
        {C1, nop        },{C1,rora      },{C1, rola      },{C1,inc_b     },{C1,dec_b     },{C1, inc_a    },{C1, dec_a    },{C1, cpl      },
624
 
        {C2,ld_a_ix0_0  },{C2,ld_a_ix0_1},{C2, ld_a_ix0_2},{C2,ld_a_ix0_3},{C2,ld_a_ix0_4},{C2,ld_a_ix0_5},{C2,ld_a_ix0_6},{C2,ld_a_ix0_7},
625
 
        {C2,ld_a_ix1_0  },{C2,ld_a_ix1_1},{C2, ld_a_ix1_2},{C2,ld_a_ix1_3},{C2,ld_a_ix1_4},{C2,ld_a_ix1_5},{C2,ld_a_ix1_6},{C2,ld_a_ix1_7},
626
 
        {C2,ld_ix2_0_a  },{C2,ld_ix2_1_a},{C2, ld_ix2_2_a},{C2,ld_ix2_3_a},{C2,ld_ix2_4_a},{C2,ld_ix2_5_a},{C2,ld_ix2_6_a},{C2,ld_ix2_7_a},
627
 
/* 20 : 8301 */
628
 
        {C2,ld_ix0_0_b  },{C2,ld_ix0_1_b},{C2, ld_ix0_2_b},{C2,ld_ix0_3_b},{C2,ld_ix0_4_b},{C2,ld_ix0_5_b},{C2,ld_ix0_6_b},{C2,ld_ix0_7_b},
629
 
        {C2,undefined   },{C2,undefined },{C2, undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },
630
 
        {C2,undefined   },{C2,undefined },{C2, undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },{C2,undefined },
631
 
        {C2,bit_r0_0    },{C2,bit_r0_1  },{C2, bit_r0_2 },{C2, bit_r0_3 },{C2, bit_r0_4 },{C2, bit_r0_5 },{C2, bit_r0_6 },{C2, bit_r0_7 },
632
 
/* 40 : 8301 */
633
 
        {C2, ld_a_r0    },{C2, ld_r0_a  },{C2, ld_a_r1  },{C2, ld_r1_a  },{C2, ld_a_r2  },{C2, ld_r2_a  },{C2, ld_a_r3  },{C2, ld_r3_a  },
634
 
        {C2, ld_a_r4    },{C2, ld_r4_a  },{C2, ld_a_r5  },{C2, ld_r5_a  },{C2, ld_a_r6  },{C2, ld_r6_a  },{C2, ld_a_r7  },{C2, ld_r7_a  },
635
 
        {C1, add_a_r0   },{C1, sub_a_r0 },{C1, add_a_r1 },{C1, sub_a_r1 },{C1, add_a_r2 },{C1, sub_a_r2 },{C1, add_a_r3 },{C1, sub_a_r3 },
636
 
        {C1, add_a_r4   },{C1, sub_a_r4 },{C1, add_a_r5 },{C1, sub_a_r5 },{C1, add_a_r6 },{C1, sub_a_r6 },{C1, add_a_r7 },{C1, sub_a_r7 },
637
 
/* 60 : 8301 */
638
 
        {C1, and_a_r0   },{C1, or_a_r0  },{C1, and_a_r1 },{C1, or_a_r1  },{C1, and_a_r2 },{C1, or_a_r2  },{C1, and_a_r3 },{C1, or_a_r3  },
639
 
        {C1, and_a_r4   },{C1, or_a_r4  },{C1, and_a_r5 },{C1, or_a_r5  },{C1, and_a_r6 },{C1, or_a_r6  },{C1, and_a_r7 },{C1, or_a_r7  },
640
 
        {C1, add_ix0_0  },{C1, add_ix0_1},{C1, add_ix0_2},{C1, add_ix0_3},{C1, add_ix0_4},{C1, add_ix0_5},{C1, add_ix0_6},{C1, add_ix0_7},
641
 
        {C1, add_ix0_8  },{C1, add_ix0_9},{C1, add_ix0_a},{C1, add_ix0_b},{C1, add_ix0_c},{C1, add_ix0_d},{C1, add_ix0_e},{C1, add_ix0_f},
642
 
/* 80 : 8301 */
643
 
        {C1, add_ix1_0  },{C1, add_ix1_1},{C1, add_ix1_2},{C1, add_ix1_3},{C1, add_ix1_4},{C1, add_ix1_5},{C1, add_ix1_6},{C1, add_ix1_7},
644
 
        {C1, add_ix1_8  },{C1, add_ix1_9},{C1, add_ix1_a},{C1, add_ix1_b},{C1, add_ix1_c},{C1, add_ix1_d},{C1, add_ix1_e},{C1, add_ix1_f},
645
 
        {C1, add_ix2_0  },{C1, add_ix2_1},{C1, add_ix2_2},{C1, add_ix2_3},{C1, add_ix2_4},{C1, add_ix2_5},{C1, add_ix2_6},{C1, add_ix2_7},
646
 
        {C1, add_ix2_8  },{C1, add_ix2_9},{C1, add_ix2_a},{C1, add_ix2_b},{C1, add_ix2_c},{C1, add_ix2_d},{C1, add_ix2_e},{C1, add_ix2_f},
647
 
/* A0 : 8301 */
648
 
        {C1, ld_base_0  },{C1, ld_base_1},{C1, ld_base_2},{C1, ld_base_3},{C1, ld_base_4},{C1, ld_base_5},{C1, ld_base_6},{C1, ld_base_7},
649
 
        {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},
650
 
        {C1, ld_bank_0  },{C1, ld_bank_1},{C1, ld_bank_2},{C1, ld_bank_3},{C2, stop     },{C1, undefined},{C1, undefined},{C1, undefined},
651
 
        {C1, undefined  },{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},{C1, undefined},
652
 
/* c0 : 8301 */
653
 
        {C2, ld_ix0_n   },{C2, ld_ix1_n},{C2, ld_ix2_n  },{C2, ld_a_n   },{C2, ld_lp0_n },{C2, ld_lp1_n },{C2, ld_lp2_n },{C2, ld_b_n   },
654
 
        {C2, add_a_n    },{C2, sub_a_n  },{C2, and_a_n  },{C2, or_a_n   },{C2, djnz_lp0 },{C2, djnz_lp1 },{C2, djnz_lp2 },{C2, jnz              },
655
 
        {C2, jnc                        },{C2, jz               },{C2, jmp              },{C2,undefined2},{C2, op_d4    },{C2, op_d5    },{C2, op_d6    },{C2, op_d7    },
656
 
        {C2, ld_a_abs  },{C2, ld_abs_a},{C2,cmp_a_n     },{C2,xor_a_n   },{C2, ld_a_r   },{C2, ld_r_a   },{C2, jc       },{C2, call},
657
 
/* E0 : 8301 */
658
 
        {C1, exg_a_ix0  },{C1, exg_a_ix1},{C1, exg_a_ix2},{C1, exg_a_lp1},{C1, exg_a_lp2},{C1, exg_a_b  },{C1, exg_a_lp0},{C1, exg_a_rb },
659
 
        {C1, ld_ix0_a   },{C1, ld_ix1_a },{C1, ld_ix2_a },{C1, ld_lp1_a },{C1, ld_lp2_a },{C1, ld_b_a   },{C1, ld_lp0_a },{C1, ld_rb_a  },
660
 
        {C1,exg_ix0_ix1},{C1,exg_ix0_ix2},{C1,op_rep_ld_ix2_b},{C1, op_rep_ld_b_ix0},{C1, save_zc},{C1, rest_zc},{C1, ld_rxb_a },{C1, ld_a_rxb },
661
 
        {C1, cmp_a_rxb },{C1, xor_a_rxb},{C1, add_a_cf },{C1, sub_a_cf },{C1, tst_a    },{C1, clr_a    },{C1, ld_a_ix0_a},{C1, ret     }
662
 
};
663
 
 
664
 
/****************************************************************************
665
 
 * Initialize emulation
666
 
 ****************************************************************************/
667
 
static CPU_INIT( alpha8201 )
668
 
{
669
 
        alpha8201_state *cpustate = get_safe_token(device);
670
 
 
671
 
        cpustate->device = device;
672
 
        cpustate->program = device->space(AS_PROGRAM);
673
 
        cpustate->direct = &cpustate->program->direct();
674
 
 
675
 
        device->save_item(NAME(cpustate->RAM));
676
 
        device->save_item(NAME(cpustate->PREVPC));
677
 
        device->save_item(NAME(cpustate->PC));
678
 
        device->save_item(NAME(cpustate->regPtr));
679
 
        device->save_item(NAME(cpustate->zf));
680
 
        device->save_item(NAME(cpustate->cf));
681
 
        device->save_item(NAME(cpustate->mb));
682
 
#if HANDLE_HALT_LINE
683
 
        device->save_item(NAME(cpustate->halt));
684
 
#endif
685
 
        device->save_item(NAME(cpustate->IX0));
686
 
        device->save_item(NAME(cpustate->IX1));
687
 
        device->save_item(NAME(cpustate->IX2));
688
 
        device->save_item(NAME(cpustate->LP0));
689
 
        device->save_item(NAME(cpustate->LP1));
690
 
        device->save_item(NAME(cpustate->LP2));
691
 
        device->save_item(NAME(cpustate->A));
692
 
        device->save_item(NAME(cpustate->B));
693
 
        device->save_item(NAME(cpustate->retptr));
694
 
        device->save_item(NAME(cpustate->savec));
695
 
        device->save_item(NAME(cpustate->savez));
696
 
}
697
 
/****************************************************************************
698
 
 * Reset registers to their initial values
699
 
 ****************************************************************************/
700
 
static CPU_RESET( alpha8201 )
701
 
{
702
 
        alpha8201_state *cpustate = get_safe_token(device);
703
 
        cpustate->PC     = 0;
704
 
        cpustate->regPtr = 0;
705
 
        cpustate->zf     = 0;
706
 
        cpustate->cf     = 0;
707
 
        cpustate->mb   = 0;
708
 
        cpustate->BIX0   = 0;
709
 
        cpustate->BIX1   = 0;
710
 
        cpustate->BIX2   = 0;
711
 
        cpustate->LP0    = 0;
712
 
        cpustate->LP1    = 0;
713
 
        cpustate->LP2    = 0;
714
 
        cpustate->A    = 0;
715
 
        cpustate->B   = 0;
716
 
#if HANDLE_HALT_LINE
717
 
        cpustate->halt = 0;
718
 
#endif
719
 
}
720
 
 
721
 
/****************************************************************************
722
 
 * Shut down CPU emulation
723
 
 ****************************************************************************/
724
 
static CPU_EXIT( alpha8201 )
725
 
{
726
 
        /* nothing to do ? */
727
 
}
728
 
 
729
 
/****************************************************************************
730
 
 * Execute cycles CPU cycles. Return number of cycles really executed
731
 
 ****************************************************************************/
732
 
 
733
 
static void alpha8xxx_execute(device_t *device,const s_opcode *op_map)
734
 
{
735
 
        alpha8201_state *cpustate = get_safe_token(device);
736
 
        unsigned opcode;
737
 
        UINT8 pcptr;
738
 
 
739
 
#if HANDLE_HALT_LINE
740
 
        if(cpustate->halt)
741
 
        {
742
 
                cpustate->icount = 0;
743
 
                return;
744
 
        }
745
 
#endif
746
 
 
747
 
        /* setup address bank & fall safe */
748
 
        cpustate->ix0.b.h =
749
 
        cpustate->ix1.b.h =
750
 
        cpustate->ix2.b.h = (cpustate->pc.b.h &= 3);
751
 
 
752
 
        /* reset start hack */
753
 
        if(cpustate->PC<0x20)
754
 
                cpustate->mb |= 0x08;
755
 
 
756
 
        do
757
 
        {
758
 
                if(cpustate->mb & 0x08)
759
 
                {
760
 
                        pcptr = M_RDMEM(0x001) & 0x1f; /* pointer of entry point */
761
 
                        cpustate->icount -= C1;
762
 
 
763
 
                        /* entry point scan phase */
764
 
                        if( (pcptr&1) == 0)
765
 
                        {
766
 
                                /* EVEN , get cpustate->PC low */
767
 
                                cpustate->pc.b.l = M_RDMEM(pcptr);
768
 
//mame_printf_debug("alpha8201 load PCL ENTRY=%02X PCL=%02X\n",pcptr, cpustate->pc.b.l);
769
 
                                cpustate->icount -= C1;
770
 
                                M_WRMEM(0x001,pcptr+1);
771
 
                                continue;
772
 
                        }
773
 
 
774
 
                        /* ODD , check HALT flag */
775
 
                        cpustate->mb   = M_RDMEM(pcptr) & (0x08|0x03);
776
 
                        cpustate->icount -= C1;
777
 
 
778
 
                        /* not entryaddress 000,001 */
779
 
                        if(pcptr<2) cpustate->mb |= 0x08;
780
 
 
781
 
                        if(cpustate->mb & 0x08)
782
 
                        {
783
 
                                /* HALTED current entry point . next one */
784
 
                                pcptr = (pcptr+1)&0x1f;
785
 
                                M_WRMEM(0x001,pcptr);
786
 
                                cpustate->icount -= C1;
787
 
                                continue;
788
 
                        }
789
 
 
790
 
                        /* goto run phase */
791
 
                        M_JMP(cpustate, cpustate->pc.b.l);
792
 
 
793
 
#if SHOW_ENTRY_POINT
794
 
logerror("alpha8201 START ENTRY=%02X cpustate->PC=%03X\n",pcptr,cpustate->PC);
795
 
mame_printf_debug("alpha8201 START ENTRY=%02X cpustate->PC=%03X\n",pcptr,cpustate->PC);
796
 
#endif
797
 
                }
798
 
 
799
 
                /* run */
800
 
                cpustate->PREVPC = cpustate->PC;
801
 
                debugger_instruction_hook(device, cpustate->PC);
802
 
                opcode =M_RDOP(cpustate->PC);
803
 
#if TRACE_PC
804
 
mame_printf_debug("alpha8201:  cpustate->PC = %03x,  opcode = %02x\n", cpustate->PC, opcode);
805
 
#endif
806
 
                cpustate->PCL++;
807
 
                cpustate->inst_cycles = op_map[opcode].cycles;
808
 
                (*(op_map[opcode].function))(cpustate);
809
 
                cpustate->icount -= cpustate->inst_cycles;
810
 
        } while (cpustate->icount>0);
811
 
}
812
 
 
813
 
static CPU_EXECUTE( alpha8201 ) { alpha8xxx_execute(device,opcode_8201); }
814
 
 
815
 
static CPU_EXECUTE( ALPHA8301 ) { alpha8xxx_execute(device,opcode_8301); }
816
 
 
817
 
/****************************************************************************
818
 
 * Set IRQ line state
819
 
 ****************************************************************************/
820
 
#if HANDLE_HALT_LINE
821
 
static void set_irq_line(alpha8201_state *cpustate, int irqline, int state)
822
 
{
823
 
        if(irqline == INPUT_LINE_HALT)
824
 
        {
825
 
                cpustate->halt = (state==ASSERT_LINE) ? 1 : 0;
826
 
/* mame_printf_debug("alpha8201 HALT %d\n",cpustate->halt); */
827
 
        }
828
 
}
829
 
#endif
830
 
 
831
 
/**************************************************************************
832
 
 * Generic set_info
833
 
 **************************************************************************/
834
 
 
835
 
static CPU_SET_INFO( alpha8201 )
836
 
{
837
 
        alpha8201_state *cpustate = get_safe_token(device);
838
 
        switch (state)
839
 
        {
840
 
#if HANDLE_HALT_LINE
841
 
                case CPUINFO_INT_INPUT_STATE + INPUT_LINE_HALT: set_irq_line(cpustate, INPUT_LINE_HALT, info->i);       break;
842
 
#endif
843
 
                case CPUINFO_INT_PC:
844
 
                case CPUINFO_INT_REGISTER + ALPHA8201_PC:                       cpustate->PC = info->i;                                         break;
845
 
                case CPUINFO_INT_SP:
846
 
                case CPUINFO_INT_REGISTER + ALPHA8201_SP:                       M_WRMEM(0x001,info->i);                         break;
847
 
                case CPUINFO_INT_REGISTER + ALPHA8201_RB:                       cpustate->regPtr = info->i & 7;                         break;
848
 
                case CPUINFO_INT_REGISTER + ALPHA8201_MB:                       cpustate->mb = info->i & 0x03;                          break;
849
 
#if 0
850
 
                case CPUINFO_INT_REGISTER + ALPHA8201_ZF:                       cpustate->zf= info->i & 0x01;                           break;
851
 
                case CPUINFO_INT_REGISTER + ALPHA8201_CF:                       cpustate->cf= info->i & 0x01;                           break;
852
 
#endif
853
 
                case CPUINFO_INT_REGISTER + ALPHA8201_IX0:                      cpustate->IX0 = info->i;                                                break;
854
 
                case CPUINFO_INT_REGISTER + ALPHA8201_IX1:                      cpustate->IX1 = info->i;                                                break;
855
 
                case CPUINFO_INT_REGISTER + ALPHA8201_IX2:                      cpustate->IX2 = info->i;                                                break;
856
 
                case CPUINFO_INT_REGISTER + ALPHA8201_LP0:                      cpustate->LP0 = info->i;                                                break;
857
 
                case CPUINFO_INT_REGISTER + ALPHA8201_LP1:                      cpustate->LP1 = info->i;                                                break;
858
 
                case CPUINFO_INT_REGISTER + ALPHA8201_LP2:                      cpustate->LP2 = info->i;                                                break;
859
 
                case CPUINFO_INT_REGISTER + ALPHA8201_A:                        cpustate->A = info->i;                                          break;
860
 
                case CPUINFO_INT_REGISTER + ALPHA8201_B:                        cpustate->B = info->i;                                          break;
861
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R0:                       WR_REG(0,info->i);                                      break;
862
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R1:                       WR_REG(1,info->i);                                      break;
863
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R2:                       WR_REG(2,info->i);                                      break;
864
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R3:                       WR_REG(3,info->i);                                      break;
865
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R4:                       WR_REG(4,info->i);                                      break;
866
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R5:                       WR_REG(5,info->i);                                      break;
867
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R6:                       WR_REG(6,info->i);                                      break;
868
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R7:                       WR_REG(7,info->i);                                      break;
869
 
        }
870
 
}
871
 
 
872
 
 
873
 
 
874
 
/**************************************************************************
875
 
 * Generic get_info
876
 
 **************************************************************************/
877
 
 
878
 
/* 8201 and 8301 */
879
 
static CPU_GET_INFO( alpha8xxx )
880
 
{
881
 
        alpha8201_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
882
 
        switch (state)
883
 
        {
884
 
                /* --- the following bits of info are returned as 64-bit signed integers --- */
885
 
                case CPUINFO_INT_CONTEXT_SIZE:                                  info->i = sizeof(alpha8201_state);              break;
886
 
                case CPUINFO_INT_INPUT_LINES:                                   info->i = 0;                                                    break;
887
 
                case CPUINFO_INT_DEFAULT_IRQ_VECTOR:                    info->i = 0;                                                    break;
888
 
                case DEVINFO_INT_ENDIANNESS:                                    info->i = ENDIANNESS_LITTLE;                                    break;
889
 
                case CPUINFO_INT_CLOCK_MULTIPLIER:                              info->i = 1;                                                    break;
890
 
                case CPUINFO_INT_CLOCK_DIVIDER:                                 info->i = 1;                                                    break;
891
 
                case CPUINFO_INT_MIN_INSTRUCTION_BYTES:                 info->i = 1;                                                    break;
892
 
                case CPUINFO_INT_MAX_INSTRUCTION_BYTES:                 info->i = 2;                                                    break;
893
 
                case CPUINFO_INT_MIN_CYCLES:                                    info->i = 1;                                                    break;
894
 
                case CPUINFO_INT_MAX_CYCLES:                                    info->i = 16;                                                   break;
895
 
 
896
 
                case DEVINFO_INT_DATABUS_WIDTH + AS_PROGRAM:    info->i = 8;                                    break;
897
 
                case DEVINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 10;                                      break;
898
 
                case DEVINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0;                                       break;
899
 
                case DEVINFO_INT_DATABUS_WIDTH + AS_DATA:       info->i = 0;                                    break;
900
 
                case DEVINFO_INT_ADDRBUS_WIDTH + AS_DATA:       info->i = 0;                                    break;
901
 
                case DEVINFO_INT_ADDRBUS_SHIFT + AS_DATA:       info->i = 0;                                    break;
902
 
                case DEVINFO_INT_DATABUS_WIDTH + AS_IO:         info->i = 8;                                    break;
903
 
                case DEVINFO_INT_ADDRBUS_WIDTH + AS_IO:         info->i = 6;                                    break;
904
 
                case DEVINFO_INT_ADDRBUS_SHIFT + AS_IO:         info->i = 0;                                    break;
905
 
#if HANDLE_HALT_LINE
906
 
                case CPUINFO_INT_INPUT_STATE + INPUT_LINE_HALT:         info->i = cpustate->halt ? ASSERT_LINE : CLEAR_LINE; break;
907
 
#endif
908
 
                case CPUINFO_INT_PREVIOUSPC:                                            info->i = cpustate->PREVPC;                                     break;
909
 
                case CPUINFO_INT_PC:
910
 
                case CPUINFO_INT_REGISTER + ALPHA8201_PC:                       info->i = cpustate->PC & 0x3ff;                         break;
911
 
                case CPUINFO_INT_SP:
912
 
                case CPUINFO_INT_REGISTER + ALPHA8201_SP:                       info->i = M_RDMEM(0x001);                       break;
913
 
                case CPUINFO_INT_REGISTER + ALPHA8201_RB:                       info->i = cpustate->regPtr;                                     break;
914
 
                case CPUINFO_INT_REGISTER + ALPHA8201_MB:                       info->i = cpustate->mb;                                         break;
915
 
                case CPUINFO_INT_REGISTER + ALPHA8201_ZF:                       info->i = cpustate->zf;                                         break;
916
 
                case CPUINFO_INT_REGISTER + ALPHA8201_CF:                       info->i = cpustate->cf;                                         break;
917
 
                case CPUINFO_INT_REGISTER + ALPHA8201_IX0:                      info->i = cpustate->IX0;                                                break;
918
 
                case CPUINFO_INT_REGISTER + ALPHA8201_IX1:                      info->i = cpustate->IX1;                                                break;
919
 
                case CPUINFO_INT_REGISTER + ALPHA8201_IX2:                      info->i = cpustate->IX2;                                                break;
920
 
                case CPUINFO_INT_REGISTER + ALPHA8201_LP0:                      info->i = cpustate->LP0;                                                break;
921
 
                case CPUINFO_INT_REGISTER + ALPHA8201_LP1:                      info->i = cpustate->LP1;                                                break;
922
 
                case CPUINFO_INT_REGISTER + ALPHA8201_LP2:                      info->i = cpustate->LP2;                                                break;
923
 
                case CPUINFO_INT_REGISTER + ALPHA8201_A:                        info->i = cpustate->A;                                          break;
924
 
                case CPUINFO_INT_REGISTER + ALPHA8201_B:                        info->i = cpustate->B;                                          break;
925
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R0:                       info->i = RD_REG(0);                            break;
926
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R1:                       info->i = RD_REG(1);                            break;
927
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R2:                       info->i = RD_REG(2);                            break;
928
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R3:                       info->i = RD_REG(3);                            break;
929
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R4:                       info->i = RD_REG(4);                            break;
930
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R5:                       info->i = RD_REG(5);                            break;
931
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R6:                       info->i = RD_REG(6);                            break;
932
 
                case CPUINFO_INT_REGISTER + ALPHA8201_R7:                       info->i = RD_REG(7);                            break;
933
 
 
934
 
                /* --- the following bits of info are returned as pointers to data or functions --- */
935
 
                case CPUINFO_FCT_SET_INFO:                                              info->setinfo = CPU_SET_INFO_NAME(alpha8201);           break;
936
 
                case CPUINFO_FCT_INIT:                                                  info->init = CPU_INIT_NAME(alpha8201);                  break;
937
 
                case CPUINFO_FCT_RESET:                                                 info->reset = CPU_RESET_NAME(alpha8201);                        break;
938
 
                case CPUINFO_FCT_EXIT:                                                  info->exit = CPU_EXIT_NAME(alpha8201);                  break;
939
 
                case CPUINFO_FCT_BURN:                                                  info->burn = NULL;                                              break;
940
 
                case CPUINFO_FCT_DISASSEMBLE:                                   info->disassemble = CPU_DISASSEMBLE_NAME(alpha8201);            break;
941
 
                case CPUINFO_PTR_INSTRUCTION_COUNTER:                   info->icount = &cpustate->icount;               break;
942
 
 
943
 
                /* --- the following bits of info are returned as NULL-terminated strings --- */
944
 
                case DEVINFO_STR_FAMILY:                                        strcpy(info->s, "AlphaDenshi MCU");             break;
945
 
                case DEVINFO_STR_VERSION:                                       strcpy(info->s, "0.1");                                 break;
946
 
                case DEVINFO_STR_SOURCE_FILE:                                           strcpy(info->s, __FILE__);                              break;
947
 
                case DEVINFO_STR_CREDITS:                                       strcpy(info->s, "Copyright Tatsuyuki Satoh"); break;
948
 
                case CPUINFO_STR_FLAGS:                                                 sprintf(info->s, "%c%c", cpustate->cf?'C':'.',cpustate->zf?'Z':'.'); break;
949
 
                case CPUINFO_STR_REGISTER + ALPHA8201_PC:               sprintf(info->s, "cpustate->PC:%03X", cpustate->PC);            break;
950
 
                case CPUINFO_STR_REGISTER + ALPHA8201_SP:               sprintf(info->s, "SP:%02X", M_RDMEM(0x001) ); break;
951
 
                case CPUINFO_STR_REGISTER + ALPHA8201_RB:               sprintf(info->s, "RB:%X", cpustate->regPtr);            break;
952
 
                case CPUINFO_STR_REGISTER + ALPHA8201_MB:               sprintf(info->s, "MB:%X", cpustate->mb);                break;
953
 
#if 0
954
 
                case CPUINFO_STR_REGISTER + ALPHA8201_ZF:               sprintf(info->s, "cpustate->zf:%X", cpustate->zf);              break;
955
 
                case CPUINFO_STR_REGISTER + ALPHA8201_CF:               sprintf(info->s, "cpustate->cf:%X", cpustate->cf);              break;
956
 
#endif
957
 
                case CPUINFO_STR_REGISTER + ALPHA8201_IX0:              sprintf(info->s, "cpustate->IX0:%02X", cpustate->IX0);          break;
958
 
                case CPUINFO_STR_REGISTER + ALPHA8201_IX1:              sprintf(info->s, "cpustate->IX1:%02X", cpustate->IX1);          break;
959
 
                case CPUINFO_STR_REGISTER + ALPHA8201_IX2:              sprintf(info->s, "cpustate->IX2:%02X", cpustate->IX2);          break;
960
 
                case CPUINFO_STR_REGISTER + ALPHA8201_LP0:              sprintf(info->s, "cpustate->LP0:%02X", cpustate->LP0);          break;
961
 
                case CPUINFO_STR_REGISTER + ALPHA8201_LP1:              sprintf(info->s, "cpustate->LP1:%02X", cpustate->LP1);          break;
962
 
                case CPUINFO_STR_REGISTER + ALPHA8201_LP2:              sprintf(info->s, "cpustate->LP2:%02X", cpustate->LP2);          break;
963
 
                case CPUINFO_STR_REGISTER + ALPHA8201_A:                sprintf(info->s, "A:%02X", cpustate->A);                break;
964
 
                case CPUINFO_STR_REGISTER + ALPHA8201_B:                sprintf(info->s, "B:%02X", cpustate->B);                break;
965
 
                case CPUINFO_STR_REGISTER + ALPHA8201_R0:               sprintf(info->s, "R0:%02X", RD_REG(0));         break;
966
 
                case CPUINFO_STR_REGISTER + ALPHA8201_R1:               sprintf(info->s, "R1:%02X", RD_REG(1));         break;
967
 
                case CPUINFO_STR_REGISTER + ALPHA8201_R2:               sprintf(info->s, "R2:%02X", RD_REG(2));         break;
968
 
                case CPUINFO_STR_REGISTER + ALPHA8201_R3:               sprintf(info->s, "R3:%02X", RD_REG(3));         break;
969
 
                case CPUINFO_STR_REGISTER + ALPHA8201_R4:               sprintf(info->s, "R4:%02X", RD_REG(4));         break;
970
 
                case CPUINFO_STR_REGISTER + ALPHA8201_R5:               sprintf(info->s, "R5:%02X", RD_REG(5));         break;
971
 
                case CPUINFO_STR_REGISTER + ALPHA8201_R6:               sprintf(info->s, "R6:%02X", RD_REG(6));         break;
972
 
                case CPUINFO_STR_REGISTER + ALPHA8201_R7:               sprintf(info->s, "R7:%02X", RD_REG(7));         break;
973
 
        }
974
 
}
975
 
CPU_GET_INFO( alpha8201 )
976
 
{
977
 
        switch (state)
978
 
        {
979
 
        case DEVINFO_STR_NAME:                                                  strcpy(info->s, "ALPHA-8201");                          break;
980
 
        case CPUINFO_FCT_EXECUTE:                                               info->execute = CPU_EXECUTE_NAME(alpha8201);                    break;
981
 
        default:
982
 
                /* 8201 / 8301 */
983
 
                CPU_GET_INFO_CALL(alpha8xxx);
984
 
        }
985
 
}
986
 
 
987
 
CPU_GET_INFO( alpha8301 )
988
 
{
989
 
        switch (state)
990
 
        {
991
 
        case DEVINFO_STR_NAME:                                                  strcpy(info->s, "ALPHA-8301");                          break;
992
 
        case CPUINFO_FCT_EXECUTE:                                               info->execute = CPU_EXECUTE_NAME(ALPHA8301);                    break;
993
 
        default:
994
 
                /* 8201 / 8301 */
995
 
                CPU_GET_INFO_CALL(alpha8xxx);
996
 
        }
997
 
}
998
 
 
999
 
DEFINE_LEGACY_CPU_DEVICE(ALPHA8201, alpha8201);
1000
 
DEFINE_LEGACY_CPU_DEVICE(ALPHA8301, alpha8301);