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Viewing changes to mess/src/mame/drivers/drw80pkr.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Jordi Mallach, Emmanuel Kasper
  • Date: 2011-12-19 22:56:27 UTC
  • mfrom: (0.1.2)
  • Revision ID: package-import@ubuntu.com-20111219225627-ub5oga1oys4ogqzm
Tags: 0.144-1
http://bugs.debian.org/651538
[ Jordi Mallach ]
* Fix syntax errors in DEP5 copyright file (lintian).
* Use a versioned copyright Format specification field.
* Update Vcs-* URLs.
* Move transitional packages to the new metapackages section, and make
  them priority extra.
* Remove references to GNU/Linux and MESS sources from copyright.
* Add build variables for s390x.
* Use .xz tarballs as it cuts 4MB for the upstream sources.
* Add nplayers.ini as a patch. Update copyright file to add CC-BY-SA-3.0.

[ Emmanuel Kasper ]
* New upstream release. Closes: #651538.
* Add Free Desktop compliant png icons of various sizes taken from
  the hydroxygen iconset
* Mess is now built from a new source package, to avoid possible source
  incompatibilities between mame and the mess overlay.
* Mame-tools are not built from the mame source package anymore, but
  from the mess source package

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mess/src/mame/drivers/drw80pkr.c
1
 
/**********************************************************************************
2
 
 
3
 
 
4
 
    DRAW 80 POKER
5
 
 
6
 
    Driver by Jim Stolis.
7
 
 
8
 
 
9
 
    --- Technical Notes ---
10
 
 
11
 
    Name:    Draw 80 Poker
12
 
    Company: IGT - International Gaming Technology
13
 
    Year:    1982
14
 
 
15
 
    Hardware:
16
 
 
17
 
    CPU =  INTEL 8039       ; I8039 compatible
18
 
    VIDEO = SYS 6545        ; CRTC6845 compatible
19
 
    SND =  AY-3-8912        ; AY8910 compatible
20
 
 
21
 
    History:
22
 
 
23
 
    This is one of the first video machines produced by IGT.  Originally, the
24
 
    company was called SIRCOMA and was founded in 1979.  It became a public
25
 
    company in 1981 and changed its name to IGT.
26
 
 
27
 
***********************************************************************************/
28
 
#include "emu.h"
29
 
#include "machine/nvram.h"
30
 
#include "sound/ay8910.h"
31
 
#include "cpu/mcs48/mcs48.h"
32
 
 
33
 
 
34
 
class drw80pkr_state : public driver_device
35
 
{
36
 
public:
37
 
        drw80pkr_state(const machine_config &mconfig, device_type type, const char *tag)
38
 
                : driver_device(mconfig, type, tag) { }
39
 
 
40
 
        tilemap_t *m_bg_tilemap;
41
 
        UINT8 m_t0;
42
 
        UINT8 m_t1;
43
 
        UINT8 m_p0;
44
 
        UINT8 m_p1;
45
 
        UINT8 m_p2;
46
 
        UINT8 m_prog;
47
 
        UINT8 m_bus;
48
 
        UINT8 m_attract_mode;
49
 
        UINT8 m_active_bank;
50
 
        UINT8 m_pkr_io_ram[0x100];
51
 
        UINT16 m_video_ram[0x0400];
52
 
        UINT8 m_color_ram[0x0400];
53
 
};
54
 
 
55
 
 
56
 
#define CPU_CLOCK                       XTAL_8MHz
57
 
#define DATA_NVRAM_SIZE     0x100
58
 
 
59
 
 
60
 
static MACHINE_START( drw80pkr )
61
 
{
62
 
        drw80pkr_state *state = machine.driver_data<drw80pkr_state>();
63
 
        machine.device<nvram_device>("nvram")->set_base(state->m_pkr_io_ram, sizeof(state->m_pkr_io_ram));
64
 
}
65
 
 
66
 
/*****************
67
 
* Write Handlers *
68
 
******************/
69
 
 
70
 
static WRITE8_HANDLER( t0_w )
71
 
{
72
 
        drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
73
 
        state->m_t0 = data;
74
 
}
75
 
 
76
 
static WRITE8_HANDLER( t1_w )
77
 
{
78
 
        drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
79
 
        state->m_t1 = data;
80
 
}
81
 
 
82
 
static WRITE8_HANDLER( p0_w )
83
 
{
84
 
        drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
85
 
        state->m_p0 = data;
86
 
}
87
 
 
88
 
static WRITE8_HANDLER( p1_w )
89
 
{
90
 
        drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
91
 
        state->m_p1 = data;
92
 
}
93
 
 
94
 
static WRITE8_HANDLER( p2_w )
95
 
{
96
 
        drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
97
 
        state->m_p2 = data;
98
 
}
99
 
 
100
 
static WRITE8_HANDLER( prog_w )
101
 
{
102
 
        drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
103
 
        state->m_prog = data;
104
 
 
105
 
        // Bankswitch Program Memory
106
 
        if (state->m_prog == 0x01)
107
 
        {
108
 
                state->m_active_bank = state->m_active_bank ^ 0x01;
109
 
 
110
 
                memory_set_bank(space->machine(), "bank1", state->m_active_bank);
111
 
        }
112
 
}
113
 
 
114
 
static WRITE8_HANDLER( bus_w )
115
 
{
116
 
        drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
117
 
        state->m_bus = data;
118
 
}
119
 
 
120
 
static WRITE8_HANDLER( drw80pkr_io_w )
121
 
{
122
 
        drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
123
 
        UINT16 n_offs;
124
 
 
125
 
        if (state->m_p2 == 0x3f || state->m_p2 == 0x7f)
126
 
        {
127
 
                n_offs = ((state->m_p1 & 0xc0) << 2 ) + offset;
128
 
 
129
 
                if (state->m_p2 == 0x3f)
130
 
                {
131
 
                        state->m_video_ram[n_offs] = data; // low address
132
 
                } else {
133
 
                        state->m_color_ram[n_offs] = data & 0x0f; // color palette
134
 
                        state->m_video_ram[n_offs] += ((data & 0xf0) << 4 ); // high address
135
 
                }
136
 
 
137
 
                tilemap_mark_tile_dirty(state->m_bg_tilemap, n_offs);
138
 
        }
139
 
 
140
 
        if (state->m_p2 == 0xc7)
141
 
        {
142
 
                // CRTC Register
143
 
                // R0 = 0x1f(31)    Horizontal Total
144
 
                // R1 = 0x18(24)    Horizontal Displayed
145
 
                // R2 = 0x1a(26)    Horizontal Sync Position
146
 
                // R3 = 0x34(52)    HSYNC/VSYNC Widths
147
 
                // R4 = 0x1f(31)    Vertical Total
148
 
                // R5 = 0x01(01)    Vertical Total Adjust
149
 
                // R6 = 0x1b(27)    Vertical Displayed
150
 
                // R7 = 0x1c(28)    Vertical Sync Position
151
 
                // R8 = 0x10        Mode Control
152
 
                //                  Non-interlace
153
 
                //                  Straight Binary - Ram Addressing
154
 
                //                  Shared Memory - Ram Access
155
 
                //                  Delay Display Enable one character time
156
 
                //                  No Delay Cursor Skew
157
 
                // R9 = 0x07(07)    Scan Line
158
 
                // R10 = 0x00       Cursor Start
159
 
                // R11 = 0x00       Cursor End
160
 
                // R12 = 0x00       Display Start Address (High)
161
 
                // R13 = 0x00       Display Start Address (Low)
162
 
        }
163
 
 
164
 
        if (state->m_p2 == 0xd7)
165
 
        {
166
 
                // CRTC Address
167
 
        }
168
 
 
169
 
        if (state->m_p2 == 0xfb) {
170
 
                state->m_pkr_io_ram[offset] = data;
171
 
        }
172
 
 
173
 
        if (state->m_p2 == 0xff)
174
 
        {
175
 
                if (state->m_p1 == 0xdf)
176
 
                {
177
 
                        state->m_attract_mode = data; // Latch this for use in input reads (0x01 = attract mode, 0x00 = game in progress)
178
 
                }
179
 
 
180
 
                if (state->m_p1 == 0xdb || state->m_p1 == 0xef || state->m_p1 == 0xf7 || state->m_p1 == 0xfb)
181
 
                {
182
 
                        // unknown, most likely lamps, meters, hopper etc.
183
 
                }
184
 
 
185
 
                // ay8910 control port
186
 
                if (state->m_p1 == 0xfc)
187
 
                        ay8910_address_w(space->machine().device("aysnd"), 0, data);
188
 
 
189
 
                // ay8910_write_port_0_w
190
 
                if (state->m_p1 == 0xfe)
191
 
                        ay8910_data_w(space->machine().device("aysnd"), 0, data);
192
 
        }
193
 
}
194
 
 
195
 
/****************
196
 
* Read Handlers *
197
 
****************/
198
 
 
199
 
static READ8_HANDLER( t0_r )
200
 
{
201
 
        drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
202
 
    return state->m_t0;
203
 
}
204
 
 
205
 
static READ8_HANDLER( t1_r )
206
 
{
207
 
        drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
208
 
    return state->m_t1;
209
 
}
210
 
 
211
 
static READ8_HANDLER( p0_r )
212
 
{
213
 
        drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
214
 
    return state->m_p0;
215
 
}
216
 
 
217
 
static READ8_HANDLER( p1_r )
218
 
{
219
 
        drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
220
 
    return state->m_p1;
221
 
}
222
 
 
223
 
static READ8_HANDLER( p2_r )
224
 
{
225
 
        drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
226
 
    return state->m_p2;
227
 
}
228
 
 
229
 
static READ8_HANDLER( bus_r )
230
 
{
231
 
        drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
232
 
    return state->m_bus;
233
 
}
234
 
 
235
 
static READ8_HANDLER( drw80pkr_io_r )
236
 
{
237
 
        drw80pkr_state *state = space->machine().driver_data<drw80pkr_state>();
238
 
        UINT8 ret;
239
 
        UINT16 kbdin;
240
 
 
241
 
        ret = 0x00;
242
 
 
243
 
        if (state->m_p2 == 0x3b)
244
 
        {
245
 
                // unknown
246
 
        }
247
 
 
248
 
        if (state->m_p2 == 0x7b)
249
 
        {
250
 
                ret = state->m_pkr_io_ram[offset];
251
 
        }
252
 
 
253
 
        if (state->m_p2 == 0xf7)
254
 
        {
255
 
                // unknown
256
 
        }
257
 
 
258
 
        if (state->m_p2 == 0xfb)
259
 
        {
260
 
                ret = state->m_pkr_io_ram[offset];
261
 
        }
262
 
 
263
 
        if (state->m_p2 == 0xff)
264
 
        {
265
 
                if (state->m_p1 == 0x5f || state->m_p1 == 0x9f || state->m_p1 == 0xdb)
266
 
                {
267
 
                        // unknown
268
 
                }
269
 
 
270
 
                if (state->m_p1 == 0xfe)
271
 
                {
272
 
                        // Dip switches tied to sound chip
273
 
                        //
274
 
                        // TODO: Unknown switch positions, but found the following flipping bits:
275
 
                        //      SW.? = Double Up Option
276
 
                        //      SW.? = Coin Denomination
277
 
                        //      SW.4 = Payout Type (0=cash, 1=credit)
278
 
                        //      SW.? = Use Joker in Deck
279
 
                        //
280
 
                        ret = 0x77; // double-up with credit payout
281
 
                }
282
 
 
283
 
                if ((state->m_attract_mode == 0x01 && state->m_p1 == 0xef) || state->m_p1 == 0xf7)
284
 
                {
285
 
 
286
 
                        // TODO: Get Input Port Values
287
 
                        kbdin = ((input_port_read(space->machine(), "IN1") & 0xaf ) << 8) + input_port_read(space->machine(), "IN0");
288
 
 
289
 
                        switch (kbdin)
290
 
                        {
291
 
                                // The following is very incorrect, but does allow you to
292
 
                                // play slightly with very messed up hold buttons etc.
293
 
                                //
294
 
                                // Open/Close the door with 'O'
295
 
                                // Press '5' (twice) with door open to play credit
296
 
                                // Press '1' to draw/deal
297
 
                                //
298
 
                                case 0x0000: ret = 0x00; break;
299
 
                                case 0x0001: ret = 0x01; break; /* Door */
300
 
                                case 0x4000: ret = 0x00; break;
301
 
                                case 0x8000: ret = 0x00; break; /* Hand Pay */
302
 
                                case 0x0002: ret = 0x00; break; /* Books */
303
 
                                case 0x0004: ret = 0x0e; break; /* Coin In */
304
 
                                case 0x0008: ret = 0x0d; break; /* Start */
305
 
                                case 0x0010: ret = 0x00; break; /* Discard */
306
 
                                case 0x0020: ret = 0x00; break; /* Cancel */
307
 
                                case 0x0040: ret = 0x01; break; /* Hold 1 */
308
 
                                case 0x0080: ret = 0x02; break; /* Hold 2 */
309
 
                                case 0x0100: ret = 0x03; break; /* Hold 3 */
310
 
                                case 0x0200: ret = 0x04; break; /* Hold 4 */
311
 
                                case 0x0400: ret = 0x05; break; /* Hold 5 */
312
 
                                case 0x0800: ret = 0x00; break; /* Bet */
313
 
                        }
314
 
                }
315
 
        }
316
 
 
317
 
    return ret;
318
 
}
319
 
 
320
 
 
321
 
/****************************
322
 
* Video/Character functions *
323
 
****************************/
324
 
 
325
 
static TILE_GET_INFO( get_bg_tile_info )
326
 
{
327
 
        drw80pkr_state *state = machine.driver_data<drw80pkr_state>();
328
 
        int color = state->m_color_ram[tile_index];
329
 
        int code = state->m_video_ram[tile_index];
330
 
 
331
 
        SET_TILE_INFO(0, code, color, 0);
332
 
}
333
 
 
334
 
static VIDEO_START( drw80pkr )
335
 
{
336
 
        drw80pkr_state *state = machine.driver_data<drw80pkr_state>();
337
 
        state->m_bg_tilemap = tilemap_create(machine, get_bg_tile_info, tilemap_scan_rows, 8, 8, 24, 27);
338
 
}
339
 
 
340
 
static SCREEN_UPDATE( drw80pkr )
341
 
{
342
 
        drw80pkr_state *state = screen->machine().driver_data<drw80pkr_state>();
343
 
        tilemap_draw(bitmap, cliprect, state->m_bg_tilemap, 0, 0);
344
 
 
345
 
        return 0;
346
 
}
347
 
 
348
 
static PALETTE_INIT( drw80pkr )
349
 
{
350
 
        int j;
351
 
 
352
 
        for (j = 0; j < machine.total_colors(); j++)
353
 
        {
354
 
                int r, g, b, tr, tg, tb, i;
355
 
 
356
 
                i = (color_prom[j] >> 3) & 0x01;
357
 
                //i = color_prom[j];
358
 
 
359
 
                /* red component */
360
 
                tr = 0xf0 - (0xf0 * ((color_prom[j] >> 0) & 0x01));
361
 
                r = tr - (i * (tr / 5));
362
 
 
363
 
                /* green component */
364
 
                tg = 0xf0 - (0xf0 * ((color_prom[j] >> 1) & 0x01));
365
 
                g = tg - (i * (tg / 5));
366
 
 
367
 
                /* blue component */
368
 
                tb = 0xf0 - (0xf0 * ((color_prom[j] >> 2) & 0x01));
369
 
                b = tb - (i * (tb / 5));
370
 
 
371
 
                palette_set_color(machine, j, MAKE_RGB(r, g, b));
372
 
        }
373
 
}
374
 
 
375
 
 
376
 
/*************************
377
 
*    Graphics Layouts    *
378
 
*************************/
379
 
 
380
 
static const gfx_layout charlayout =
381
 
{
382
 
        8,8,    /* 8x8 characters */
383
 
        RGN_FRAC(1,2), /* 512 characters */
384
 
        2,  /* 2 bitplanes */
385
 
        { 0, RGN_FRAC(1,2) },
386
 
        { STEP8(0,1) },
387
 
        { STEP8(0,8) },
388
 
        8*8
389
 
};
390
 
 
391
 
 
392
 
/******************************
393
 
* Graphics Decode Information *
394
 
******************************/
395
 
 
396
 
static GFXDECODE_START( drw80pkr )
397
 
        GFXDECODE_ENTRY( "gfx1", 0x00000, charlayout, 0, 16 )
398
 
GFXDECODE_END
399
 
 
400
 
 
401
 
/**************
402
 
* Driver Init *
403
 
***************/
404
 
 
405
 
static DRIVER_INIT( drw80pkr )
406
 
{
407
 
        memory_configure_bank(machine, "bank1", 0, 2, machine.region("maincpu")->base(), 0x1000);
408
 
}
409
 
 
410
 
 
411
 
/*************************
412
 
* Memory map information *
413
 
*************************/
414
 
 
415
 
static ADDRESS_MAP_START( drw80pkr_map, AS_PROGRAM, 8 )
416
 
        AM_RANGE(0x0000, 0x1fff) AM_ROMBANK("bank1")
417
 
ADDRESS_MAP_END
418
 
 
419
 
static ADDRESS_MAP_START( drw80pkr_io_map, AS_IO, 8 )
420
 
        AM_RANGE(0x00, 0xff) AM_READWRITE(drw80pkr_io_r, drw80pkr_io_w)
421
 
        AM_RANGE(MCS48_PORT_T0,   MCS48_PORT_T0) AM_READWRITE(t0_r, t0_w)
422
 
        AM_RANGE(MCS48_PORT_T1,   MCS48_PORT_T1) AM_READWRITE(t1_r, t1_w)
423
 
        AM_RANGE(MCS48_PORT_P0,   MCS48_PORT_P0) AM_READWRITE(p0_r, p0_w)
424
 
        AM_RANGE(MCS48_PORT_P1,   MCS48_PORT_P1) AM_READWRITE(p1_r, p1_w)
425
 
        AM_RANGE(MCS48_PORT_P2,   MCS48_PORT_P2) AM_READWRITE(p2_r, p2_w)
426
 
        AM_RANGE(MCS48_PORT_PROG, MCS48_PORT_PROG) AM_RAM_WRITE(prog_w)
427
 
    AM_RANGE(MCS48_PORT_BUS,  MCS48_PORT_BUS) AM_READWRITE(bus_r, bus_w)
428
 
ADDRESS_MAP_END
429
 
 
430
 
/*************************
431
 
*      Input ports       *
432
 
*************************/
433
 
 
434
 
static INPUT_PORTS_START( drw80pkr )
435
 
        // Unknown at this time
436
 
        // These are temporary buttons for testing only
437
 
        PORT_START("IN0")
438
 
        PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_GAMBLE_DOOR ) PORT_TOGGLE
439
 
        PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_GAMBLE_BOOK ) PORT_NAME("Books")
440
 
        PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(2)
441
 
        PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_START1 ) PORT_NAME("Start")
442
 
        PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OTHER ) PORT_NAME("Discard") PORT_CODE(KEYCODE_2)
443
 
        PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_POKER_CANCEL )
444
 
        PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_POKER_HOLD1 )
445
 
        PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_POKER_HOLD2 )
446
 
 
447
 
        PORT_START("IN1")
448
 
        PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_POKER_HOLD3 )
449
 
        PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_POKER_HOLD4 )
450
 
        PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_POKER_HOLD5 )
451
 
        PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED )
452
 
        PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OTHER) PORT_NAME("Hopper") PORT_TOGGLE PORT_CODE(KEYCODE_H)
453
 
        PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_GAMBLE_PAYOUT)
454
 
        PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_UNUSED )
455
 
        PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
456
 
INPUT_PORTS_END
457
 
 
458
 
/*************************
459
 
*     Machine Driver     *
460
 
*************************/
461
 
 
462
 
static MACHINE_CONFIG_START( drw80pkr, drw80pkr_state )
463
 
        // basic machine hardware
464
 
        MCFG_CPU_ADD("maincpu", I8039, CPU_CLOCK)
465
 
        MCFG_CPU_PROGRAM_MAP(drw80pkr_map)
466
 
    MCFG_CPU_IO_MAP(drw80pkr_io_map)
467
 
        MCFG_CPU_VBLANK_INT("screen", irq0_line_hold)
468
 
 
469
 
        MCFG_MACHINE_START(drw80pkr)
470
 
 
471
 
        // video hardware
472
 
 
473
 
        MCFG_SCREEN_ADD("screen", RASTER)
474
 
        MCFG_SCREEN_REFRESH_RATE(60)
475
 
        MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
476
 
        MCFG_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
477
 
        MCFG_SCREEN_SIZE((31+1)*8, (31+1)*8)
478
 
        MCFG_SCREEN_VISIBLE_AREA(0*8, 24*8-1, 0*8, 27*8-1)
479
 
        MCFG_SCREEN_UPDATE(drw80pkr)
480
 
 
481
 
        MCFG_GFXDECODE(drw80pkr)
482
 
        MCFG_PALETTE_LENGTH(16*16)
483
 
 
484
 
        MCFG_PALETTE_INIT(drw80pkr)
485
 
        MCFG_VIDEO_START(drw80pkr)
486
 
 
487
 
        MCFG_NVRAM_ADD_0FILL("nvram")
488
 
 
489
 
        // sound hardware
490
 
        MCFG_SPEAKER_STANDARD_MONO("mono")
491
 
 
492
 
        MCFG_SOUND_ADD("aysnd", AY8912, 20000000/12)
493
 
        MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.75)
494
 
MACHINE_CONFIG_END
495
 
 
496
 
/*************************
497
 
*        Rom Load        *
498
 
*************************/
499
 
 
500
 
ROM_START( drw80pkr )
501
 
        ROM_REGION( 0x2000, "maincpu", 0 )
502
 
        ROM_LOAD( "pm0.u81",   0x0000, 0x1000, CRC(73223555) SHA1(229999ec00a1353f0d4928c65c8975079060c5af) )
503
 
        ROM_LOAD( "pm1.u82",   0x1000, 0x1000, CRC(f8158f2b) SHA1(da3b30cfd49cd0e8a48d78fd3f82b2b4ab33670c) )
504
 
 
505
 
        ROM_REGION( 0x002000, "gfx1", 0 )
506
 
        ROM_LOAD( "cg0-a.u74",   0x0000, 0x1000, CRC(0eefe598) SHA1(ed10aac345b10e35fb15babdd3ac30ebe2b8fc0f) )
507
 
        ROM_LOAD( "cg1-a.u76",   0x1000, 0x1000, CRC(522a96d0) SHA1(48f855a132413493353fbf6a44a1feb34ae6726d) )
508
 
 
509
 
        ROM_REGION( 0x100, "proms", 0 )
510
 
        ROM_LOAD( "cap13.u92", 0x0000, 0x0100, CRC(be67a8d9) SHA1(24b8cd19a5ec09779a737f6fc8c07b44f1226c8f) )
511
 
ROM_END
512
 
 
513
 
ROM_START( drw80pk2 )
514
 
        ROM_REGION( 0x2000, "maincpu", 0 )
515
 
        ROM_LOAD( "pm0.u81",   0x0000, 0x1000, CRC(0f3e97d2) SHA1(aa9e4015246284f32435d7320de667e075412e5b) )
516
 
        ROM_LOAD( "pm1.u82",   0x1000, 0x1000, CRC(5a6ad467) SHA1(0128bd70b65244a0f68031d5f451bf115eeb7609) )
517
 
 
518
 
        ROM_REGION( 0x002000, "gfx1", 0 )
519
 
        ROM_LOAD( "cg0-a.u74",   0x0000, 0x1000, CRC(97f5eb92) SHA1(f6c7bb42ccef8a78e8d56104ad942ae5b8e5b0df) )
520
 
        ROM_LOAD( "cg1-a.u76",   0x1000, 0x1000, CRC(2a3a750d) SHA1(db6183d11b2865b011c3748dc472cf5858dde78f) )
521
 
 
522
 
        ROM_REGION( 0x100, "proms", 0 )
523
 
        ROM_LOAD( "cap13.u92", 0x0000, 0x0100, CRC(be67a8d9) SHA1(24b8cd19a5ec09779a737f6fc8c07b44f1226c8f) )
524
 
ROM_END
525
 
 
526
 
/*************************
527
 
*      Game Drivers      *
528
 
*************************/
529
 
 
530
 
/*    YEAR  NAME      PARENT  MACHINE   INPUT     INIT      ROT    COMPANY                                  FULLNAME                FLAGS   */
531
 
GAME( 1982, drw80pkr, 0,      drw80pkr, drw80pkr, drw80pkr, ROT0,  "IGT - International Gaming Technology", "Draw 80 Poker",        GAME_NOT_WORKING )
532
 
GAME( 1983, drw80pk2, 0,      drw80pkr, drw80pkr, drw80pkr, ROT0,  "IGT - International Gaming Technology", "Draw 80 Poker - Minn", GAME_NOT_WORKING )