1
/***********************************************************************
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Functions to emulate general aspects of the machine (RAM, ROM,
8
***********************************************************************/
13
#include "includes/z80ne.h"
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#include "machine/ay31015.h"
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#include "machine/kr2376.h"
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#include "video/m6847.h"
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#include "machine/wd17xx.h"
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#include "imagedev/cassette.h"
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#include "imagedev/flopdrv.h"
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#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
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/* timer to read cassette waveforms */
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static cassette_image_device *cassette_device_image(running_machine &machine)
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z80ne_state *state = machine.driver_data<z80ne_state>();
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if (state->m_lx385_ctrl & 0x08)
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return machine.device<cassette_image_device>(CASSETTE2_TAG);
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return machine.device<cassette_image_device>(CASSETTE_TAG);
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static TIMER_CALLBACK(z80ne_cassette_tc)
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z80ne_state *state = machine.driver_data<z80ne_state>();
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state->m_cass_data.input.length++;
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cass_ws = ((cassette_device_image(machine))->input() > +0.02) ? 1 : 0;
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if ((cass_ws ^ state->m_cass_data.input.level) & cass_ws)
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state->m_cass_data.input.level = cass_ws;
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state->m_cass_data.input.bit = ((state->m_cass_data.input.length < state->m_cass_data.wave_filter) || (state->m_cass_data.input.length > 0x20)) ? 1 : 0;
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state->m_cass_data.input.length = 0;
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ay31015_set_input_pin( state->m_ay31015, AY31015_SI, state->m_cass_data.input.bit );
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state->m_cass_data.input.level = cass_ws;
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/* saving a tape - convert the serial stream from the uart */
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state->m_cass_data.output.length--;
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if (!(state->m_cass_data.output.length))
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if (state->m_cass_data.output.level)
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state->m_cass_data.output.level = 0;
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state->m_cass_data.output.level=1;
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cass_ws = ay31015_get_output_pin( state->m_ay31015, AY31015_SO );
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state->m_cass_data.wave_length = cass_ws ? state->m_cass_data.wave_short : state->m_cass_data.wave_long;
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cassette_device_image(machine)->output(state->m_cass_data.output.level ? -1.0 : +1.0);
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state->m_cass_data.output.length = state->m_cass_data.wave_length;
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/* first two entries point to rom on reset */
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UINT8 *RAM = machine.region("z80ne")->base();
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memory_configure_bank(machine, "bank1", 0, 1, &RAM[0x00000], 0x0400); /* RAM at 0x0000 */
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memory_configure_bank(machine, "bank1", 1, 1, &RAM[0x14000], 0x0400); /* ep382 at 0x0000 */
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memory_configure_bank(machine, "bank2", 0, 1, &RAM[0x14000], 0x0400); /* ep382 at 0x8000 */
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DRIVER_INIT_CALL(z80ne);
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DRIVER_INIT( z80netb )
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DRIVER_INIT( z80netf )
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/* first two entries point to rom on reset */
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UINT8 *RAM = machine.region("z80ne")->base();
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memory_configure_bank(machine, "bank1", 0, 1, &RAM[0x00000], 0x0400); /* RAM at 0x0000-0x03FF */
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memory_configure_bank(machine, "bank1", 1, 3, &RAM[0x14400], 0x0400); /* ep390, ep1390, ep2390 at 0x0000-0x03FF */
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memory_configure_bank(machine, "bank1", 4, 1, &RAM[0x14000], 0x0400); /* ep382 at 0x0000-0x03FF */
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memory_configure_bank(machine, "bank1", 5, 1, &RAM[0x10000], 0x0400); /* ep548 at 0x0000-0x03FF */
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memory_configure_bank(machine, "bank2", 0, 1, &RAM[0x00400], 0x3C00); /* RAM at 0x0400 */
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memory_configure_bank(machine, "bank2", 1, 1, &RAM[0x10400], 0x3C00); /* ep548 at 0x0400-0x3FFF */
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memory_configure_bank(machine, "bank3", 0, 1, &RAM[0x08000], 0x0400); /* RAM at 0x8000 */
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memory_configure_bank(machine, "bank3", 1, 1, &RAM[0x14000], 0x0400); /* ep382 at 0x8000 */
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memory_configure_bank(machine, "bank4", 0, 1, &RAM[0x0F000], 0x0400); /* RAM at 0xF000 */
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memory_configure_bank(machine, "bank4", 1, 3, &RAM[0x14400], 0x0400); /* ep390, ep1390, ep2390 at 0xF000 */
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static TIMER_CALLBACK( z80ne_kbd_scan )
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z80ne_state *state = machine.driver_data<z80ne_state>();
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* NE555 is connected to a 74LS93 binary counter
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* QA-QC: column index for LEDs and keyboard
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* QD: keyboard row select
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* Port F0 input bit assignment:
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* 0 QA bits 0..3 of row counter
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* 4 Control button pressed, active high
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* 7 Selected button pressed, active low
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--state->m_lx383_scan_counter;
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state->m_lx383_scan_counter &= 0x0f;
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if ( --state->m_lx383_downsampler == 0 )
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state->m_lx383_downsampler = LX383_DOWNSAMPLING;
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key_bits = (input_port_read(machine, "ROW1") << 8) | input_port_read(machine, "ROW0");
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// rst = input_port_read(machine, "RST");
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ctrl = input_port_read(machine, "CTRL");
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for ( i = 0; i<LX383_KEYS; i++)
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state->m_lx383_key[i] = ( i | (key_bits & 0x01 ? 0x80 : 0x00) | ~ctrl);
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DIRECT_UPDATE_HANDLER( z80ne_default )
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* Handle NMI delay for single step instruction
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DIRECT_UPDATE_HANDLER( z80ne_nmi_delay_count )
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z80ne_state *state = machine.driver_data<z80ne_state>();
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state->m_nmi_delay_counter--;
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if (!state->m_nmi_delay_counter)
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machine.device("z80ne")->memory().space(AS_PROGRAM)->set_direct_update_handler(direct_update_delegate(FUNC(z80ne_default), &machine));
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cputag_set_input_line(machine, "z80ne", INPUT_LINE_NMI, PULSE_LINE);
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* Handle delayed ROM/RAM banking at RESET
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* after the first reset_delay_counter bytes have been read from ROM, switch the RAM back in
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DIRECT_UPDATE_HANDLER( z80ne_reset_delay_count )
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z80ne_state *state = machine.driver_data<z80ne_state>();
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address_space *space = machine.device("z80ne")->memory().space(AS_PROGRAM);
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* TODO: when debugger is active, his memory access causes this callback
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if(!space->debugger_access())
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state->m_reset_delay_counter--;
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if (!state->m_reset_delay_counter)
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/* remove this callback */
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machine.device("z80ne")->memory().space(AS_PROGRAM)->set_direct_update_handler(direct_update_delegate(FUNC(z80ne_default), &machine));
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/* and switch to RAM bank at address 0x0000 */
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memory_set_bank( machine, "bank1", 0 ); /* RAM at 0x0000 (bank 1) */
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static void reset_lx388(running_machine &machine)
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z80ne_state *state = machine.driver_data<z80ne_state>();
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state->m_lx388_kr2376 = machine.device("lx388_kr2376");
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kr2376_set_input_pin( state->m_lx388_kr2376, KR2376_DSII, 0);
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kr2376_set_input_pin( state->m_lx388_kr2376, KR2376_PII, 0);
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static void reset_lx382_banking(running_machine &machine)
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z80ne_state *state = machine.driver_data<z80ne_state>();
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address_space *space = machine.device("z80ne")->memory().space(AS_PROGRAM);
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/* switch to ROM bank at address 0x0000 */
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memory_set_bank(machine, "bank1", 1);
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memory_set_bank(machine, "bank2", 0); /* ep382 at 0x8000 */
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/* after the first 3 bytes have been read from ROM, switch the RAM back in */
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state->m_reset_delay_counter = 2;
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space->set_direct_update_handler(direct_update_delegate(FUNC(z80ne_reset_delay_count), &machine));
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static void reset_lx390_banking(running_machine &machine)
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z80ne_state *state = machine.driver_data<z80ne_state>();
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address_space *space = machine.device("z80ne")->memory().space(AS_PROGRAM);
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state->m_reset_delay_counter = 0;
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switch (input_port_read(machine, "CONFIG") & 0x07) {
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case 0x01: /* EP382 Hex Monitor */
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logerror("reset_lx390_banking: banking ep382\n");
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memory_set_bank(machine, "bank1", 4); /* ep382 at 0x0000 for 3 cycles, then RAM */
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memory_set_bank(machine, "bank2", 0); /* RAM at 0x0400 */
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memory_set_bank(machine, "bank3", 1); /* ep382 at 0x8000 */
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memory_set_bank(machine, "bank4", 0); /* RAM at 0xF000 */
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/* after the first 3 bytes have been read from ROM, switch the RAM back in */
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state->m_reset_delay_counter = 2;
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space->set_direct_update_handler(direct_update_delegate(FUNC(z80ne_reset_delay_count), &machine));
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case 0x02: /* EP548 16k BASIC */
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logerror("reset_lx390_banking: banking ep548\n");
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memory_set_bank(machine, "bank1", 5); /* ep548 at 0x0000-0x03FF */
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memory_set_bank(machine, "bank2", 1); /* ep548 at 0x0400-0x3FFF */
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memory_set_bank(machine, "bank3", 0); /* RAM at 0x8000 */
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memory_set_bank(machine, "bank4", 0); /* RAM at 0xF000 */
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machine.device("z80ne")->memory().space(AS_PROGRAM)->set_direct_update_handler(direct_update_delegate(FUNC(z80ne_default), &machine));
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case 0x03: /* EP390 Boot Loader for 5.5k floppy BASIC */
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logerror("reset_lx390_banking: banking ep390\n");
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memory_set_bank(machine, "bank1", 1); /* ep390 at 0x0000-0 x03FF for 3 cycles, then RAM */
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memory_set_bank(machine, "bank2", 0); /* RAM at 0x0400-0x3FFF */
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memory_set_bank(machine, "bank3", 0); /* RAM at 0x8000 */
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memory_set_bank(machine, "bank4", 1); /* ep390 at 0xF000 */
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machine.device("z80ne")->memory().space(AS_PROGRAM)->set_direct_update_handler(direct_update_delegate(FUNC(z80ne_default), &machine));
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case 0x04: /* EP1390 Boot Loader for NE DOS 1.0/1.5 */
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logerror("reset_lx390_banking: banking ep1390\n");
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memory_set_bank(machine, "bank1", 2); /* ep1390 at 0x0000-0x03FF for 3 cycles, then RAM */
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memory_set_bank(machine, "bank2", 0); /* RAM at 0x0400-0x3FFF */
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memory_set_bank(machine, "bank3", 0); /* RAM at 0x8000 */
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memory_set_bank(machine, "bank4", 2); /* ep1390 at 0xF000 */
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machine.device("z80ne")->memory().space(AS_PROGRAM)->set_direct_update_handler(direct_update_delegate(FUNC(z80ne_default), &machine));
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case 0x05: /* EP2390 Boot Loader for NE DOS G.1 */
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logerror("reset_lx390_banking: banking ep2390\n");
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memory_set_bank(machine, "bank1", 3); /* ep2390 at 0x0000-0x03FF for 3 cycles, then RAM */
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memory_set_bank(machine, "bank2", 0); /* RAM at 0x0400-0x3FFF */
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memory_set_bank(machine, "bank3", 0); /* RAM at 0x8000 */
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memory_set_bank(machine, "bank4", 3); /* ep2390 at 0xF000 */
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machine.device("z80ne")->memory().space(AS_PROGRAM)->set_direct_update_handler(direct_update_delegate(FUNC(z80ne_default), &machine));
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/* TODO: in real hardware the ENH bus line is pulled down
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* until a I/O read is performed on a address with A0 address bit low and A1 or A2 address bit high
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static MACHINE_RESET(z80ne_base)
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z80ne_state *state = machine.driver_data<z80ne_state>();
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address_space *space = machine.device("z80ne")->memory().space(AS_PROGRAM);
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LOG(("In MACHINE_RESET z80ne_base\n"));
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for ( i=0; i<LX383_KEYS; i++)
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state->m_lx383_key[i] = 0xf0 | i;
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state->m_lx383_scan_counter = 0x0f;
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state->m_lx383_downsampler = LX383_DOWNSAMPLING;
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/* Initialize cassette interface */
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switch(input_port_read(machine, "LX.385") & 0x07)
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state->m_cass_data.speed = TAPE_300BPS;
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state->m_cass_data.wave_filter = LX385_TAPE_SAMPLE_FREQ / 1600;
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state->m_cass_data.wave_short = LX385_TAPE_SAMPLE_FREQ / (2400 * 2);
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state->m_cass_data.wave_long = LX385_TAPE_SAMPLE_FREQ / (1200 * 2);
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state->m_cass_data.speed = TAPE_600BPS;
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state->m_cass_data.wave_filter = LX385_TAPE_SAMPLE_FREQ / 3200;
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state->m_cass_data.wave_short = LX385_TAPE_SAMPLE_FREQ / (4800 * 2);
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state->m_cass_data.wave_long = LX385_TAPE_SAMPLE_FREQ / (2400 * 2);
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state->m_cass_data.speed = TAPE_1200BPS;
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state->m_cass_data.wave_filter = LX385_TAPE_SAMPLE_FREQ / 6400;
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state->m_cass_data.wave_short = LX385_TAPE_SAMPLE_FREQ / (9600 * 2);
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state->m_cass_data.wave_long = LX385_TAPE_SAMPLE_FREQ / (4800 * 2);
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state->m_cass_data.wave_length = state->m_cass_data.wave_short;
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state->m_cass_data.output.length = state->m_cass_data.wave_length;
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state->m_cass_data.output.level = 1;
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state->m_cass_data.input.length = 0;
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state->m_cass_data.input.bit = 1;
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state->m_ay31015 = machine.device("ay_3_1015");
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ay31015_set_input_pin( state->m_ay31015, AY31015_CS, 0 );
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ay31015_set_input_pin( state->m_ay31015, AY31015_NB1, 1 );
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ay31015_set_input_pin( state->m_ay31015, AY31015_NB2, 1 );
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ay31015_set_input_pin( state->m_ay31015, AY31015_TSB, 1 );
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ay31015_set_input_pin( state->m_ay31015, AY31015_EPS, 1 );
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ay31015_set_input_pin( state->m_ay31015, AY31015_NP, input_port_read(machine, "LX.385") & 0x80 ? 1 : 0 );
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ay31015_set_input_pin( state->m_ay31015, AY31015_CS, 1 );
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ay31015_set_receiver_clock( state->m_ay31015, state->m_cass_data.speed * 16.0);
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ay31015_set_transmitter_clock( state->m_ay31015, state->m_cass_data.speed * 16.0);
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state->m_nmi_delay_counter = 0;
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lx385_ctrl_w(space, 0, 0);
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LOG(("In MACHINE_RESET z80ne\n"));
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reset_lx382_banking(machine);
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MACHINE_RESET_CALL( z80ne_base );
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MACHINE_RESET(z80net)
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LOG(("In MACHINE_RESET z80net\n"));
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MACHINE_RESET_CALL( z80ne );
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reset_lx388(machine);
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MACHINE_RESET(z80netb)
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LOG(("In MACHINE_RESET z80netb\n"));
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MACHINE_RESET_CALL( z80ne_base );
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reset_lx388(machine);
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MACHINE_RESET(z80netf)
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LOG(("In MACHINE_RESET z80netf\n"));
371
reset_lx390_banking(machine);
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MACHINE_RESET_CALL( z80ne_base );
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reset_lx388(machine);
376
INPUT_CHANGED( z80ne_reset )
379
rst = input_port_read(field.machine(), "RST");
383
running_machine &machine = field.machine();
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machine.schedule_soft_reset();
388
INPUT_CHANGED( z80ne_nmi )
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nmi = input_port_read(field.machine(), "LX388_BRK");
395
cputag_set_input_line(field.machine(), "z80ne", INPUT_LINE_NMI, PULSE_LINE);
399
MACHINE_START( z80ne )
401
z80ne_state *state = machine.driver_data<z80ne_state>();
402
LOG(("In MACHINE_START z80ne\n"));
403
state->m_lx385_ctrl = 0x1f;
404
state_save_register_item( machine, "z80ne", NULL, 0, state->m_lx383_scan_counter );
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state_save_register_item( machine, "z80ne", NULL, 0, state->m_lx383_downsampler );
406
state_save_register_item_array( machine, "z80ne", NULL, 0, state->m_lx383_key );
407
state_save_register_item( machine, "z80ne", NULL, 0, state->m_nmi_delay_counter );
408
state->m_cassette_timer = machine.scheduler().timer_alloc(FUNC(z80ne_cassette_tc));
409
machine.scheduler().timer_pulse( attotime::from_hz(1000), FUNC(z80ne_kbd_scan));
412
MACHINE_START( z80net )
414
MACHINE_START_CALL( z80ne );
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LOG(("In MACHINE_START z80net\n"));
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MACHINE_START( z80netb )
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MACHINE_START_CALL( z80net );
421
LOG(("In MACHINE_START z80netb\n"));
424
MACHINE_START( z80netf )
426
MACHINE_START_CALL( z80net );
427
LOG(("In MACHINE_START z80netf\n"));
430
/******************************************************************************
432
******************************************************************************/
434
/* LX.383 - LX.384 HEX keyboard and display */
435
READ8_HANDLER( lx383_r )
437
z80ne_state *state = space->machine().driver_data<z80ne_state>();
441
* IC14 NE555 astable oscillator
442
* IC13 74LS93 binary counter
443
* IC5 74LS240 tri-state buffer
445
* l'oscillatore NE555 alimenta il clock del contatore 74LS93
447
* D1 - Q(B) |-- column
455
return state->m_lx383_key[state->m_lx383_scan_counter];
458
WRITE8_HANDLER( lx383_w )
460
z80ne_state *state = space->machine().driver_data<z80ne_state>();
462
* First 8 locations (F0-F7) are mapped to a dual-port 8-byte RAM
463
* The 1KHz NE-555 astable oscillator circuit drive
464
* a 4-bit 74LS93 binary counter.
465
* The 3 least sigificant bits of the counter are connected
466
* both to the read addres of the dual-port ram and to
467
* a 74LS156 3 to 8 binary decoder driving the cathode
468
* of 8 7-segments LEDS.
469
* The data output of the dual-port ram drive the anodes
470
* of the LEDS through 74LS07 buffers.
471
* LED segments - dual-port RAM bit:
479
* P 0x80 (represented by DP in original schematics)
481
* A write in the range F0-FF starts a 74LS90 counter
482
* that trigger the NMI line of the CPU afther 2 instruction
483
* fetch cycles for single step execution.
487
output_set_digit_value( offset, data ^ 0xff );
489
/* after writing to port 0xF8 and the first ~M1 cycles strike a NMI for single step execution */
490
state->m_nmi_delay_counter = 1;
491
space->machine().device("z80ne")->memory().space(AS_PROGRAM)->set_direct_update_handler(direct_update_delegate(FUNC(z80ne_nmi_delay_count), &space->machine()));
495
/* LX.385 Cassette tape interface */
497
* NE555 is connected to a 74LS93 binary counter
499
* QA-QC: colum index for LEDs and keyboard
500
* QD: keyboard row select
502
* Port EE: UART Data Read/Write
503
* Port EF: Status/Control
504
* read, UART status bits read
508
* 3 TBMT Transmitter Buffer Empty
509
* 4 DAV Data Available
510
* 5 EOC End Of Character
513
* write, UART control bits / Tape Unit select / Modulation control
514
* 0 bit1=0, bit0=0 UART Reset pulse
515
* 1 bit1=0, bit0=1 UART RDAV (Reset Data Available) pulse
516
* 2 Tape modulation enable
517
* 3 *TAPEA Enable (active low) (at reset: low)
518
* 4 *TAPEB Enable (active low) (at reset: low)
519
* Cassette is connected to the uart data input and output via the cassette
520
* interface hardware.
522
* The cassette interface hardware converts square-wave pulses into bits which the uart receives.
524
* 1. the cassette format: "frequency shift" is converted
525
into the uart data format "non-return to zero"
527
2. on cassette a 1 data bit is stored as 8 2400 Hz pulses
528
and a 0 data bit as 4 1200 Hz pulses
529
- At 1200 baud, a logic 1 is 1 cycle of 1200 Hz and a logic 0 is 1/2 cycle of 600 Hz.
530
- At 300 baud, a logic 1 is 8 cycles of 2400 Hz and a logic 0 is 4 cycles of 1200 Hz.
532
Attenuation is applied to the signal and the square wave edges are rounded.
534
A manchester encoder is used. A flip-flop synchronises input
535
data on the positive-edge of the clock pulse.
538
READ8_HANDLER(lx385_data_r)
540
z80ne_state *state = space->machine().driver_data<z80ne_state>();
541
return ay31015_get_received_data( state->m_ay31015 );
544
READ8_HANDLER(lx385_ctrl_r)
546
z80ne_state *state = space->machine().driver_data<z80ne_state>();
547
/* set unused bits high */
550
ay31015_set_input_pin( state->m_ay31015, AY31015_SWE, 0 );
551
data |= (ay31015_get_output_pin( state->m_ay31015, AY31015_OR ) ? 0x01 : 0);
552
data |= (ay31015_get_output_pin( state->m_ay31015, AY31015_FE ) ? 0x02 : 0);
553
data |= (ay31015_get_output_pin( state->m_ay31015, AY31015_PE ) ? 0x04 : 0);
554
data |= (ay31015_get_output_pin( state->m_ay31015, AY31015_TBMT ) ? 0x08 : 0);
555
data |= (ay31015_get_output_pin( state->m_ay31015, AY31015_DAV ) ? 0x10 : 0);
556
data |= (ay31015_get_output_pin( state->m_ay31015, AY31015_EOC ) ? 0x20 : 0);
557
ay31015_set_input_pin( state->m_ay31015, AY31015_SWE, 1 );
562
WRITE8_HANDLER(lx385_data_w)
564
z80ne_state *state = space->machine().driver_data<z80ne_state>();
565
ay31015_set_transmit_data( state->m_ay31015, data );
568
#define LX385_CASSETTE_MOTOR_MASK ((1<<3)|(1<<4))
570
WRITE8_HANDLER(lx385_ctrl_w)
572
z80ne_state *state = space->machine().driver_data<z80ne_state>();
573
/* Translate data to control signals
574
* 0 bit1=0, bit0=0 UART Reset pulse
575
* 1 bit1=0, bit0=1 UART RDAV (Reset Data Available) pulse
576
* 2 UART Tx Clock Enable (active high)
577
* 3 *TAPEA Enable (active low) (at reset: low)
578
* 4 *TAPEB Enable (active low) (at reset: low)
580
UINT8 uart_reset, uart_rdav, uart_tx_clock;
581
UINT8 motor_a, motor_b;
582
UINT8 changed_bits = (state->m_lx385_ctrl ^ data) & 0x1C;
583
state->m_lx385_ctrl = data;
585
uart_reset = ((data & 0x03) == 0x00);
586
uart_rdav = ((data & 0x03) == 0x01);
587
uart_tx_clock = ((data & 0x04) == 0x04);
588
motor_a = ((data & 0x08) == 0x00);
589
motor_b = ((data & 0x10) == 0x00);
591
/* UART Reset and RDAV */
594
ay31015_set_input_pin( state->m_ay31015, AY31015_XR, 1 );
595
ay31015_set_input_pin( state->m_ay31015, AY31015_XR, 0 );
600
ay31015_set_input_pin( state->m_ay31015, AY31015_RDAV, 1 );
601
ay31015_set_input_pin( state->m_ay31015, AY31015_RDAV, 0 );
604
if (!changed_bits) return;
606
/* UART Tx Clock enable/disable */
607
if(changed_bits & 0x04)
608
ay31015_set_transmitter_clock( state->m_ay31015, uart_tx_clock ? state->m_cass_data.speed * 16.0 : 0.0);
611
if(changed_bits & 0x18)
613
space->machine().device<cassette_image_device>(CASSETTE_TAG)->change_state(
614
(motor_a) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
616
space->machine().device<cassette_image_device>(CASSETTE2_TAG)->change_state(
617
(motor_b) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
619
if (motor_a || motor_b)
620
state->m_cassette_timer->adjust(attotime::zero, 0, attotime::from_hz(LX385_TAPE_SAMPLE_FREQ));
622
state->m_cassette_timer->adjust(attotime::zero);
626
READ8_DEVICE_HANDLER( lx388_mc6847_videoram_r )
628
z80ne_state *state = device->machine().driver_data<z80ne_state>();
629
UINT8 *videoram = state->m_videoram;
630
int d6 = BIT(videoram[offset], 6);
631
int d7 = BIT(videoram[offset], 7);
633
mc6847_inv_w(device, d6 && d7);
634
mc6847_as_w(device, !d6 && d7);
635
mc6847_intext_w(device, !d6 && d7);
637
return videoram[offset];
640
SCREEN_UPDATE( lx388 )
642
device_t *mc6847 = screen->machine().device("mc6847");
643
return mc6847_update(mc6847, bitmap, cliprect);
646
READ8_HANDLER(lx388_data_r)
648
z80ne_state *state = space->machine().driver_data<z80ne_state>();
651
data = kr2376_data_r(state->m_lx388_kr2376, 0) & 0x7f;
652
data |= kr2376_get_output_pin(state->m_lx388_kr2376, KR2376_SO) << 7;
656
READ8_HANDLER( lx388_read_field_sync )
658
device_t *mc6847 = space->machine().device("mc6847");
659
return mc6847_fs_r(mc6847) << 7;
663
* DRQ INTRQ IC9B.10 IC8B.*Q
671
WRITE8_DEVICE_HANDLER(lx390_motor_w)
673
z80ne_state *state = device->machine().driver_data<z80ne_state>();
674
/* Selection of drive and parameters
675
A write also causes the selected drive motor to turn on for about 3 seconds.
676
When the motor turns off, the drive is deselected.
677
d7 Unused (trs80: 1=MFM, 0=FM)
679
d5 0=Side 0, 1=Side 1 (trs80: 1=Write Precompensation enabled)
680
d4 Unused (trs80: 0=Side 0, 1=Side 1)
684
d0 1=select drive 0 */
700
state->m_wd17xx_state.head = (data & 32) ? 1 : 0;
701
state->m_wd17xx_state.drive = data & 0x0F;
703
/* no drive selected, turn off all leds */
704
if (!state->m_wd17xx_state.drive)
706
output_set_value("drv0", 0);
707
output_set_value("drv1", 0);
712
LOG(("lx390_motor_w, set drive %1d\n", drive));
713
wd17xx_set_drive(device,drive);
714
LOG(("lx390_motor_w, set side %1d\n", state->m_wd17xx_state.head));
715
wd17xx_set_side(device, state->m_wd17xx_state.head);
719
READ8_DEVICE_HANDLER(lx390_reset_bank)
723
/* if PC is not in range, we are under integrated debugger control, DON'T SWAP */
724
pc = cpu_get_pc(device->machine().device("z80ne"));
725
if((pc >= 0xf000) && (pc <=0xffff))
727
LOG(("lx390_reset_bank, reset memory bank 1\n"));
728
memory_set_bank(device->machine(), "bank1", 0); /* RAM at 0x0000 (bank 1) */
732
LOG(("lx390_reset_bank, bypass because in debugger\n"));
737
READ8_DEVICE_HANDLER(lx390_fdc_r)
744
d = wd17xx_status_r(device, 0) ^ 0xff;
745
LOG(("lx390_fdc_r, WD17xx status: %02x\n", d));
748
d = wd17xx_track_r(device, 0) ^ 0xff;
749
LOG(("lx390_fdc_r, WD17xx track: %02x\n", d));
752
d = wd17xx_sector_r(device, 0) ^ 0xff;
753
LOG(("lx390_fdc_r, WD17xx sector: %02x\n", d));
756
d = wd17xx_data_r(device, 0) ^ 0xff;
757
LOG(("lx390_fdc_r, WD17xx data3: %02x\n", d));
761
lx390_reset_bank(device, 0);
764
d = wd17xx_data_r(device, 3) ^ 0xff;
765
LOG(("lx390_fdc_r, WD17xx data7, force: %02x\n", d));
773
WRITE8_DEVICE_HANDLER(lx390_fdc_w)
775
z80ne_state *state = device->machine().driver_data<z80ne_state>();
782
LOG(("lx390_fdc_w, WD17xx command: %02x\n", d));
783
wd17xx_command_w(device, offset, d ^ 0xff);
784
if (state->m_wd17xx_state.drive & 1)
785
output_set_value("drv0", 2);
786
else if (state->m_wd17xx_state.drive & 2)
787
output_set_value("drv1", 2);
790
LOG(("lx390_fdc_w, WD17xx track: %02x\n", d));
791
wd17xx_track_w(device, offset, d ^ 0xff);
794
LOG(("lx390_fdc_w, WD17xx sector: %02x\n", d));
795
wd17xx_sector_w(device, offset, d ^ 0xff);
798
wd17xx_data_w(device, 0, d ^ 0xff);
799
LOG(("lx390_fdc_w, WD17xx data3: %02x\n", d));
802
LOG(("lx390_fdc_w, motor_w: %02x\n", d));
803
lx390_motor_w(device, 0, d);
806
LOG(("lx390_fdc_w, WD17xx data7, force: %02x\n", d));
807
wd17xx_data_w(device, 3, d ^ 0xff);