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Viewing changes to mess/src/mame/drivers/crystal.c

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Jordi Mallach, Emmanuel Kasper
  • Date: 2011-12-19 22:56:27 UTC
  • mfrom: (0.1.2)
  • Revision ID: package-import@ubuntu.com-20111219225627-ub5oga1oys4ogqzm
Tags: 0.144-1
http://bugs.debian.org/651538
[ Jordi Mallach ]
* Fix syntax errors in DEP5 copyright file (lintian).
* Use a versioned copyright Format specification field.
* Update Vcs-* URLs.
* Move transitional packages to the new metapackages section, and make
  them priority extra.
* Remove references to GNU/Linux and MESS sources from copyright.
* Add build variables for s390x.
* Use .xz tarballs as it cuts 4MB for the upstream sources.
* Add nplayers.ini as a patch. Update copyright file to add CC-BY-SA-3.0.

[ Emmanuel Kasper ]
* New upstream release. Closes: #651538.
* Add Free Desktop compliant png icons of various sizes taken from
  the hydroxygen iconset
* Mess is now built from a new source package, to avoid possible source
  incompatibilities between mame and the mess overlay.
* Mame-tools are not built from the mame source package anymore, but
  from the mess source package

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Lines of Context:
mess/src/mame/drivers/crystal.c
1
 
/*
2
 
    CRYSTAL SYSTEM by Brezzasoft (2001)
3
 
    using VRender0 System on a Chip
4
 
 
5
 
    The VRender0 (info at archive.org for http://www.mesdigital.com) chip contains:
6
 
        - CPU Core SE3208 (info at www.adc.co.kr) @ 43Mhz
7
 
        - 2 DMA chans
8
 
        - 4 Timers
9
 
        - 32 PIO pins
10
 
        - PWM output
11
 
        - 32 channels wavetable synth (8bit linear, 16bit linear and 8bit ulaw sample format)
12
 
        - Custom 2D video rendering device (texture mapping, alphablend, roz)
13
 
 
14
 
    The protection is a PIC deviced labeled SMART-IC in the rom board, I'm not sure how
15
 
    it exactly works, but it supplies some opcodes that have been replaced with garbage
16
 
    in the main program. I don't know if it traps reads and returns the correct ones when
17
 
    reading from flash, or if it's interfaced by the main program after copying the program
18
 
    from flash to ram and it provides the addresses and values to patch. I patch the flash
19
 
    program with the correct data
20
 
 
21
 
    MAME driver by ElSemi
22
 
 
23
 
The Crystal of Kings
24
 
Brezza Soft Corporation (Japan), 2001
25
 
 
26
 
This game runs on a small cartridge-based PCB known as the 'Crystal System'
27
 
There are only two known games running on this system, Crystal of Kings and Evolution Soccer.
28
 
The main PCB is small (approx 6" square) and contains only a few components. All of the processing
29
 
work is done by the large IC in the middle of the PCB. The system looks a bit like IGS's PGM System, in
30
 
that it's housed in a plastic case and has a single slot for insertion of a game cart. However this
31
 
system and the game carts are approx. half the size of the PGM carts.
32
 
On bootup, the screen is black and the system outputs a vertical white line on the right side of the screen.
33
 
The HSync is approx 20kHz, the screen is out of sync on a standard 15kHz arcade monitor.
34
 
After approx. 15-20 seconds, the screen changes to white and has some vertical stripes on it and the HSync
35
 
changes to 15kHz. After a few more seconds the game boots to a white screen and a blue 'Brezza Soft' logo.
36
 
Without a cart plugged in, the screen stays at the first vertical line screen.
37
 
 
38
 
Main PCB Layout
39
 
---------------
40
 
 
41
 
Brezza Soft MAGIC EYES AMG0110B
42
 
  |----------------------------------------------------|
43
 
  |TDA1519   VOL     3.6V_BATT  SW1 SW2 SW3            |
44
 
|-|                                                    |
45
 
|                              DS1233                  |
46
 
|                                                |---| |
47
 
|                                       GM76256  |   | |
48
 
|        DA1133A                        |-----|  |   | |
49
 
|                HY57V651620  32.768kHz |MX27L|  |   | |
50
 
|                               DS1302  |1000 |  |   | |
51
 
|J                  |-------------|     |-----|  |   | |
52
 
|A                  |             |LED1          |   | |
53
 
|M                  |             |LED2          |CN1| |
54
 
|M      HY57V651620 | VRENDERZERO |              |   | |
55
 
|A                  |             |              |   | |
56
 
|                   |             |              |   | |
57
 
|                   |-------------| HY57V651620  |   | |
58
 
|                                                |   | |
59
 
|              14.31818MHz                       |   | |
60
 
|                              PAL               |---| |
61
 
|                                    TD62003           |
62
 
|-|                                                    |
63
 
  | |---------------| DSW(8)                           |
64
 
  |-|     CN2       |----------------------------------|
65
 
    |---------------|
66
 
 
67
 
Notes:
68
 
      GM76C256   : Hyundai GM76C256 32k x8 SRAM (SOP28)
69
 
      MX27L1000  : Macronix MX27L1000QC-12 128k x8 EEPROM (BIOS, PLCC32)
70
 
      PAL        : Atmel ATF16V8-10PC PAL (DIP20)
71
 
      HY57V651620: Hyundai HY57V651620 4M x16 SDRAM (SSOP54)
72
 
      DA1311A    : Philips DA1311A DAC (SOIC8)
73
 
      DS1233     : Dallas DS1233 master reset IC (SOIC4)
74
 
      DS1302     : Dallas DS1302 real time clock IC (DIP8)
75
 
      VRENDERZERO: MESGraphics VRenderZERO (all-in-one main CPU/graphics/sound, QFP240)
76
 
      SW1        : Push button reset switch
77
 
      SW2        : Push button service switch
78
 
      SW3        : Push button test switch
79
 
      TDA1519    : Philips TDA1519 dual 6W stereo power amplifier (SIP9)
80
 
      VOL        : Master volume potentiometer
81
 
      3.6V_BATT  : 3.6 Volt NiCad battery 65mAh (for RTC)
82
 
      TD62003    : Toshiba TD62003 PNP 50V 0.5A quad darlington switch, for driving coin meters (DIP16)
83
 
      CN1        : PCI-type slot for extension riser board (for game cart connection at 90 degrees to the main PCB)
84
 
      CN2        : IDC 34-way flat cable connector (purpose unknown)
85
 
      VSync      : 60Hz
86
 
 
87
 
 
88
 
Game cart PCB
89
 
-------------
90
 
Cart sticker: 'THE CRYSTAL OF KINGS      BCSV0000'
91
 
PCB printing: Brezza Soft MAGIC EYES AMG0111B
92
 
|------------------------------|
93
 
|                              |
94
 
|PIC16xxx?                     |
95
 
|           U8   U7   U6   U5  |
96
 
|3.57945Mhz                    |
97
 
|                              |
98
 
|                              |
99
 
|                              |
100
 
|                              |
101
 
|74HC138                       |
102
 
|           U4   U3   U2   U1  |
103
 
|                              |
104
 
|                              |
105
 
|                              |
106
 
|-|                          |-|
107
 
  |--------------------------|
108
 
 
109
 
Notes:
110
 
      The cart PCB is single sided and contains only...
111
 
      1x 3.579545MHz crystal
112
 
      1x 74HC138 logic chip
113
 
      1x 18 pin unknown chip (DIP18, surface scratched but it's probably a PIC16xxx, labelled 'dgSMART-PR3 MAGIC EYES')
114
 
      3x Intel E28F128J3A 128MBit surface mounted FlashROMs (TSOP56, labelled 'BREZZASOFT BCSV0004Fxx', xx=01, 02, 03)
115
 
         Note: there are 8 spaces total for FlashROMs. Only U1, U2 & U3 are populated in this cart.
116
 
 
117
 
*/
118
 
 
119
 
#include "emu.h"
120
 
#include "cpu/se3208/se3208.h"
121
 
#include "video/vrender0.h"
122
 
#include "machine/ds1302.h"
123
 
#include "sound/vrender0.h"
124
 
#include "machine/nvram.h"
125
 
 
126
 
#define IDLE_LOOP_SPEEDUP
127
 
 
128
 
class crystal_state : public driver_device
129
 
{
130
 
public:
131
 
        crystal_state(const machine_config &mconfig, device_type type, const char *tag)
132
 
                : driver_device(mconfig, type, tag) { }
133
 
 
134
 
        /* memory pointers */
135
 
        UINT32 *  m_workram;
136
 
        UINT32 *  m_textureram;
137
 
        UINT32 *  m_frameram;
138
 
        UINT32 *  m_sysregs;
139
 
        UINT32 *  m_vidregs;
140
 
//  UINT32 *  m_nvram;    // currently this uses generic nvram handling
141
 
 
142
 
#ifdef IDLE_LOOP_SPEEDUP
143
 
        UINT8     m_FlipCntRead;
144
 
#endif
145
 
 
146
 
        UINT32    m_Bank;
147
 
        UINT8     m_FlipCount;
148
 
        UINT8     m_IntHigh;
149
 
        UINT32    m_Timerctrl[4];
150
 
        emu_timer *m_Timer[4];
151
 
        UINT32    m_FlashCmd;
152
 
        UINT32    m_PIO;
153
 
        UINT32    m_DMActrl[2];
154
 
        UINT8     m_OldPort4;
155
 
        UINT32    *m_ResetPatch;
156
 
 
157
 
        device_t *m_maincpu;
158
 
        device_t *m_ds1302;
159
 
        device_t *m_vr0video;
160
 
};
161
 
 
162
 
static void IntReq( running_machine &machine, int num )
163
 
{
164
 
        crystal_state *state = machine.driver_data<crystal_state>();
165
 
        address_space *space = state->m_maincpu->memory().space(AS_PROGRAM);
166
 
        UINT32 IntEn = space->read_dword(0x01800c08);
167
 
        UINT32 IntPend = space->read_dword(0x01800c0c);
168
 
        if (IntEn & (1 << num))
169
 
        {
170
 
                IntPend |= (1 << num);
171
 
                space->write_dword(0x01800c0c, IntPend);
172
 
                device_set_input_line(state->m_maincpu, SE3208_INT, ASSERT_LINE);
173
 
        }
174
 
#ifdef IDLE_LOOP_SPEEDUP
175
 
        state->m_FlipCntRead = 0;
176
 
        device_resume(state->m_maincpu, SUSPEND_REASON_SPIN);
177
 
#endif
178
 
}
179
 
 
180
 
static READ32_HANDLER( FlipCount_r )
181
 
{
182
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
183
 
 
184
 
#ifdef IDLE_LOOP_SPEEDUP
185
 
        UINT32 IntPend = space->read_dword(0x01800c0c);
186
 
        state->m_FlipCntRead++;
187
 
        if (state->m_FlipCntRead >= 16 && !IntPend && state->m_FlipCount != 0)
188
 
                device_suspend(state->m_maincpu, SUSPEND_REASON_SPIN, 1);
189
 
#endif
190
 
        return ((UINT32) state->m_FlipCount) << 16;
191
 
}
192
 
 
193
 
static WRITE32_HANDLER( FlipCount_w )
194
 
{
195
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
196
 
 
197
 
        if (mem_mask & 0x00ff0000)
198
 
        {
199
 
                int fc = (data >> 16) & 0xff;
200
 
                if (fc == 1)
201
 
                        state->m_FlipCount++;
202
 
                else if (fc == 0)
203
 
                        state->m_FlipCount = 0;
204
 
        }
205
 
}
206
 
 
207
 
static READ32_HANDLER( Input_r )
208
 
{
209
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
210
 
 
211
 
        if (offset == 0)
212
 
                return input_port_read(space->machine(), "P1_P2");
213
 
        else if (offset == 1)
214
 
                return input_port_read(space->machine(), "P3_P4");
215
 
        else if( offset == 2)
216
 
        {
217
 
                UINT8 Port4 = input_port_read(space->machine(), "SYSTEM");
218
 
                if (!(Port4 & 0x10) && ((state->m_OldPort4 ^ Port4) & 0x10))    //coin buttons trigger IRQs
219
 
                        IntReq(space->machine(), 12);
220
 
                if (!(Port4 & 0x20) && ((state->m_OldPort4 ^ Port4) & 0x20))
221
 
                        IntReq(space->machine(), 19);
222
 
                state->m_OldPort4 = Port4;
223
 
                return /*dips*/input_port_read(space->machine(), "DSW") | (Port4 << 16);
224
 
        }
225
 
        return 0;
226
 
}
227
 
 
228
 
static WRITE32_HANDLER( IntAck_w )
229
 
{
230
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
231
 
        UINT32 IntPend = space->read_dword(0x01800c0c);
232
 
 
233
 
        if (mem_mask & 0xff)
234
 
        {
235
 
                IntPend &= ~(1 << (data & 0x1f));
236
 
                space->write_dword(0x01800c0c, IntPend);
237
 
                if (!IntPend)
238
 
                        device_set_input_line(state->m_maincpu, SE3208_INT, CLEAR_LINE);
239
 
        }
240
 
        if (mem_mask & 0xff00)
241
 
                state->m_IntHigh = (data >> 8) & 7;
242
 
}
243
 
 
244
 
static IRQ_CALLBACK( icallback )
245
 
{
246
 
        crystal_state *state = device->machine().driver_data<crystal_state>();
247
 
        address_space *space = device->memory().space(AS_PROGRAM);
248
 
        UINT32 IntPend = space->read_dword(0x01800c0c);
249
 
        int i;
250
 
 
251
 
        for (i = 0; i < 32; ++i)
252
 
        {
253
 
                if (BIT(IntPend, i))
254
 
                {
255
 
                        return (state->m_IntHigh << 5) | i;
256
 
                }
257
 
        }
258
 
        return 0;               //This should never happen
259
 
}
260
 
 
261
 
static WRITE32_HANDLER( Banksw_w )
262
 
{
263
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
264
 
 
265
 
        state->m_Bank = (data >> 1) & 7;
266
 
        if (state->m_Bank <= 2)
267
 
                memory_set_bankptr(space->machine(), "bank1", space->machine().region("user1")->base() + state->m_Bank * 0x1000000);
268
 
        else
269
 
                memory_set_bankptr(space->machine(), "bank1", space->machine().region("user2")->base());
270
 
}
271
 
 
272
 
static TIMER_CALLBACK( Timercb )
273
 
{
274
 
        crystal_state *state = machine.driver_data<crystal_state>();
275
 
        int which = (int)(FPTR)ptr;
276
 
        static const int num[] = { 0, 1, 9, 10 };
277
 
 
278
 
        if (!(state->m_Timerctrl[which] & 2))
279
 
                state->m_Timerctrl[which] &= ~1;
280
 
 
281
 
        IntReq(machine, num[which]);
282
 
}
283
 
 
284
 
INLINE void Timer_w( address_space *space, int which, UINT32 data, UINT32 mem_mask )
285
 
{
286
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
287
 
 
288
 
        if (((data ^ state->m_Timerctrl[which]) & 1) && (data & 1))     //Timer activate
289
 
        {
290
 
                int PD = (data >> 8) & 0xff;
291
 
                int TCV = space->read_dword(0x01801404 + which * 8);
292
 
                attotime period = attotime::from_hz(43000000) * ((PD + 1) * (TCV + 1));
293
 
 
294
 
                if (state->m_Timerctrl[which] & 2)
295
 
                        state->m_Timer[which]->adjust(period, 0, period);
296
 
                else
297
 
                        state->m_Timer[which]->adjust(period);
298
 
        }
299
 
        COMBINE_DATA(&state->m_Timerctrl[which]);
300
 
}
301
 
 
302
 
static WRITE32_HANDLER( Timer0_w )
303
 
{
304
 
        Timer_w(space, 0, data, mem_mask);
305
 
}
306
 
 
307
 
static READ32_HANDLER( Timer0_r )
308
 
{
309
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
310
 
        return state->m_Timerctrl[0];
311
 
}
312
 
 
313
 
static WRITE32_HANDLER( Timer1_w )
314
 
{
315
 
        Timer_w(space, 1, data, mem_mask);
316
 
}
317
 
 
318
 
static READ32_HANDLER( Timer1_r )
319
 
{
320
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
321
 
        return state->m_Timerctrl[1];
322
 
}
323
 
 
324
 
static WRITE32_HANDLER( Timer2_w )
325
 
{
326
 
        Timer_w(space, 2, data, mem_mask);
327
 
}
328
 
 
329
 
static READ32_HANDLER( Timer2_r )
330
 
{
331
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
332
 
        return state->m_Timerctrl[2];
333
 
}
334
 
 
335
 
static WRITE32_HANDLER( Timer3_w )
336
 
{
337
 
        Timer_w(space, 3, data, mem_mask);
338
 
}
339
 
 
340
 
static READ32_HANDLER( Timer3_r )
341
 
{
342
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
343
 
        return state->m_Timerctrl[3];
344
 
}
345
 
 
346
 
static READ32_HANDLER( FlashCmd_r )
347
 
{
348
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
349
 
 
350
 
        if ((state->m_FlashCmd & 0xff) == 0xff)
351
 
        {
352
 
                if (state->m_Bank <= 2)
353
 
                {
354
 
                        UINT32 *ptr = (UINT32*)(space->machine().region("user1")->base() + state->m_Bank * 0x1000000);
355
 
                        return ptr[0];
356
 
                }
357
 
                else
358
 
                        return 0xffffffff;
359
 
        }
360
 
        if ((state->m_FlashCmd & 0xff) == 0x90)
361
 
        {
362
 
                if (state->m_Bank <= 2)
363
 
            return 0x00180089;  //Intel 128MBit
364
 
                else
365
 
                        return 0xffffffff;
366
 
        }
367
 
        return 0;
368
 
}
369
 
 
370
 
static WRITE32_HANDLER( FlashCmd_w )
371
 
{
372
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
373
 
        state->m_FlashCmd = data;
374
 
}
375
 
 
376
 
static READ32_HANDLER( PIO_r )
377
 
{
378
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
379
 
        return state->m_PIO;
380
 
}
381
 
 
382
 
static WRITE32_HANDLER( PIO_w )
383
 
{
384
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
385
 
        UINT32 RST = data & 0x01000000;
386
 
        UINT32 CLK = data & 0x02000000;
387
 
        UINT32 DAT = data & 0x10000000;
388
 
 
389
 
        if (!RST)
390
 
                state->m_ds1302->reset();
391
 
 
392
 
        ds1302_dat_w(state->m_ds1302, 0, DAT ? 1 : 0);
393
 
        ds1302_clk_w(state->m_ds1302, 0, CLK ? 1 : 0);
394
 
 
395
 
        if (ds1302_read(state->m_ds1302, 0))
396
 
                space->write_dword(0x01802008, space->read_dword(0x01802008) | 0x10000000);
397
 
        else
398
 
                space->write_dword(0x01802008, space->read_dword(0x01802008) & (~0x10000000));
399
 
 
400
 
        COMBINE_DATA(&state->m_PIO);
401
 
}
402
 
 
403
 
INLINE void DMA_w( address_space *space, int which, UINT32 data, UINT32 mem_mask )
404
 
{
405
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
406
 
 
407
 
        if (((data ^ state->m_DMActrl[which]) & (1 << 10)) && (data & (1 << 10)))       //DMAOn
408
 
        {
409
 
                UINT32 CTR = data;
410
 
                UINT32 SRC = space->read_dword(0x01800804 + which * 0x10);
411
 
                UINT32 DST = space->read_dword(0x01800808 + which * 0x10);
412
 
                UINT32 CNT = space->read_dword(0x0180080C + which * 0x10);
413
 
                int i;
414
 
 
415
 
                if (CTR & 0x2)  //32 bits
416
 
                {
417
 
                        for (i = 0; i < CNT; ++i)
418
 
                        {
419
 
                                UINT32 v = space->read_dword(SRC + i * 4);
420
 
                                space->write_dword(DST + i * 4, v);
421
 
                        }
422
 
                }
423
 
                else if (CTR & 0x1)     //16 bits
424
 
                {
425
 
                        for (i = 0; i < CNT; ++i)
426
 
                        {
427
 
                                UINT16 v = space->read_word(SRC + i * 2);
428
 
                                space->write_word(DST + i * 2, v);
429
 
                        }
430
 
                }
431
 
                else    //8 bits
432
 
                {
433
 
                        for (i = 0; i < CNT; ++i)
434
 
                        {
435
 
                                UINT8 v = space->read_byte(SRC + i);
436
 
                                space->write_byte(DST + i, v);
437
 
                        }
438
 
                }
439
 
                data &= ~(1 << 10);
440
 
                space->write_dword(0x0180080C + which * 0x10, 0);
441
 
                IntReq(space->machine(), 7 + which);
442
 
        }
443
 
        COMBINE_DATA(&state->m_DMActrl[which]);
444
 
}
445
 
 
446
 
static READ32_HANDLER( DMA0_r )
447
 
{
448
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
449
 
        return state->m_DMActrl[0];
450
 
}
451
 
 
452
 
static WRITE32_HANDLER( DMA0_w )
453
 
{
454
 
        DMA_w(space, 0, data, mem_mask);
455
 
}
456
 
 
457
 
static READ32_HANDLER( DMA1_r )
458
 
{
459
 
        crystal_state *state = space->machine().driver_data<crystal_state>();
460
 
        return state->m_DMActrl[1];
461
 
}
462
 
 
463
 
static WRITE32_HANDLER( DMA1_w )
464
 
{
465
 
        DMA_w(space, 1, data, mem_mask);
466
 
}
467
 
 
468
 
 
469
 
static ADDRESS_MAP_START( crystal_mem, AS_PROGRAM, 32 )
470
 
        AM_RANGE(0x00000000, 0x0001ffff) AM_ROM AM_WRITENOP
471
 
 
472
 
        AM_RANGE(0x01200000, 0x0120000f) AM_READ(Input_r)
473
 
        AM_RANGE(0x01280000, 0x01280003) AM_WRITE(Banksw_w)
474
 
        AM_RANGE(0x01400000, 0x0140ffff) AM_RAM AM_SHARE("nvram")
475
 
 
476
 
        AM_RANGE(0x01801400, 0x01801403) AM_READWRITE(Timer0_r, Timer0_w)
477
 
        AM_RANGE(0x01801408, 0x0180140b) AM_READWRITE(Timer1_r, Timer1_w)
478
 
        AM_RANGE(0x01801410, 0x01801413) AM_READWRITE(Timer2_r, Timer2_w)
479
 
        AM_RANGE(0x01801418, 0x0180141b) AM_READWRITE(Timer3_r, Timer3_w)
480
 
        AM_RANGE(0x01802004, 0x01802007) AM_READWRITE(PIO_r, PIO_w)
481
 
 
482
 
        AM_RANGE(0x01800800, 0x01800803) AM_READWRITE(DMA0_r, DMA0_w)
483
 
        AM_RANGE(0x01800810, 0x01800813) AM_READWRITE(DMA1_r, DMA1_w)
484
 
 
485
 
        AM_RANGE(0x01800c04, 0x01800c07) AM_WRITE(IntAck_w)
486
 
        AM_RANGE(0x01800000, 0x0180ffff) AM_RAM AM_BASE_MEMBER(crystal_state, m_sysregs)
487
 
        AM_RANGE(0x02000000, 0x027fffff) AM_RAM AM_BASE_MEMBER(crystal_state, m_workram)
488
 
 
489
 
        AM_RANGE(0x030000a4, 0x030000a7) AM_READWRITE(FlipCount_r, FlipCount_w)
490
 
 
491
 
        AM_RANGE(0x03000000, 0x0300ffff) AM_RAM AM_BASE_MEMBER(crystal_state, m_vidregs)
492
 
        AM_RANGE(0x03800000, 0x03ffffff) AM_RAM AM_BASE_MEMBER(crystal_state, m_textureram)
493
 
        AM_RANGE(0x04000000, 0x047fffff) AM_RAM AM_BASE_MEMBER(crystal_state, m_frameram)
494
 
        AM_RANGE(0x04800000, 0x04800fff) AM_DEVREADWRITE("vrender", vr0_snd_read, vr0_snd_write)
495
 
 
496
 
        AM_RANGE(0x05000000, 0x05000003) AM_READWRITE(FlashCmd_r, FlashCmd_w)
497
 
        AM_RANGE(0x05000000, 0x05ffffff) AM_ROMBANK("bank1")
498
 
 
499
 
        AM_RANGE(0x44414F4C, 0x44414F7F) AM_RAM AM_BASE_MEMBER(crystal_state, m_ResetPatch)
500
 
 
501
 
ADDRESS_MAP_END
502
 
 
503
 
static void PatchReset( running_machine &machine )
504
 
{
505
 
        //The test menu reset routine seems buggy
506
 
        //it reads the reset vector from 0x02000000 but it should be
507
 
        //read from 0x00000000. At 0x2000000 there is the bios signature
508
 
        //"LOADED VER....", so it jumps to "LOAD" in hex (0x44414F4C)
509
 
        //I'll add some code there that makes the game stay in a loop
510
 
        //reading the flip register so the idle skip works
511
 
 
512
 
/*
513
 
Loop1:
514
 
    LDI 1,%R2
515
 
    LDI     0x30000a6,%R1
516
 
    STS %R2,(%R1,0x0)
517
 
 
518
 
loop:
519
 
    LDI 0x30000a6,%R1
520
 
    LDSU    (%R1,0x0),%R2
521
 
    CMP     %R2,0x0000
522
 
    JNZ loop
523
 
 
524
 
    JMP Loop1
525
 
*/
526
 
 
527
 
        crystal_state *state = machine.driver_data<crystal_state>();
528
 
 
529
 
#if 1
530
 
        static const UINT32 Patch[] =
531
 
        {
532
 
                0x40c0ea01,
533
 
                0xe906400a,
534
 
                0x40c02a20,
535
 
                0xe906400a,
536
 
                0xa1d03a20,
537
 
                0xdef4d4fa
538
 
        };
539
 
 
540
 
        memcpy(state->m_ResetPatch, Patch, sizeof(Patch));
541
 
#else
542
 
        static const UINT8 Patch[] =
543
 
        {
544
 
                0x01,0xEA,0xC0,0x40,0x0A,0x40,0x06,0xE9,
545
 
                0x20,0x2A,0xC0,0x40,0x0A,0x40,0x06,0xE9,
546
 
                0x20,0x3A,0xD0,0xA1,0xFA,0xD4,0xF4,0xDE
547
 
        };
548
 
 
549
 
        memcpy(state->m_ResetPatch, Patch, sizeof(Patch));
550
 
#endif
551
 
}
552
 
 
553
 
static void crystal_banksw_postload(running_machine &machine)
554
 
{
555
 
        crystal_state *state = machine.driver_data<crystal_state>();
556
 
 
557
 
        if (state->m_Bank <= 2)
558
 
                memory_set_bankptr(machine, "bank1", machine.region("user1")->base() + state->m_Bank * 0x1000000);
559
 
        else
560
 
                memory_set_bankptr(machine, "bank1", machine.region("user2")->base());
561
 
}
562
 
 
563
 
static MACHINE_START( crystal )
564
 
{
565
 
        crystal_state *state = machine.driver_data<crystal_state>();
566
 
        int i;
567
 
 
568
 
        state->m_maincpu = machine.device("maincpu");
569
 
        state->m_ds1302 = machine.device("rtc");
570
 
        state->m_vr0video = machine.device("vr0");
571
 
 
572
 
        device_set_irq_callback(machine.device("maincpu"), icallback);
573
 
        for (i = 0; i < 4; i++)
574
 
                state->m_Timer[i] = machine.scheduler().timer_alloc(FUNC(Timercb), (void*)(FPTR)i);
575
 
 
576
 
        PatchReset(machine);
577
 
 
578
 
#ifdef IDLE_LOOP_SPEEDUP
579
 
        state->save_item(NAME(state->m_FlipCntRead));
580
 
#endif
581
 
 
582
 
        state->save_item(NAME(state->m_Bank));
583
 
        state->save_item(NAME(state->m_FlipCount));
584
 
        state->save_item(NAME(state->m_IntHigh));
585
 
        state->save_item(NAME(state->m_Timerctrl));
586
 
        state->save_item(NAME(state->m_FlashCmd));
587
 
        state->save_item(NAME(state->m_PIO));
588
 
        state->save_item(NAME(state->m_DMActrl));
589
 
        state->save_item(NAME(state->m_OldPort4));
590
 
        machine.save().register_postload(save_prepost_delegate(FUNC(crystal_banksw_postload), &machine));
591
 
}
592
 
 
593
 
static MACHINE_RESET( crystal )
594
 
{
595
 
        crystal_state *state = machine.driver_data<crystal_state>();
596
 
        int i;
597
 
 
598
 
        memset(state->m_sysregs, 0, 0x10000);
599
 
        memset(state->m_vidregs, 0, 0x10000);
600
 
        state->m_FlipCount = 0;
601
 
        state->m_IntHigh = 0;
602
 
        device_set_irq_callback(machine.device("maincpu"), icallback);
603
 
        state->m_Bank = 0;
604
 
        memory_set_bankptr(machine, "bank1", machine.region("user1")->base() + 0);
605
 
        state->m_FlashCmd = 0xff;
606
 
        state->m_OldPort4 = 0;
607
 
 
608
 
        state->m_DMActrl[0] = 0;
609
 
        state->m_DMActrl[1] = 0;
610
 
 
611
 
        for (i = 0; i < 4; i++)
612
 
        {
613
 
                state->m_Timerctrl[i] = 0;
614
 
                state->m_Timer[i]->adjust(attotime::never);
615
 
        }
616
 
 
617
 
        vr0_snd_set_areas(machine.device("vrender"), state->m_textureram, state->m_frameram);
618
 
#ifdef IDLE_LOOP_SPEEDUP
619
 
        state->m_FlipCntRead = 0;
620
 
#endif
621
 
 
622
 
        PatchReset(machine);
623
 
}
624
 
 
625
 
static UINT16 GetVidReg( address_space *space, UINT16 reg )
626
 
{
627
 
        return space->read_word(0x03000000 + reg);
628
 
}
629
 
 
630
 
static void SetVidReg( address_space *space, UINT16 reg, UINT16 val )
631
 
{
632
 
        space->write_word(0x03000000 + reg, val);
633
 
}
634
 
 
635
 
 
636
 
static SCREEN_UPDATE( crystal )
637
 
{
638
 
        crystal_state *state = screen->machine().driver_data<crystal_state>();
639
 
        address_space *space = screen->machine().device("maincpu")->memory().space(AS_PROGRAM);
640
 
        int DoFlip;
641
 
 
642
 
        UINT32 B0 = 0x0;
643
 
        UINT32 B1 = (GetVidReg(space, 0x90) & 0x8000) ? 0x400000 : 0x100000;
644
 
        UINT16 *Front, *Back;
645
 
        UINT16 *Visible, *DrawDest;
646
 
        UINT16 *srcline;
647
 
        int y;
648
 
        UINT16 head, tail;
649
 
        UINT32 width = screen->width();
650
 
 
651
 
        if (GetVidReg(space, 0x8e) & 1)
652
 
        {
653
 
                Front = (UINT16*) (state->m_frameram + B1 / 4);
654
 
                Back  = (UINT16*) (state->m_frameram + B0 / 4);
655
 
        }
656
 
        else
657
 
        {
658
 
                Front = (UINT16*) (state->m_frameram + B0 / 4);
659
 
                Back  = (UINT16*) (state->m_frameram + B1 / 4);
660
 
        }
661
 
 
662
 
        Visible  = (UINT16*) Front;
663
 
        DrawDest = (UINT16 *) state->m_frameram;
664
 
 
665
 
 
666
 
        if (GetVidReg(space, 0x8c) & 0x80)
667
 
                DrawDest = Front;
668
 
        else
669
 
                DrawDest = Back;
670
 
 
671
 
//  DrawDest = Visible;
672
 
 
673
 
        srcline = (UINT16 *) DrawDest;
674
 
 
675
 
        DoFlip = 0;
676
 
        head = GetVidReg(space, 0x82);
677
 
        tail = GetVidReg(space, 0x80);
678
 
        while ((head & 0x7ff) != (tail & 0x7ff))
679
 
        {
680
 
                DoFlip = vrender0_ProcessPacket(state->m_vr0video, 0x03800000 + head * 64, DrawDest, (UINT8*)state->m_textureram);
681
 
                head++;
682
 
                head &= 0x7ff;
683
 
                if (DoFlip)
684
 
                        break;
685
 
        }
686
 
 
687
 
        if (DoFlip)
688
 
                SetVidReg(space, 0x8e, GetVidReg(space, 0x8e) ^ 1);
689
 
 
690
 
        srcline = (UINT16 *) Visible;
691
 
        for (y = 0; y < 240; y++)
692
 
                memcpy(BITMAP_ADDR16(bitmap, y, 0), &srcline[y * 512], width * 2);
693
 
 
694
 
        return 0;
695
 
}
696
 
 
697
 
static SCREEN_EOF(crystal)
698
 
{
699
 
        crystal_state *state = machine.driver_data<crystal_state>();
700
 
        address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
701
 
        UINT16 head, tail;
702
 
        int DoFlip = 0;
703
 
 
704
 
        head = GetVidReg(space, 0x82);
705
 
        tail = GetVidReg(space, 0x80);
706
 
        while ((head & 0x7ff) != (tail & 0x7ff))
707
 
        {
708
 
                UINT16 Packet0 = space->read_word(0x03800000 + head * 64);
709
 
                if (Packet0 & 0x81)
710
 
                        DoFlip = 1;
711
 
                head++;
712
 
                head &= 0x7ff;
713
 
                if (DoFlip)
714
 
                        break;
715
 
        }
716
 
        SetVidReg(space, 0x82, head);
717
 
        if (DoFlip)
718
 
        {
719
 
                if (state->m_FlipCount)
720
 
                        state->m_FlipCount--;
721
 
 
722
 
        }
723
 
}
724
 
 
725
 
static INTERRUPT_GEN(crystal_interrupt)
726
 
{
727
 
        IntReq(device->machine(), 24);          //VRender0 VBlank
728
 
}
729
 
 
730
 
static INPUT_PORTS_START(crystal)
731
 
        PORT_START("P1_P2")
732
 
        PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
733
 
        PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
734
 
        PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
735
 
        PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
736
 
        PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
737
 
        PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
738
 
        PORT_BIT( 0x00000040, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1)
739
 
        PORT_BIT( 0x00000080, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(2)
740
 
        PORT_BIT( 0x0000ff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
741
 
 
742
 
        PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
743
 
        PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
744
 
        PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
745
 
        PORT_BIT( 0x00080000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
746
 
        PORT_BIT( 0x00100000, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
747
 
        PORT_BIT( 0x00200000, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
748
 
        PORT_BIT( 0x00400000, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
749
 
        PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
750
 
        PORT_BIT( 0xff000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
751
 
 
752
 
        PORT_START("P3_P4")
753
 
        PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
754
 
        PORT_BIT( 0x00000002, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
755
 
        PORT_BIT( 0x00000004, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
756
 
        PORT_BIT( 0x00000008, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
757
 
        PORT_BIT( 0x00000010, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
758
 
        PORT_BIT( 0x00000020, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
759
 
        PORT_BIT( 0x00000040, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(3)
760
 
        PORT_BIT( 0x00000080, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(4)
761
 
        PORT_BIT( 0x0000ff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
762
 
 
763
 
        PORT_BIT( 0x00010000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(3)
764
 
        PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(4)
765
 
        PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(3)
766
 
        PORT_BIT( 0x00080000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(4)
767
 
        PORT_BIT( 0x00100000, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(3)
768
 
        PORT_BIT( 0x00200000, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(4)
769
 
        PORT_BIT( 0x00400000, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(3)
770
 
        PORT_BIT( 0x00800000, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(4)
771
 
        PORT_BIT( 0xff000000, IP_ACTIVE_LOW, IPT_UNKNOWN )
772
 
 
773
 
        PORT_START("SYSTEM")
774
 
        PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
775
 
        PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
776
 
        PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START3 )
777
 
        PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START4 )
778
 
        PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 )
779
 
        PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 )
780
 
        PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE1 )
781
 
        PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW )
782
 
 
783
 
        PORT_START("DSW")
784
 
        PORT_DIPNAME( 0x01, 0x01, DEF_STR( Pause ) )
785
 
        PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
786
 
        PORT_DIPSETTING(    0x00, DEF_STR( On ) )
787
 
        PORT_DIPNAME( 0x02, 0x02, DEF_STR( Free_Play ) )
788
 
        PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
789
 
        PORT_DIPSETTING(    0x00, DEF_STR( On ) )
790
 
        PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
791
 
        PORT_DIPSETTING(    0x04, DEF_STR( Off ) )
792
 
        PORT_DIPSETTING(    0x00, DEF_STR( On ) )
793
 
        PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
794
 
        PORT_DIPSETTING(    0x08, DEF_STR( Off ) )
795
 
        PORT_DIPSETTING(    0x00, DEF_STR( On ) )
796
 
        PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
797
 
        PORT_DIPSETTING(    0x10, DEF_STR( Off ) )
798
 
        PORT_DIPSETTING(    0x00, DEF_STR( On ) )
799
 
        PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
800
 
        PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
801
 
        PORT_DIPSETTING(    0x00, DEF_STR( On ) )
802
 
        PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
803
 
        PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
804
 
        PORT_DIPSETTING(    0x00, DEF_STR( On ) )
805
 
        PORT_DIPNAME( 0x80, 0x80, DEF_STR( Test ) )
806
 
        PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
807
 
        PORT_DIPSETTING(    0x00, DEF_STR( On ) )
808
 
INPUT_PORTS_END
809
 
 
810
 
static const vr0_interface vr0_config =
811
 
{
812
 
        0x04800000
813
 
};
814
 
 
815
 
static const vr0video_interface vr0video_config =
816
 
{
817
 
        "maincpu"
818
 
};
819
 
 
820
 
static MACHINE_CONFIG_START( crystal, crystal_state )
821
 
 
822
 
        MCFG_CPU_ADD("maincpu", SE3208, 43000000)
823
 
        MCFG_CPU_PROGRAM_MAP(crystal_mem)
824
 
        MCFG_CPU_VBLANK_INT("screen", crystal_interrupt)
825
 
 
826
 
        MCFG_MACHINE_START(crystal)
827
 
        MCFG_MACHINE_RESET(crystal)
828
 
 
829
 
        MCFG_NVRAM_ADD_0FILL("nvram")
830
 
 
831
 
        MCFG_SCREEN_ADD("screen", RASTER)
832
 
        MCFG_SCREEN_REFRESH_RATE(60)
833
 
        MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
834
 
        MCFG_SCREEN_FORMAT(BITMAP_FORMAT_INDEXED16)
835
 
        MCFG_SCREEN_SIZE(320, 240)
836
 
        MCFG_SCREEN_VISIBLE_AREA(0, 319, 0, 239)
837
 
        MCFG_SCREEN_UPDATE(crystal)
838
 
        MCFG_SCREEN_EOF(crystal)
839
 
 
840
 
        MCFG_VIDEO_VRENDER0_ADD("vr0", vr0video_config)
841
 
 
842
 
        MCFG_PALETTE_INIT(RRRRR_GGGGGG_BBBBB)
843
 
        MCFG_PALETTE_LENGTH(65536)
844
 
 
845
 
        MCFG_DS1302_ADD("rtc")
846
 
 
847
 
        MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
848
 
 
849
 
        MCFG_SOUND_ADD("vrender", VRENDER0, 0)
850
 
        MCFG_SOUND_CONFIG(vr0_config)
851
 
        MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
852
 
        MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
853
 
MACHINE_CONFIG_END
854
 
 
855
 
/*
856
 
    Top blade screen is 32 pixels wider
857
 
*/
858
 
static MACHINE_CONFIG_DERIVED( topbladv, crystal )
859
 
 
860
 
        MCFG_SCREEN_MODIFY("screen")
861
 
        MCFG_SCREEN_SIZE(320+32, 240)
862
 
        MCFG_SCREEN_VISIBLE_AREA(0, 319+32, 0, 239)
863
 
 
864
 
MACHINE_CONFIG_END
865
 
 
866
 
ROM_START( crysbios )
867
 
        ROM_REGION( 0x20000, "maincpu", 0 ) // bios
868
 
        ROM_LOAD("mx27l1000.u14",  0x000000, 0x020000, CRC(BEFF39A9) SHA1(b6f6dda58d9c82273f9422c1bd623411e58982cb) )
869
 
 
870
 
        ROM_REGION32_LE( 0x3000000, "user1", ROMREGION_ERASEFF ) // Flash
871
 
 
872
 
        ROM_REGION( 0x10000, "user2",   ROMREGION_ERASEFF )     //Unmapped flash
873
 
ROM_END
874
 
 
875
 
ROM_START( crysking )
876
 
        ROM_REGION( 0x20000, "maincpu", 0 ) // bios
877
 
        ROM_LOAD("mx27l1000.u14",  0x000000, 0x020000, CRC(BEFF39A9) SHA1(b6f6dda58d9c82273f9422c1bd623411e58982cb))
878
 
 
879
 
        ROM_REGION32_LE( 0x3000000, "user1", 0 ) // Flash
880
 
        ROM_LOAD("bcsv0004f01.u1",  0x0000000, 0x1000000, CRC(8FEFF120) SHA1(2ea42fa893bff845b5b855e2556789f8354e9066) )
881
 
        ROM_LOAD("bcsv0004f02.u2",  0x1000000, 0x1000000, CRC(0E799845) SHA1(419674ce043cb1efb18303f4cb7fdbbae642ee39) )
882
 
        ROM_LOAD("bcsv0004f03.u3",  0x2000000, 0x1000000, CRC(659E2D17) SHA1(342c98f3f695ef4dea8b533612451c4d2fb58809) )
883
 
 
884
 
        ROM_REGION( 0x10000, "user2",   ROMREGION_ERASEFF )     //Unmapped flash
885
 
ROM_END
886
 
 
887
 
ROM_START( evosocc )
888
 
        ROM_REGION( 0x20000, "maincpu", 0 ) // bios
889
 
        ROM_LOAD("mx27l1000.u14",  0x000000, 0x020000, CRC(BEFF39A9) SHA1(b6f6dda58d9c82273f9422c1bd623411e58982cb))
890
 
 
891
 
        ROM_REGION32_LE( 0x3000000, "user1", 0 ) // Flash
892
 
        ROM_LOAD("bcsv0001u01",  0x0000000, 0x1000000, CRC(2581A0EA) SHA1(ee483ac60a3ed00a21cb515974cec4af19916a7d) )
893
 
        ROM_LOAD("bcsv0001u02",  0x1000000, 0x1000000, CRC(47EF1794) SHA1(f573706c17d1342b9b7aed9b40b8b648f0bf58db) )
894
 
        ROM_LOAD("bcsv0001u03",  0x2000000, 0x1000000, CRC(F396A2EC) SHA1(f305eb10856fb5d4c229a6b09d6a2fb21b24ce66) )
895
 
 
896
 
        ROM_REGION( 0x10000, "user2",   ROMREGION_ERASEFF )     //Unmapped flash
897
 
ROM_END
898
 
 
899
 
ROM_START( topbladv )
900
 
        ROM_REGION( 0x20000, "maincpu", 0 ) // bios
901
 
        ROM_LOAD("mx27l1000.u14",  0x000000, 0x020000, CRC(BEFF39A9) SHA1(b6f6dda58d9c82273f9422c1bd623411e58982cb))
902
 
 
903
 
        ROM_REGION( 0x4300, "pic", 0 ) // pic16c727 - we don't have a core for this
904
 
        ROM_LOAD("top_blade_v_pic16c727.bin",  0x000000, 0x4300, CRC(9cdea57b) SHA1(884156085f9e780cdf719aedc2e8a0fd5983613b) )
905
 
 
906
 
 
907
 
        ROM_REGION32_LE( 0x1000000, "user1", 0 ) // Flash
908
 
        ROM_LOAD("flash.u1",  0x0000000, 0x1000000, CRC(bd23f640) SHA1(1d22aa2c828642bb7c1dfea4e13f777f95acc701) )
909
 
 
910
 
        ROM_REGION( 0x10000, "user2",   ROMREGION_ERASEFF )     //Unmapped flash
911
 
ROM_END
912
 
 
913
 
 
914
 
ROM_START( officeye )
915
 
        ROM_REGION( 0x20000, "maincpu", 0 ) // bios (not the standard one)
916
 
        ROM_LOAD("bios.u14",  0x000000, 0x020000, CRC(ffc57e90) SHA1(6b6a17fd4798dea9c7b880f3063be8494e7db302) )
917
 
 
918
 
        ROM_REGION( 0x4280, "pic", 0 ) // pic16f84a - we don't have a core for this
919
 
        ROM_LOAD("office_yeo_in_cheon_ha_pic16f84a.bin",  0x000000, 0x4280, CRC(7561cdf5) SHA1(eade592823a110019b4af81a7dc56d01f7d6589f) )
920
 
 
921
 
 
922
 
        ROM_REGION32_LE( 0x2000000, "user1", 0 ) // Flash
923
 
        ROM_LOAD("flash.u1",  0x0000000, 0x1000000, CRC(d3f3eec4) SHA1(ea728415bd4906964b7d37f4379a8a3bd42a1c2d) )
924
 
        ROM_LOAD("flash.u2",  0x1000000, 0x1000000, CRC(e4f85d0a) SHA1(2ddfa6b3a30e69754aa9d96434ff3d37784bfa57) )
925
 
 
926
 
        ROM_REGION( 0x10000, "user2",   ROMREGION_ERASEFF )     //Unmapped flash
927
 
ROM_END
928
 
 
929
 
 
930
 
ROM_START( donghaer )
931
 
        ROM_REGION( 0x20000, "maincpu", 0 ) // bios
932
 
        ROM_LOAD("mx27l1000.u14",  0x000000, 0x020000, CRC(BEFF39A9) SHA1(b6f6dda58d9c82273f9422c1bd623411e58982cb))
933
 
 
934
 
        ROM_REGION( 0x4280, "pic", 0 ) // pic16f84a - we don't have a core for this (or the dump in this case)
935
 
        ROM_LOAD("donghaer_pic16f84a.bin",  0x000000, 0x4280, NO_DUMP )
936
 
 
937
 
        ROM_REGION32_LE( 0x2000000, "user1", 0 ) // Flash
938
 
        ROM_LOAD( "u1",           0x0000000, 0x1000000, CRC(61217ad7) SHA1(2593f1356aa850f4f9aa5d00bec822aa59c59224) )
939
 
        ROM_LOAD( "u2",           0x1000000, 0x1000000, CRC(6d82f1a5) SHA1(036bd45f0daac1ffeaa5ad9774fc1b56e3c75ff9) )
940
 
 
941
 
        ROM_REGION( 0x10000, "user2",   ROMREGION_ERASEFF )     //Unmapped flash
942
 
ROM_END
943
 
 
944
 
static DRIVER_INIT(crysking)
945
 
{
946
 
        UINT16 *Rom = (UINT16*) machine.region("user1")->base();
947
 
 
948
 
        //patch the data feed by the protection
949
 
 
950
 
        Rom[WORD_XOR_LE(0x7bb6/2)] = 0xDF01;
951
 
        Rom[WORD_XOR_LE(0x7bb8/2)] = 0x9C00;
952
 
 
953
 
        Rom[WORD_XOR_LE(0x976a/2)] = 0x901C;
954
 
        Rom[WORD_XOR_LE(0x976c/2)] = 0x9001;
955
 
 
956
 
        Rom[WORD_XOR_LE(0x8096/2)] = 0x90FC;
957
 
        Rom[WORD_XOR_LE(0x8098/2)] = 0x9001;
958
 
 
959
 
        Rom[WORD_XOR_LE(0x8a52/2)] = 0x4000;    //NOP
960
 
        Rom[WORD_XOR_LE(0x8a54/2)] = 0x403c;    //NOP
961
 
}
962
 
 
963
 
static DRIVER_INIT(evosocc)
964
 
{
965
 
        UINT16 *Rom = (UINT16*) machine.region("user1")->base();
966
 
        Rom += 0x1000000 * 2 / 2;
967
 
 
968
 
        Rom[WORD_XOR_LE(0x97388E/2)] = 0x90FC;  //PUSH R2..R7
969
 
        Rom[WORD_XOR_LE(0x973890/2)] = 0x9001;  //PUSH R0
970
 
 
971
 
        Rom[WORD_XOR_LE(0x971058/2)] = 0x907C;  //PUSH R2..R6
972
 
        Rom[WORD_XOR_LE(0x971060/2)] = 0x9001; //PUSH R0
973
 
 
974
 
        Rom[WORD_XOR_LE(0x978036/2)] = 0x900C;  //PUSH R2-R3
975
 
        Rom[WORD_XOR_LE(0x978038/2)] = 0x8303;  //LD    (%SP,0xC),R3
976
 
 
977
 
        Rom[WORD_XOR_LE(0x974ED0/2)] = 0x90FC;  //PUSH R7-R6-R5-R4-R3-R2
978
 
        Rom[WORD_XOR_LE(0x974ED2/2)] = 0x9001;  //PUSH R0
979
 
}
980
 
 
981
 
static DRIVER_INIT(topbladv)
982
 
{
983
 
        UINT16 *Rom = (UINT16*) machine.region("user1")->base();
984
 
 
985
 
        Rom[WORD_XOR_LE(0x12d7a/2)] = 0x90FC;   //PUSH R7-R6-R5-R4-R3-R2
986
 
        Rom[WORD_XOR_LE(0x12d7c/2)] = 0x9001;   //PUSH R0
987
 
 
988
 
        Rom[WORD_XOR_LE(0x2fe18/2)] = 0x9001;   //PUSH R0
989
 
        Rom[WORD_XOR_LE(0x2fe1a/2)] = 0x9200;   //PUSH SR
990
 
 
991
 
        Rom[WORD_XOR_LE(0x18880/2)] = 0x9001;   //PUSH R0
992
 
        Rom[WORD_XOR_LE(0x18882/2)] = 0x9200;   //PUSH SR
993
 
 
994
 
        Rom[WORD_XOR_LE(0xDACE/2)] = 0x901C;    //PUSH R4-R3-R2
995
 
        Rom[WORD_XOR_LE(0xDAD0/2)] = 0x9001;    //PUSH R0
996
 
 
997
 
}
998
 
 
999
 
static DRIVER_INIT(officeye)
1000
 
{
1001
 
        UINT16 *Rom = (UINT16*) machine.region("user1")->base();
1002
 
 
1003
 
        Rom[WORD_XOR_LE(0x9c9e/2)] = 0x901C;    //PUSH R4-R3-R2
1004
 
        Rom[WORD_XOR_LE(0x9ca0/2)] = 0x9001;    //PUSH R0
1005
 
 
1006
 
        Rom[WORD_XOR_LE(0x9EE4/2)] = 0x907C;    //PUSH R6-R5-R4-R3-R2
1007
 
        Rom[WORD_XOR_LE(0x9EE6/2)] = 0x9001;    //PUSH R0
1008
 
 
1009
 
        Rom[WORD_XOR_LE(0x4B2E0/2)] = 0x9004;   //PUSH R2
1010
 
        Rom[WORD_XOR_LE(0x4B2E2/2)] = 0x9001;   //PUSH R0
1011
 
 
1012
 
/*
1013
 
    Rom[WORD_XOR_LE(0x18880/2)] = 0x9001; //PUSH R0
1014
 
    Rom[WORD_XOR_LE(0x18882/2)] = 0x9200; //PUSH SR
1015
 
 */
1016
 
}
1017
 
 
1018
 
 
1019
 
 
1020
 
GAME( 2001, crysbios,        0, crystal,  crystal,         0, ROT0, "BrezzaSoft", "Crystal System BIOS", GAME_IS_BIOS_ROOT )
1021
 
GAME( 2001, crysking, crysbios, crystal,  crystal,  crysking, ROT0, "BrezzaSoft", "The Crystal of Kings", 0 )
1022
 
GAME( 2001, evosocc,  crysbios, crystal,  crystal,  evosocc,  ROT0, "Evoga", "Evolution Soccer", 0 )
1023
 
GAME( 2003, topbladv, crysbios, topbladv, crystal,  topbladv, ROT0, "SonoKong / Expotato", "Top Blade V", GAME_NOT_WORKING ) // protection
1024
 
GAME( 2001, officeye,        0, crystal,  crystal,  officeye, ROT0, "Danbi", "Office Yeo In Cheon Ha (version 1.2)", GAME_NOT_WORKING ) // protection
1025
 
GAME( 2001, donghaer,        0, crystal,  crystal,  officeye, ROT0, "Danbi", "Donggul Donggul Haerong", GAME_NOT_WORKING )