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Viewing changes to mess/src/emu/cpu/mips/mips3com.h

  • Committer: Package Import Robot
  • Author(s): Jordi Mallach, Jordi Mallach, Emmanuel Kasper
  • Date: 2011-12-19 22:56:27 UTC
  • mfrom: (0.1.2)
  • Revision ID: package-import@ubuntu.com-20111219225627-ub5oga1oys4ogqzm
Tags: 0.144-1
http://bugs.debian.org/651538
[ Jordi Mallach ]
* Fix syntax errors in DEP5 copyright file (lintian).
* Use a versioned copyright Format specification field.
* Update Vcs-* URLs.
* Move transitional packages to the new metapackages section, and make
  them priority extra.
* Remove references to GNU/Linux and MESS sources from copyright.
* Add build variables for s390x.
* Use .xz tarballs as it cuts 4MB for the upstream sources.
* Add nplayers.ini as a patch. Update copyright file to add CC-BY-SA-3.0.

[ Emmanuel Kasper ]
* New upstream release. Closes: #651538.
* Add Free Desktop compliant png icons of various sizes taken from
  the hydroxygen iconset
* Mess is now built from a new source package, to avoid possible source
  incompatibilities between mame and the mess overlay.
* Mame-tools are not built from the mame source package anymore, but
  from the mess source package

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mess/src/emu/cpu/mips/mips3com.h
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/***************************************************************************
2
 
 
3
 
    mips3com.h
4
 
 
5
 
    Common MIPS III/IV definitions and functions
6
 
 
7
 
***************************************************************************/
8
 
 
9
 
#pragma once
10
 
 
11
 
#ifndef __MIPS3COM_H__
12
 
#define __MIPS3COM_H__
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14
 
#include "mips3.h"
15
 
#include "cpu/vtlb.h"
16
 
 
17
 
 
18
 
/***************************************************************************
19
 
    CONSTANTS
20
 
***************************************************************************/
21
 
 
22
 
#define MIPS3_USE_DRC
23
 
 
24
 
/* core parameters */
25
 
#define MIPS3_MIN_PAGE_SHIFT            12
26
 
#define MIPS3_MIN_PAGE_SIZE                     (1 << MIPS3_MIN_PAGE_SHIFT)
27
 
#define MIPS3_MIN_PAGE_MASK                     (MIPS3_MIN_PAGE_SIZE - 1)
28
 
#define MIPS3_MAX_PADDR_SHIFT           32
29
 
#define MIPS3_MAX_TLB_ENTRIES           48
30
 
 
31
 
/* cycle parameters */
32
 
#define MIPS3_COUNT_READ_CYCLES         250
33
 
#define MIPS3_CAUSE_READ_CYCLES         250
34
 
 
35
 
/* MIPS flavors */
36
 
enum _mips3_flavor
37
 
{
38
 
        /* MIPS III variants */
39
 
        MIPS3_TYPE_MIPS_III,
40
 
        MIPS3_TYPE_VR4300,
41
 
        MIPS3_TYPE_R4600,
42
 
        MIPS3_TYPE_R4650,
43
 
        MIPS3_TYPE_R4700,
44
 
 
45
 
        /* MIPS IV variants */
46
 
        MIPS3_TYPE_MIPS_IV,
47
 
        MIPS3_TYPE_R5000,
48
 
        MIPS3_TYPE_QED5271,
49
 
        MIPS3_TYPE_RM7000
50
 
};
51
 
typedef enum _mips3_flavor mips3_flavor;
52
 
 
53
 
/* TLB bits */
54
 
#define TLB_GLOBAL                              0x01
55
 
#define TLB_VALID                               0x02
56
 
#define TLB_DIRTY                               0x04
57
 
#define TLB_PRESENT                             0x08
58
 
 
59
 
/* COP0 registers */
60
 
#define COP0_Index                              0
61
 
#define COP0_Random                             1
62
 
#define COP0_EntryLo                    2
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#define COP0_EntryLo0                   2
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#define COP0_EntryLo1                   3
65
 
#define COP0_Context                    4
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#define COP0_PageMask                   5
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#define COP0_Wired                              6
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#define COP0_BadVAddr                   8
69
 
#define COP0_Count                              9
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#define COP0_EntryHi                    10
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#define COP0_Compare                    11
72
 
#define COP0_Status                             12
73
 
#define COP0_Cause                              13
74
 
#define COP0_EPC                                14
75
 
#define COP0_PRId                               15
76
 
#define COP0_Config                             16
77
 
#define COP0_LLAddr                             17
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#define COP0_XContext                   20
79
 
#define COP0_ECC                                26
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#define COP0_CacheErr                   27
81
 
#define COP0_TagLo                              28
82
 
#define COP0_TagHi                              29
83
 
#define COP0_ErrorPC                    30
84
 
 
85
 
/* Status register bits */
86
 
#define SR_IE                                   0x00000001
87
 
#define SR_EXL                                  0x00000002
88
 
#define SR_ERL                                  0x00000004
89
 
#define SR_KSU_MASK                             0x00000018
90
 
#define SR_KSU_KERNEL                   0x00000000
91
 
#define SR_KSU_SUPERVISOR               0x00000008
92
 
#define SR_KSU_USER                             0x00000010
93
 
#define SR_IMSW0                                0x00000100
94
 
#define SR_IMSW1                                0x00000200
95
 
#define SR_IMEX0                                0x00000400
96
 
#define SR_IMEX1                                0x00000800
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#define SR_IMEX2                                0x00001000
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#define SR_IMEX3                                0x00002000
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#define SR_IMEX4                                0x00004000
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#define SR_IMEX5                                0x00008000
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#define SR_DE                                   0x00010000
102
 
#define SR_CE                                   0x00020000
103
 
#define SR_CH                                   0x00040000
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#define SR_SR                                   0x00100000
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#define SR_TS                                   0x00200000
106
 
#define SR_BEV                                  0x00400000
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#define SR_ITS                                  0x01000000      /* VR4300 only, Application Note doesn't give purpose */
108
 
#define SR_RE                                   0x02000000
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#define SR_FR                                   0x04000000
110
 
#define SR_RP                                   0x08000000
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#define SR_COP0                                 0x10000000
112
 
#define SR_COP1                                 0x20000000
113
 
#define SR_COP2                                 0x40000000
114
 
#define SR_COP3                                 0x80000000
115
 
 
116
 
/* exception types */
117
 
#define EXCEPTION_INTERRUPT             0
118
 
#define EXCEPTION_TLBMOD                1
119
 
#define EXCEPTION_TLBLOAD               2
120
 
#define EXCEPTION_TLBSTORE              3
121
 
#define EXCEPTION_ADDRLOAD              4
122
 
#define EXCEPTION_ADDRSTORE             5
123
 
#define EXCEPTION_BUSINST               6
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#define EXCEPTION_BUSDATA               7
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#define EXCEPTION_SYSCALL               8
126
 
#define EXCEPTION_BREAK                 9
127
 
#define EXCEPTION_INVALIDOP             10
128
 
#define EXCEPTION_BADCOP                11
129
 
#define EXCEPTION_OVERFLOW              12
130
 
#define EXCEPTION_TRAP                  13
131
 
#define EXCEPTION_TLBLOAD_FILL  16
132
 
#define EXCEPTION_TLBSTORE_FILL 17
133
 
#define EXCEPTION_COUNT                 18
134
 
 
135
 
 
136
 
 
137
 
/***************************************************************************
138
 
    HELPER MACROS
139
 
***************************************************************************/
140
 
 
141
 
#define REG_LO                  32
142
 
#define REG_HI                  33
143
 
 
144
 
#define RSREG                   ((op >> 21) & 31)
145
 
#define RTREG                   ((op >> 16) & 31)
146
 
#define RDREG                   ((op >> 11) & 31)
147
 
#define SHIFT                   ((op >> 6) & 31)
148
 
 
149
 
#define FRREG                   ((op >> 21) & 31)
150
 
#define FTREG                   ((op >> 16) & 31)
151
 
#define FSREG                   ((op >> 11) & 31)
152
 
#define FDREG                   ((op >> 6) & 31)
153
 
 
154
 
#define IS_SINGLE(o)    (((o) & (1 << 21)) == 0)
155
 
#define IS_DOUBLE(o)    (((o) & (1 << 21)) != 0)
156
 
#define IS_FLOAT(o)     (((o) & (1 << 23)) == 0)
157
 
#define IS_INTEGRAL(o)  (((o) & (1 << 23)) != 0)
158
 
 
159
 
#define SIMMVAL                 ((INT16)op)
160
 
#define UIMMVAL                 ((UINT16)op)
161
 
#define LIMMVAL                 (op & 0x03ffffff)
162
 
 
163
 
 
164
 
 
165
 
/***************************************************************************
166
 
    STRUCTURES & TYPEDEFS
167
 
***************************************************************************/
168
 
 
169
 
/* MIPS3 TLB entry */
170
 
typedef struct _mips3_tlb_entry mips3_tlb_entry;
171
 
struct _mips3_tlb_entry
172
 
{
173
 
        UINT64                  page_mask;
174
 
        UINT64                  entry_hi;
175
 
        UINT64                  entry_lo[2];
176
 
};
177
 
 
178
 
 
179
 
/* forward declaration of implementation-specific state */
180
 
typedef struct _mips3imp_state mips3imp_state;
181
 
 
182
 
 
183
 
/* MIPS3 state */
184
 
typedef struct _mips3_state mips3_state;
185
 
struct _mips3_state
186
 
{
187
 
        /* core registers */
188
 
        UINT32                  pc;
189
 
        int                             icount;
190
 
        UINT64                  r[35];
191
 
 
192
 
        /* COP registers */
193
 
        UINT64                  cpr[3][32];
194
 
        UINT64                  ccr[3][32];
195
 
        UINT32                  llbit;
196
 
 
197
 
        /* internal stuff */
198
 
        mips3_flavor    flavor;
199
 
        device_irq_callback irq_callback;
200
 
        legacy_cpu_device *     device;
201
 
        address_space *program;
202
 
        direct_read_data *direct;
203
 
        UINT32                  system_clock;
204
 
        UINT32                  cpu_clock;
205
 
        UINT64                  count_zero_time;
206
 
        UINT32                  compare_armed;
207
 
        emu_timer *             compare_int_timer;
208
 
 
209
 
        /* derived info based on flavor */
210
 
        UINT32                  pfnmask;
211
 
        UINT8                   tlbentries;
212
 
 
213
 
        /* memory accesses */
214
 
        UINT8                   bigendian;
215
 
        data_accessors  memory;
216
 
 
217
 
        /* cache memory */
218
 
        size_t                  icache_size;
219
 
        size_t                  dcache_size;
220
 
 
221
 
        /* MMU */
222
 
        vtlb_state *    vtlb;
223
 
        mips3_tlb_entry tlb[MIPS3_MAX_TLB_ENTRIES];
224
 
 
225
 
        /* for use by specific implementations */
226
 
        mips3imp_state *impstate;
227
 
};
228
 
 
229
 
 
230
 
 
231
 
/***************************************************************************
232
 
    FUNCTION PROTOTYPES
233
 
***************************************************************************/
234
 
 
235
 
void mips3com_init(mips3_state *mips, mips3_flavor flavor, int bigendian, legacy_cpu_device *device, device_irq_callback irqcallback);
236
 
void mips3com_exit(mips3_state *mips);
237
 
 
238
 
void mips3com_reset(mips3_state *mips);
239
 
offs_t mips3com_dasm(mips3_state *mips, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
240
 
void mips3com_update_cycle_counting(mips3_state *mips);
241
 
 
242
 
void mips3com_asid_changed(mips3_state *mips);
243
 
int mips3com_translate_address(mips3_state *mips, address_spacenum space, int intention, offs_t *address);
244
 
void mips3com_tlbr(mips3_state *mips);
245
 
void mips3com_tlbwi(mips3_state *mips);
246
 
void mips3com_tlbwr(mips3_state *mips);
247
 
void mips3com_tlbp(mips3_state *mips);
248
 
 
249
 
void mips3com_set_info(mips3_state *mips, UINT32 state, cpuinfo *info);
250
 
void mips3com_get_info(mips3_state *mips, UINT32 state, cpuinfo *info);
251
 
 
252
 
 
253
 
 
254
 
/***************************************************************************
255
 
    INLINE FUNCTIONS
256
 
***************************************************************************/
257
 
 
258
 
/*-------------------------------------------------
259
 
    mips3com_set_irq_line - set or clear the given
260
 
    IRQ line
261
 
-------------------------------------------------*/
262
 
 
263
 
INLINE void mips3com_set_irq_line(mips3_state *mips, int irqline, int state)
264
 
{
265
 
        if (state != CLEAR_LINE)
266
 
                mips->cpr[0][COP0_Cause] |= 0x400 << irqline;
267
 
        else
268
 
                mips->cpr[0][COP0_Cause] &= ~(0x400 << irqline);
269
 
}
270
 
 
271
 
#endif /* __MIPS3COM_H__ */