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/**********************************************************************
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Zilog Z8 Single-Chip MCU emulation
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Visit http://mamedev.org for licensing and usage restrictions.
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**********************************************************************/
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/***************************************************************************
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***************************************************************************/
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#define read(_reg) register_read(cpustate, _reg)
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#define r(_data) get_working_register(cpustate, _data)
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#define Ir(_data) get_intermediate_register(cpustate, get_working_register(cpustate, _data))
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#define R get_register(cpustate, fetch(cpustate))
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#define IR get_intermediate_register(cpustate, get_register(cpustate, fetch(cpustate)))
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#define RR get_intermediate_register(cpustate, get_register(cpustate, fetch(cpustate)))
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#define IM fetch(cpustate)
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#define flag(_flag) ((cpustate->r[Z8_REGISTER_FLAGS] & Z8_FLAGS##_##_flag) ? 1 : 0)
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#define mode_r1_r2(_func) \
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UINT8 dst_src = fetch(cpustate);\
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UINT8 dst = r(dst_src >> 4);\
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UINT8 src = read(r(dst_src & 0x0f));\
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_func(cpustate, dst, src);
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#define mode_r1_Ir2(_func) \
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UINT8 dst_src = fetch(cpustate);\
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UINT8 dst = r(dst_src >> 4);\
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UINT8 src = read(Ir(dst_src & 0x0f));\
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_func(cpustate, dst, src);
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#define mode_R2_R1(_func) \
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_func(cpustate, dst, src);
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#define mode_IR2_R1(_func) \
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_func(cpustate, dst, src);
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#define mode_R1_IM(_func) \
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_func(cpustate, dst, src);
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#define mode_IR1_IM(_func) \
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_func(cpustate, dst, src);
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#define mode_r1(_func) \
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UINT8 dst = r(opcode >> 4);\
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#define mode_R1(_func) \
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#define mode_RR1(_func) \
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#define mode_IR1(_func) \
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#define mode_r1_IM(_func) \
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UINT8 dst = r(opcode >> 4);\
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_func(cpustate, dst, src);
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#define mode_r1_R2(_func) \
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UINT8 dst = r(opcode >> 4);\
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_func(cpustate, dst, src);
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#define mode_r2_R1(_func) \
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UINT8 src = read(r(opcode >> 4));\
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_func(cpustate, dst, src);
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#define mode_Ir1_r2(_func) \
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UINT8 dst_src = fetch(cpustate);\
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UINT8 dst = Ir(dst_src >> 4);\
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UINT8 src = read(r(dst_src & 0x0f));\
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_func(cpustate, dst, src);
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#define mode_R2_IR1(_func) \
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_func(cpustate, dst, src);
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#define mode_r1_x_R2(_func) \
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UINT8 dst_src = fetch(cpustate);\
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UINT8 dst = r(dst_src >> 4);\
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UINT8 src = read(read(r(dst_src & 0x0f)) + R);\
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_func(cpustate, dst, src);
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#define mode_r2_x_R1(_func) \
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UINT8 dst_src = fetch(cpustate);\
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UINT8 dst = R + read(r(dst_src & 0x0f));\
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UINT8 src = read(r(dst_src >> 4));\
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_func(cpustate, dst, src);
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/***************************************************************************
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***************************************************************************/
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static void clear(z8_state *cpustate, UINT8 dst)
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register_write(cpustate, dst, 0);
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INSTRUCTION( clr_R1 ) { mode_R1(clear) }
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INSTRUCTION( clr_IR1 ) { mode_IR1(clear) }
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static void load(z8_state *cpustate, UINT8 dst, UINT8 src)
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register_write(cpustate, dst, src);
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INSTRUCTION( ld_r1_IM ) { mode_r1_IM(load) }
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INSTRUCTION( ld_r1_R2 ) { mode_r1_R2(load) }
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INSTRUCTION( ld_r2_R1 ) { mode_r2_R1(load) }
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INSTRUCTION( ld_Ir1_r2 ) { mode_Ir1_r2(load) }
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INSTRUCTION( ld_R2_IR1 ) { mode_R2_IR1(load) }
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INSTRUCTION( ld_r1_x_R2 ) { mode_r1_x_R2(load) }
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INSTRUCTION( ld_r2_x_R1 ) { mode_r2_x_R1(load) }
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INSTRUCTION( ld_r1_r2 ) { mode_r1_r2(load) }
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INSTRUCTION( ld_r1_Ir2 ) { mode_r1_Ir2(load) }
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INSTRUCTION( ld_R2_R1 ) { mode_R2_R1(load) }
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INSTRUCTION( ld_IR2_R1 ) { mode_IR2_R1(load) }
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INSTRUCTION( ld_R1_IM ) { mode_R1_IM(load) }
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INSTRUCTION( ld_IR1_IM ) { mode_IR1_IM(load) }
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static void load_from_memory(z8_state *cpustate, address_space *space)
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UINT8 operands = fetch(cpustate);
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UINT8 dst = get_working_register(cpustate, operands >> 4);
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UINT8 src = get_working_register(cpustate, operands & 0x0f);
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UINT16 address = register_pair_read(cpustate, src);
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UINT8 data = cpustate->direct->read_decrypted_byte(address);
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register_write(cpustate, dst, data);
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static void load_to_memory(z8_state *cpustate, address_space *space)
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UINT8 operands = fetch(cpustate);
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UINT8 src = get_working_register(cpustate, operands >> 4);
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UINT8 dst = get_working_register(cpustate, operands & 0x0f);
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UINT16 address = register_pair_read(cpustate, dst);
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UINT8 data = register_read(cpustate, src);
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cpustate->program->write_byte(address, data);
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static void load_from_memory_autoinc(z8_state *cpustate, address_space *space)
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UINT8 operands = fetch(cpustate);
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UINT8 dst = get_working_register(cpustate, operands >> 4);
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UINT8 real_dst = get_intermediate_register(cpustate, dst);
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UINT8 src = get_working_register(cpustate, operands & 0x0f);
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UINT16 address = register_pair_read(cpustate, src);
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UINT8 data = cpustate->direct->read_decrypted_byte(address);
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register_write(cpustate, real_dst, data);
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register_write(cpustate, dst, real_dst + 1);
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register_pair_write(cpustate, src, address + 1);
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static void load_to_memory_autoinc(z8_state *cpustate, address_space *space)
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UINT8 operands = fetch(cpustate);
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UINT8 src = get_working_register(cpustate, operands >> 4);
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UINT8 dst = get_working_register(cpustate, operands & 0x0f);
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UINT8 real_src = get_intermediate_register(cpustate, src);
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UINT16 address = register_pair_read(cpustate, dst);
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UINT8 data = register_read(cpustate, real_src);
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cpustate->program->write_byte(address, data);
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register_pair_write(cpustate, dst, address + 1);
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register_write(cpustate, src, real_src + 1);
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INSTRUCTION( ldc_r1_Irr2 ) { load_from_memory(cpustate, cpustate->program); }
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INSTRUCTION( ldc_r2_Irr1 ) { load_to_memory(cpustate, cpustate->program); }
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INSTRUCTION( ldci_Ir1_Irr2 ) { load_from_memory_autoinc(cpustate, cpustate->program); }
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INSTRUCTION( ldci_Ir2_Irr1 ) { load_to_memory_autoinc(cpustate, cpustate->program); }
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INSTRUCTION( lde_r1_Irr2 ) { load_from_memory(cpustate, cpustate->data); }
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INSTRUCTION( lde_r2_Irr1 ) { load_to_memory(cpustate, cpustate->data); }
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INSTRUCTION( ldei_Ir1_Irr2 ) { load_from_memory_autoinc(cpustate, cpustate->data); }
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INSTRUCTION( ldei_Ir2_Irr1 ) { load_to_memory_autoinc(cpustate, cpustate->data); }
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static void pop(z8_state *cpustate, UINT8 dst)
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register_write(cpustate, dst, stack_pop_byte(cpustate));
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INSTRUCTION( pop_R1 ) { mode_R1(pop) }
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INSTRUCTION( pop_IR1 ) { mode_IR1(pop) }
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static void push(z8_state *cpustate, UINT8 src)
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stack_push_byte(cpustate, read(src));
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INSTRUCTION( push_R2 ) { mode_R1(push) }
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INSTRUCTION( push_IR2 ) { mode_IR1(push) }
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/***************************************************************************
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ARITHMETIC INSTRUCTIONS
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***************************************************************************/
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static void add_carry(z8_state *cpustate, UINT8 dst, INT8 src)
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/* dst <- dst + src + C */
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UINT8 data = register_read(cpustate, dst);
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UINT16 new_data = data + src + flag(C);
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set_flag_c(new_data & 0x100);
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set_flag_z(new_data == 0);
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set_flag_s(new_data & 0x80);
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set_flag_v(((data & 0x80) == (src & 0x80)) && ((new_data & 0x80) != (src & 0x80)));
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set_flag_h(((data & 0x1f) == 0x0f) && ((new_data & 0x1f) == 0x10));
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register_write(cpustate, dst, new_data & 0xff);
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INSTRUCTION( adc_r1_r2 ) { mode_r1_r2(add_carry) }
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INSTRUCTION( adc_r1_Ir2 ) { mode_r1_Ir2(add_carry) }
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INSTRUCTION( adc_R2_R1 ) { mode_R2_R1(add_carry) }
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INSTRUCTION( adc_IR2_R1 ) { mode_IR2_R1(add_carry) }
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INSTRUCTION( adc_R1_IM ) { mode_R1_IM(add_carry) }
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INSTRUCTION( adc_IR1_IM ) { mode_IR1_IM(add_carry) }
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static void add(z8_state *cpustate, UINT8 dst, INT8 src)
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/* dst <- dst + src */
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UINT8 data = register_read(cpustate, dst);
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UINT16 new_data = data + src;
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set_flag_c(new_data & 0x100);
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set_flag_z(new_data == 0);
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set_flag_s(new_data & 0x80);
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set_flag_v(((data & 0x80) == (src & 0x80)) && ((new_data & 0x80) != (src & 0x80)));
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set_flag_h(((data & 0x1f) == 0x0f) && ((new_data & 0x1f) == 0x10));
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register_write(cpustate, dst, new_data & 0xff);
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INSTRUCTION( add_r1_r2 ) { mode_r1_r2(add) }
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INSTRUCTION( add_r1_Ir2 ) { mode_r1_Ir2(add) }
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INSTRUCTION( add_R2_R1 ) { mode_R2_R1(add) }
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INSTRUCTION( add_IR2_R1 ) { mode_IR2_R1(add) }
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INSTRUCTION( add_R1_IM ) { mode_R1_IM(add) }
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INSTRUCTION( add_IR1_IM ) { mode_IR1_IM(add) }
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static void compare(z8_state *cpustate, UINT8 dst, UINT8 src)
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UINT8 data = register_read(cpustate, dst);
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UINT16 new_data = data - src;
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set_flag_c(!(new_data & 0x100));
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set_flag_z(new_data == 0);
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set_flag_s(new_data & 0x80);
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set_flag_v(((data & 0x80) != (src & 0x80)) && ((new_data & 0x80) == (src & 0x80)));
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INSTRUCTION( cp_r1_r2 ) { mode_r1_r2(compare) }
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INSTRUCTION( cp_r1_Ir2 ) { mode_r1_Ir2(compare) }
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INSTRUCTION( cp_R2_R1 ) { mode_R2_R1(compare) }
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INSTRUCTION( cp_IR2_R1 ) { mode_IR2_R1(compare) }
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INSTRUCTION( cp_R1_IM ) { mode_R1_IM(compare) }
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INSTRUCTION( cp_IR1_IM ) { mode_IR1_IM(compare) }
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static void decimal_adjust(z8_state *cpustate, UINT8 dst)
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INSTRUCTION( da_R1 ) { mode_R1(decimal_adjust) }
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INSTRUCTION( da_IR1 ) { mode_IR1(decimal_adjust) }
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static void decrement(z8_state *cpustate, UINT8 dst)
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UINT8 data = register_read(cpustate, dst) - 1;
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set_flag_z(data == 0);
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set_flag_s(data & 0x80);
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set_flag_v(data == 0x7f);
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register_write(cpustate, dst, data);
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INSTRUCTION( dec_R1 ) { mode_R1(decrement) }
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INSTRUCTION( dec_IR1 ) { mode_IR1(decrement) }
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static void decrement_word(z8_state *cpustate, UINT8 dst)
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UINT16 data = register_pair_read(cpustate, dst) - 1;
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set_flag_z(data == 0);
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set_flag_s(data & 0x8000);
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set_flag_v(data == 0x7fff);
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register_pair_write(cpustate, dst, data);
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INSTRUCTION( decw_RR1 ) { mode_RR1(decrement_word) }
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INSTRUCTION( decw_IR1 ) { mode_IR1(decrement_word) }
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static void increment(z8_state *cpustate, UINT8 dst)
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UINT8 data = register_read(cpustate, dst) + 1;
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set_flag_z(data == 0);
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set_flag_s(data & 0x80);
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set_flag_v(data == 0x80);
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register_write(cpustate, dst, data);
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INSTRUCTION( inc_r1 ) { mode_r1(increment) }
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INSTRUCTION( inc_R1 ) { mode_R1(increment) }
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INSTRUCTION( inc_IR1 ) { mode_IR1(increment) }
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static void increment_word(z8_state *cpustate, UINT8 dst)
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UINT16 data = register_pair_read(cpustate, dst) + 1;
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set_flag_z(data == 0);
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set_flag_s(data & 0x8000);
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set_flag_v(data == 0x8000);
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register_pair_write(cpustate, dst, data);
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INSTRUCTION( incw_RR1 ) { mode_RR1(increment_word) }
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INSTRUCTION( incw_IR1 ) { mode_IR1(increment_word) }
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static void subtract_carry(z8_state *cpustate, UINT8 dst, UINT8 src)
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/* dst <- dst - src - C */
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UINT8 data = register_read(cpustate, dst);
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UINT16 new_data = data - src;
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set_flag_c(!(new_data & 0x100));
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set_flag_z(new_data == 0);
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set_flag_s(new_data & 0x80);
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set_flag_v(((data & 0x80) != (src & 0x80)) && ((new_data & 0x80) == (src & 0x80)));
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set_flag_h(!(((data & 0x1f) == 0x0f) && ((new_data & 0x1f) == 0x10)));
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register_write(cpustate, dst, new_data & 0xff);
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INSTRUCTION( sbc_r1_r2 ) { mode_r1_r2(subtract_carry) }
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INSTRUCTION( sbc_r1_Ir2 ) { mode_r1_Ir2(subtract_carry) }
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INSTRUCTION( sbc_R2_R1 ) { mode_R2_R1(subtract_carry) }
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INSTRUCTION( sbc_IR2_R1 ) { mode_IR2_R1(subtract_carry) }
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INSTRUCTION( sbc_R1_IM ) { mode_R1_IM(subtract_carry) }
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INSTRUCTION( sbc_IR1_IM ) { mode_IR1_IM(subtract_carry) }
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static void subtract(z8_state *cpustate, UINT8 dst, UINT8 src)
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/* dst <- dst - src */
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UINT8 data = register_read(cpustate, dst);
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UINT16 new_data = data - src;
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set_flag_c(!(new_data & 0x100));
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set_flag_z(new_data == 0);
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set_flag_s(new_data & 0x80);
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set_flag_v(((data & 0x80) != (src & 0x80)) && ((new_data & 0x80) == (src & 0x80)));
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set_flag_h(!(((data & 0x1f) == 0x0f) && ((new_data & 0x1f) == 0x10)));
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register_write(cpustate, dst, new_data & 0xff);
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INSTRUCTION( sub_r1_r2 ) { mode_r1_r2(subtract) }
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INSTRUCTION( sub_r1_Ir2 ) { mode_r1_Ir2(subtract) }
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INSTRUCTION( sub_R2_R1 ) { mode_R2_R1(subtract) }
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INSTRUCTION( sub_IR2_R1 ) { mode_IR2_R1(subtract) }
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INSTRUCTION( sub_R1_IM ) { mode_R1_IM(subtract) }
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INSTRUCTION( sub_IR1_IM ) { mode_IR1_IM(subtract) }
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/***************************************************************************
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***************************************************************************/
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static void _and(z8_state *cpustate, UINT8 dst, UINT8 src)
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/* dst <- dst AND src */
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UINT8 data = register_read(cpustate, dst) & src;
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register_write(cpustate, dst, data);
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set_flag_z(data == 0);
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set_flag_s(data & 0x80);
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INSTRUCTION( and_r1_r2 ) { mode_r1_r2(_and) }
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INSTRUCTION( and_r1_Ir2 ) { mode_r1_Ir2(_and) }
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INSTRUCTION( and_R2_R1 ) { mode_R2_R1(_and) }
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INSTRUCTION( and_IR2_R1 ) { mode_IR2_R1(_and) }
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INSTRUCTION( and_R1_IM ) { mode_R1_IM(_and) }
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INSTRUCTION( and_IR1_IM ) { mode_IR1_IM(_and) }
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static void complement(z8_state *cpustate, UINT8 dst)
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UINT8 data = register_read(cpustate, dst) ^ 0xff;
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register_write(cpustate, dst, data);
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set_flag_z(data == 0);
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set_flag_s(data & 0x80);
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INSTRUCTION( com_R1 ) { mode_R1(complement) }
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INSTRUCTION( com_IR1 ) { mode_IR1(complement) }
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static void _or(z8_state *cpustate, UINT8 dst, UINT8 src)
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/* dst <- dst OR src */
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UINT8 data = register_read(cpustate, dst) | src;
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register_write(cpustate, dst, data);
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set_flag_z(data == 0);
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set_flag_s(data & 0x80);
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INSTRUCTION( or_r1_r2 ) { mode_r1_r2(_or) }
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INSTRUCTION( or_r1_Ir2 ) { mode_r1_Ir2(_or) }
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INSTRUCTION( or_R2_R1 ) { mode_R2_R1(_or) }
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INSTRUCTION( or_IR2_R1 ) { mode_IR2_R1(_or) }
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INSTRUCTION( or_R1_IM ) { mode_R1_IM(_or) }
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INSTRUCTION( or_IR1_IM ) { mode_IR1_IM(_or) }
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static void _xor(z8_state *cpustate, UINT8 dst, UINT8 src)
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/* dst <- dst XOR src */
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UINT8 data = register_read(cpustate, dst) ^ src;
469
register_write(cpustate, dst, data);
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set_flag_z(data == 0);
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set_flag_s(data & 0x80);
476
INSTRUCTION( xor_r1_r2 ) { mode_r1_r2(_xor) }
477
INSTRUCTION( xor_r1_Ir2 ) { mode_r1_Ir2(_xor) }
478
INSTRUCTION( xor_R2_R1 ) { mode_R2_R1(_xor) }
479
INSTRUCTION( xor_IR2_R1 ) { mode_IR2_R1(_xor) }
480
INSTRUCTION( xor_R1_IM ) { mode_R1_IM(_xor) }
481
INSTRUCTION( xor_IR1_IM ) { mode_IR1_IM(_xor) }
483
/***************************************************************************
484
PROGRAM CONTROL INSTRUCTIONS
485
***************************************************************************/
487
static void call(z8_state *cpustate, UINT16 dst)
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stack_push_word(cpustate, cpustate->pc);
493
INSTRUCTION( call_IRR1 ) { UINT16 dst = register_pair_read(cpustate, get_intermediate_register(cpustate, get_register(cpustate, fetch(cpustate)))); call(cpustate, dst); }
494
INSTRUCTION( call_DA ) { UINT16 dst = (fetch(cpustate) << 8) | fetch(cpustate); call(cpustate, dst); }
496
INSTRUCTION( djnz_r1_RA )
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INT8 ra = (INT8)fetch(cpustate);
501
int r = get_working_register(cpustate, opcode >> 4);
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UINT8 data = register_read(cpustate, r) - 1;
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register_write(cpustate, r, data);
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/* if r<>0, PC <- PC + dst */
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register_write(cpustate, Z8_REGISTER_FLAGS, stack_pop_byte(cpustate));
521
cpustate->pc = stack_pop_word(cpustate);
524
cpustate->r[Z8_REGISTER_IMR] |= Z8_IMR_ENABLE;
531
cpustate->pc = stack_pop_word(cpustate);
534
static void jump(z8_state *cpustate, UINT16 dst)
540
INSTRUCTION( jp_IRR1 ) { jump(cpustate, register_pair_read(cpustate, IR)); }
542
static int check_condition_code(z8_state *cpustate, int cc)
548
case CC_F: truth = 0; break;
549
case CC_LT: truth = flag(S) ^ flag(V); break;
550
case CC_LE: truth = (flag(Z) | (flag(S) ^ flag(V))); break;
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case CC_ULE: truth = flag(C) | flag(Z); break;
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case CC_OV: truth = flag(V); break;
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case CC_MI: truth = flag(S); break;
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case CC_Z: truth = flag(Z); break;
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case CC_C: truth = flag(C); break;
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case CC_T: truth = 1; break;
557
case CC_GE: truth = !(flag(S) ^ flag(V)); break;
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case CC_GT: truth = !(flag(Z) | (flag(S) ^ flag(V))); break;
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case CC_UGT: truth = ((!flag(C)) & (!flag(Z))); break;
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case CC_NOV: truth = !flag(V); break;
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case CC_PL: truth = !flag(S); break;
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case CC_NZ: truth = !flag(Z); break;
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case CC_NC: truth = !flag(C); break;
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INSTRUCTION( jp_cc_DA )
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UINT16 dst = (fetch(cpustate) << 8) | fetch(cpustate);
573
/* if cc is true, then PC <- dst */
574
if (check_condition_code(cpustate, opcode >> 4))
581
INSTRUCTION( jr_cc_RA )
583
INT8 ra = (INT8)fetch(cpustate);
584
UINT16 dst = cpustate->pc + ra;
586
/* if cc is true, then PC <- dst */
587
if (check_condition_code(cpustate, opcode >> 4))
594
/***************************************************************************
595
BIT MANIPULATION INSTRUCTIONS
596
***************************************************************************/
598
static void test_complement_under_mask(z8_state *cpustate, UINT8 dst, UINT8 src)
600
/* NOT(dst) AND src */
601
UINT8 data = (register_read(cpustate, dst) ^ 0xff) & src;
603
set_flag_z(data == 0);
604
set_flag_s(data & 0x80);
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INSTRUCTION( tcm_r1_r2 ) { mode_r1_r2(test_complement_under_mask) }
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INSTRUCTION( tcm_r1_Ir2 ) { mode_r1_Ir2(test_complement_under_mask) }
610
INSTRUCTION( tcm_R2_R1 ) { mode_R2_R1(test_complement_under_mask) }
611
INSTRUCTION( tcm_IR2_R1 ) { mode_IR2_R1(test_complement_under_mask) }
612
INSTRUCTION( tcm_R1_IM ) { mode_R1_IM(test_complement_under_mask) }
613
INSTRUCTION( tcm_IR1_IM ) { mode_IR1_IM(test_complement_under_mask) }
615
static void test_under_mask(z8_state *cpustate, UINT8 dst, UINT8 src)
618
UINT8 data = register_read(cpustate, dst) & src;
620
set_flag_z(data == 0);
621
set_flag_s(data & 0x80);
625
INSTRUCTION( tm_r1_r2 ) { mode_r1_r2(test_under_mask) }
626
INSTRUCTION( tm_r1_Ir2 ) { mode_r1_Ir2(test_under_mask) }
627
INSTRUCTION( tm_R2_R1 ) { mode_R2_R1(test_under_mask) }
628
INSTRUCTION( tm_IR2_R1 ) { mode_IR2_R1(test_under_mask) }
629
INSTRUCTION( tm_R1_IM ) { mode_R1_IM(test_under_mask) }
630
INSTRUCTION( tm_IR1_IM ) { mode_IR1_IM(test_under_mask) }
632
/***************************************************************************
633
ROTATE AND SHIFT INSTRUCTIONS
634
***************************************************************************/
636
static void rotate_left(z8_state *cpustate, UINT8 dst)
639
UINT8 data = register_read(cpustate, dst);
640
UINT8 new_data = (data << 1) | BIT(data, 7);
642
set_flag_c(data & 0x80);
643
set_flag_z(data == 0);
644
set_flag_s(new_data & 0x80);
645
set_flag_v((data & 0x80) != (new_data & 0x80));
647
register_write(cpustate, dst, new_data);
650
INSTRUCTION( rl_R1 ) { mode_R1(rotate_left) }
651
INSTRUCTION( rl_IR1 ) { mode_IR1(rotate_left) }
653
static void rotate_left_carry(z8_state *cpustate, UINT8 dst)
656
UINT8 data = register_read(cpustate, dst);
657
UINT8 new_data = (data << 1) | flag(C);
659
set_flag_c(data & 0x80);
660
set_flag_z(data == 0);
661
set_flag_s(new_data & 0x80);
662
set_flag_v((data & 0x80) != (new_data & 0x80));
664
register_write(cpustate, dst, new_data);
667
INSTRUCTION( rlc_R1 ) { mode_R1(rotate_left_carry) }
668
INSTRUCTION( rlc_IR1 ) { mode_IR1(rotate_left_carry) }
670
static void rotate_right(z8_state *cpustate, UINT8 dst)
673
UINT8 data = register_read(cpustate, dst);
674
UINT8 new_data = ((data & 0x01) << 7) | (data >> 1);
676
set_flag_c(data & 0x01);
677
set_flag_z(data == 0);
678
set_flag_s(new_data & 0x80);
679
set_flag_v((data & 0x80) != (new_data & 0x80));
681
register_write(cpustate, dst, new_data);
684
INSTRUCTION( rr_R1 ) { mode_R1(rotate_right) }
685
INSTRUCTION( rr_IR1 ) { mode_IR1(rotate_right) }
687
static void rotate_right_carry(z8_state *cpustate, UINT8 dst)
690
UINT8 data = register_read(cpustate, dst);
691
UINT8 new_data = (flag(C) << 7) | (data >> 1);
693
set_flag_c(data & 0x01);
694
set_flag_z(data == 0);
695
set_flag_s(new_data & 0x80);
696
set_flag_v((data & 0x80) != (new_data & 0x80));
698
register_write(cpustate, dst, new_data);
701
INSTRUCTION( rrc_R1 ) { mode_R1(rotate_right_carry) }
702
INSTRUCTION( rrc_IR1 ) { mode_IR1(rotate_right_carry) }
704
static void shift_right_arithmetic(z8_state *cpustate, UINT8 dst)
707
UINT8 data = register_read(cpustate, dst);
708
UINT8 new_data = (data & 0x80) | ((data >> 1) & 0x7f);
710
set_flag_c(data & 0x01);
711
set_flag_z(data == 0);
712
set_flag_s(new_data & 0x80);
715
register_write(cpustate, dst, new_data);
718
INSTRUCTION( sra_R1 ) { mode_R1(shift_right_arithmetic) }
719
INSTRUCTION( sra_IR1 ) { mode_IR1(shift_right_arithmetic) }
721
static void swap(z8_state *cpustate, UINT8 dst)
723
/* dst(7-4) <-> dst(3-0) */
724
UINT8 data = register_read(cpustate, dst);
725
data = (data << 4) | (data >> 4);
726
register_write(cpustate, dst, data);
728
set_flag_z(data == 0);
729
set_flag_s(data & 0x80);
730
// set_flag_v(0); undefined
733
INSTRUCTION( swap_R1 ) { mode_R1(swap) }
734
INSTRUCTION( swap_IR1 ) { mode_IR1(swap) }
736
/***************************************************************************
737
CPU CONTROL INSTRUCTIONS
738
***************************************************************************/
740
INSTRUCTION( ccf ) { cpustate->r[Z8_REGISTER_FLAGS] ^= Z8_FLAGS_C; }
741
INSTRUCTION( di ) { cpustate->r[Z8_REGISTER_IMR] &= ~Z8_IMR_ENABLE; }
742
INSTRUCTION( ei ) { cpustate->r[Z8_REGISTER_IMR] |= Z8_IMR_ENABLE; }
743
INSTRUCTION( nop ) { /* no operation */ }
744
INSTRUCTION( rcf ) { set_flag_c(0); }
745
INSTRUCTION( scf ) { set_flag_c(1); }
746
INSTRUCTION( srp_IM ) { cpustate->r[Z8_REGISTER_RP] = fetch(cpustate); }