1
/* author: stephen crowley, crow@debian.org */
4
* Permission is hereby granted, free of charge, to any person obtaining a
5
* copy of this software and associated documentation files (the "Software"),
6
* to deal in the Software without restriction, including without limitation
7
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
* and/or sell copies of the Software, and to permit persons to whom the
9
* Software is furnished to do so, subject to the following conditions:
11
* The above copyright notice and this permission notice shall be included
12
* in all copies or substantial portions of the Software.
14
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
* STEPHEN CROWLEY, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
18
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
20
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22
/* $XFree86: xc/lib/GL/mesa/src/drv/mga/mgaregs.h,v 1.6 2003/01/12 03:55:46 tsi Exp $ */
27
/*************** (START) AUTOMATICLY GENERATED REGISTER FILE *****************/
29
* Generated on Wed Jan 26 13:44:46 MST 2000
35
* Power Graphic Mode Memory Space Registers
38
#define MGAREG_MGA_EXEC 0x0100
39
#define MGAREG_AGP_PLL 0x1e4c
41
# define AGP_PLL_agp2xpllen_MASK 0xfffffffe /* bit 0 */
42
# define AGP_PLL_agp2xpllen_disable 0x0
43
# define AGP_PLL_agp2xpllen_enable 0x1
45
#define MGAREG_CFG_OR 0x1e4c
47
# define CFG_OR_comp_or_MASK 0xfffffff7 /* bit 3 */
48
# define CFG_OR_comp_or_disable 0x0
49
# define CFG_OR_comp_or_enable 0x8
50
# define CFG_OR_compfreq_MASK 0xffffff0f /* bits 4-7 */
51
# define CFG_OR_compfreq_SHIFT 4
52
# define CFG_OR_comporup_MASK 0xfffff0ff /* bits 8-11 */
53
# define CFG_OR_comporup_SHIFT 8
54
# define CFG_OR_compordn_MASK 0xffff0fff /* bits 12-15 */
55
# define CFG_OR_compordn_SHIFT 12
56
# define CFG_OR_e2pq_MASK 0xfffeffff /* bit 16 */
57
# define CFG_OR_e2pq_disable 0x0
58
# define CFG_OR_e2pq_enable 0x10000
59
# define CFG_OR_e2pqbypcsn_MASK 0xfffdffff /* bit 17 */
60
# define CFG_OR_e2pqbypcsn_disable 0x0
61
# define CFG_OR_e2pqbypcsn_enable 0x20000
62
# define CFG_OR_e2pqbypd_MASK 0xfffbffff /* bit 18 */
63
# define CFG_OR_e2pqbypd_disable 0x0
64
# define CFG_OR_e2pqbypd_enable 0x40000
65
# define CFG_OR_e2pbypclk_MASK 0xfff7ffff /* bit 19 */
66
# define CFG_OR_e2pbypclk_disable 0x0
67
# define CFG_OR_e2pbypclk_enable 0x80000
68
# define CFG_OR_e2pbyp_MASK 0xffefffff /* bit 20 */
69
# define CFG_OR_e2pbyp_disable 0x0
70
# define CFG_OR_e2pbyp_enable 0x100000
71
# define CFG_OR_rate_cap_or_MASK 0xff1fffff /* bits 21-23 */
72
# define CFG_OR_rate_cap_or_SHIFT 21
73
# define CFG_OR_rq_or_MASK 0xe0ffffff /* bits 24-28 */
74
# define CFG_OR_rq_or_SHIFT 24
76
#define MGAREG_ALPHACTRL 0x2c7c
78
# define AC_src_MASK 0xfffffff0 /* bits 0-3 */
79
# define AC_src_zero 0x0 /* val 0, shift 0 */
80
# define AC_src_one 0x1 /* val 1, shift 0 */
81
# define AC_src_dst_color 0x2 /* val 2, shift 0 */
82
# define AC_src_om_dst_color 0x3 /* val 3, shift 0 */
83
# define AC_src_src_alpha 0x4 /* val 4, shift 0 */
84
# define AC_src_om_src_alpha 0x5 /* val 5, shift 0 */
85
# define AC_src_dst_alpha 0x6 /* val 6, shift 0 */
86
# define AC_src_om_dst_alpha 0x7 /* val 7, shift 0 */
87
# define AC_src_src_alpha_sat 0x8 /* val 8, shift 0 */
88
# define AC_dst_MASK 0xffffff0f /* bits 4-7 */
89
# define AC_dst_zero 0x0 /* val 0, shift 4 */
90
# define AC_dst_one 0x10 /* val 1, shift 4 */
91
# define AC_dst_src_color 0x20 /* val 2, shift 4 */
92
# define AC_dst_om_src_color 0x30 /* val 3, shift 4 */
93
# define AC_dst_src_alpha 0x40 /* val 4, shift 4 */
94
# define AC_dst_om_src_alpha 0x50 /* val 5, shift 4 */
95
# define AC_dst_dst_alpha 0x60 /* val 6, shift 4 */
96
# define AC_dst_om_dst_alpha 0x70 /* val 7, shift 4 */
97
# define AC_amode_MASK 0xfffffcff /* bits 8-9 */
98
# define AC_amode_FCOL 0x0 /* val 0, shift 8 */
99
# define AC_amode_alpha_channel 0x100 /* val 1, shift 8 */
100
# define AC_amode_video_alpha 0x200 /* val 2, shift 8 */
101
# define AC_amode_RSVD 0x300 /* val 3, shift 8 */
102
# define AC_astipple_MASK 0xfffff7ff /* bit 11 */
103
# define AC_astipple_disable 0x0
104
# define AC_astipple_enable 0x800
105
# define AC_aten_MASK 0xffffefff /* bit 12 */
106
# define AC_aten_disable 0x0
107
# define AC_aten_enable 0x1000
108
# define AC_atmode_MASK 0xffff1fff /* bits 13-15 */
109
# define AC_atmode_noacmp 0x0 /* val 0, shift 13 */
110
# define AC_atmode_ae 0x4000 /* val 2, shift 13 */
111
# define AC_atmode_ane 0x6000 /* val 3, shift 13 */
112
# define AC_atmode_alt 0x8000 /* val 4, shift 13 */
113
# define AC_atmode_alte 0xa000 /* val 5, shift 13 */
114
# define AC_atmode_agt 0xc000 /* val 6, shift 13 */
115
# define AC_atmode_agte 0xe000 /* val 7, shift 13 */
116
# define AC_atref_MASK 0xff00ffff /* bits 16-23 */
117
# define AC_atref_SHIFT 16
118
# define AC_alphasel_MASK 0xfcffffff /* bits 24-25 */
119
# define AC_alphasel_fromtex 0x0 /* val 0, shift 24 */
120
# define AC_alphasel_diffused 0x1000000 /* val 1, shift 24 */
121
# define AC_alphasel_modulated 0x2000000 /* val 2, shift 24 */
122
# define AC_alphasel_trans 0x3000000 /* val 3, shift 24 */
124
#define MGAREG_ALPHASTART 0x2c70
125
#define MGAREG_ALPHAXINC 0x2c74
126
#define MGAREG_ALPHAYINC 0x2c78
127
#define MGAREG_AR0 0x1c60
129
# define AR0_ar0_MASK 0xfffc0000 /* bits 0-17 */
130
# define AR0_ar0_SHIFT 0
132
#define MGAREG_AR1 0x1c64
134
# define AR1_ar1_MASK 0xff000000 /* bits 0-23 */
135
# define AR1_ar1_SHIFT 0
137
#define MGAREG_AR2 0x1c68
139
# define AR2_ar2_MASK 0xfffc0000 /* bits 0-17 */
140
# define AR2_ar2_SHIFT 0
142
#define MGAREG_AR3 0x1c6c
144
# define AR3_ar3_MASK 0xff000000 /* bits 0-23 */
145
# define AR3_ar3_SHIFT 0
146
# define AR3_spage_MASK 0xf8ffffff /* bits 24-26 */
147
# define AR3_spage_SHIFT 24
149
#define MGAREG_AR4 0x1c70
151
# define AR4_ar4_MASK 0xfffc0000 /* bits 0-17 */
152
# define AR4_ar4_SHIFT 0
154
#define MGAREG_AR5 0x1c74
156
# define AR5_ar5_MASK 0xfffc0000 /* bits 0-17 */
157
# define AR5_ar5_SHIFT 0
159
#define MGAREG_AR6 0x1c78
161
# define AR6_ar6_MASK 0xfffc0000 /* bits 0-17 */
162
# define AR6_ar6_SHIFT 0
164
#define MGAREG_BCOL 0x1c20
165
#define MGAREG_BESA1CORG 0x3d10
166
#define MGAREG_BESA1ORG 0x3d00
167
#define MGAREG_BESA2CORG 0x3d14
168
#define MGAREG_BESA2ORG 0x3d04
169
#define MGAREG_BESB1CORG 0x3d18
170
#define MGAREG_BESB1ORG 0x3d08
171
#define MGAREG_BESB2CORG 0x3d1c
172
#define MGAREG_BESB2ORG 0x3d0c
173
#define MGAREG_BESCTL 0x3d20
175
# define BC_besen_MASK 0xfffffffe /* bit 0 */
176
# define BC_besen_disable 0x0
177
# define BC_besen_enable 0x1
178
# define BC_besv1srcstp_MASK 0xffffffbf /* bit 6 */
179
# define BC_besv1srcstp_even 0x0
180
# define BC_besv1srcstp_odd 0x40
181
# define BC_besv2srcstp_MASK 0xfffffeff /* bit 8 */
182
# define BC_besv2srcstp_disable 0x0
183
# define BC_besv2srcstp_enable 0x100
184
# define BC_beshfen_MASK 0xfffffbff /* bit 10 */
185
# define BC_beshfen_disable 0x0
186
# define BC_beshfen_enable 0x400
187
# define BC_besvfen_MASK 0xfffff7ff /* bit 11 */
188
# define BC_besvfen_disable 0x0
189
# define BC_besvfen_enable 0x800
190
# define BC_beshfixc_MASK 0xffffefff /* bit 12 */
191
# define BC_beshfixc_weight 0x0
192
# define BC_beshfixc_coeff 0x1000
193
# define BC_bescups_MASK 0xfffeffff /* bit 16 */
194
# define BC_bescups_disable 0x0
195
# define BC_bescups_enable 0x10000
196
# define BC_bes420pl_MASK 0xfffdffff /* bit 17 */
197
# define BC_bes420pl_422 0x0
198
# define BC_bes420pl_420 0x20000
199
# define BC_besdith_MASK 0xfffbffff /* bit 18 */
200
# define BC_besdith_disable 0x0
201
# define BC_besdith_enable 0x40000
202
# define BC_beshmir_MASK 0xfff7ffff /* bit 19 */
203
# define BC_beshmir_disable 0x0
204
# define BC_beshmir_enable 0x80000
205
# define BC_besbwen_MASK 0xffefffff /* bit 20 */
206
# define BC_besbwen_color 0x0
207
# define BC_besbwen_bw 0x100000
208
# define BC_besblank_MASK 0xffdfffff /* bit 21 */
209
# define BC_besblank_disable 0x0
210
# define BC_besblank_enable 0x200000
211
# define BC_besfselm_MASK 0xfeffffff /* bit 24 */
212
# define BC_besfselm_soft 0x0
213
# define BC_besfselm_hard 0x1000000
214
# define BC_besfsel_MASK 0xf9ffffff /* bits 25-26 */
215
# define BC_besfsel_a1 0x0 /* val 0, shift 25 */
216
# define BC_besfsel_a2 0x2000000 /* val 1, shift 25 */
217
# define BC_besfsel_b1 0x4000000 /* val 2, shift 25 */
218
# define BC_besfsel_b2 0x6000000 /* val 3, shift 25 */
220
#define MGAREG_BESGLOBCTL 0x3dc0
222
# define BGC_beshzoom_MASK 0xfffffffe /* bit 0 */
223
# define BGC_beshzoom_disable 0x0
224
# define BGC_beshzoom_enable 0x1
225
# define BGC_beshzoomf_MASK 0xfffffffd /* bit 1 */
226
# define BGC_beshzoomf_disable 0x0
227
# define BGC_beshzoomf_enable 0x2
228
# define BGC_bescorder_MASK 0xfffffff7 /* bit 3 */
229
# define BGC_bescorder_even 0x0
230
# define BGC_bescorder_odd 0x8
231
# define BGC_besreghup_MASK 0xffffffef /* bit 4 */
232
# define BGC_besreghup_disable 0x0
233
# define BGC_besreghup_enable 0x10
234
# define BGC_besvcnt_MASK 0xf000ffff /* bits 16-27 */
235
# define BGC_besvcnt_SHIFT 16
237
#define MGAREG_BESHCOORD 0x3d28
239
# define BHC_besright_MASK 0xfffff800 /* bits 0-10 */
240
# define BHC_besright_SHIFT 0
241
# define BHC_besleft_MASK 0xf800ffff /* bits 16-26 */
242
# define BHC_besleft_SHIFT 16
244
#define MGAREG_BESHISCAL 0x3d30
246
# define BHISF_beshiscal_MASK 0xffe00003 /* bits 2-20 */
247
# define BHISF_beshiscal_SHIFT 2
249
#define MGAREG_BESHSRCEND 0x3d3c
251
# define BHSE_beshsrcend_MASK 0xfc000003 /* bits 2-25 */
252
# define BHSE_beshsrcend_SHIFT 2
254
#define MGAREG_BESHSRCLST 0x3d50
256
# define BHSL_beshsrclst_MASK 0xfc00ffff /* bits 16-25 */
257
# define BHSL_beshsrclst_SHIFT 16
259
#define MGAREG_BESHSRCST 0x3d38
261
# define BHSS_beshsrcst_MASK 0xfc000003 /* bits 2-25 */
262
# define BHSS_beshsrcst_SHIFT 2
264
#define MGAREG_BESPITCH 0x3d24
266
# define BP_bespitch_MASK 0xfffff000 /* bits 0-11 */
267
# define BP_bespitch_SHIFT 0
269
#define MGAREG_BESSTATUS 0x3dc4
271
# define BS_besstat_MASK 0xfffffffc /* bits 0-1 */
272
# define BS_besstat_a1 0x0 /* val 0, shift 0 */
273
# define BS_besstat_a2 0x1 /* val 1, shift 0 */
274
# define BS_besstat_b1 0x2 /* val 2, shift 0 */
275
# define BS_besstat_b2 0x3 /* val 3, shift 0 */
277
#define MGAREG_BESV1SRCLST 0x3d54
279
# define BSF_besv1srclast_MASK 0xfffffc00 /* bits 0-9 */
280
# define BSF_besv1srclast_SHIFT 0
282
#define MGAREG_BESV2SRCLST 0x3d58
284
# define BSF_besv2srclst_MASK 0xfffffc00 /* bits 0-9 */
285
# define BSF_besv2srclst_SHIFT 0
287
#define MGAREG_BESV1WGHT 0x3d48
289
# define BSF_besv1wght_MASK 0xffff0003 /* bits 2-15 */
290
# define BSF_besv1wght_SHIFT 2
291
# define BSF_besv1wghts_MASK 0xfffeffff /* bit 16 */
292
# define BSF_besv1wghts_disable 0x0
293
# define BSF_besv1wghts_enable 0x10000
295
#define MGAREG_BESV2WGHT 0x3d4c
297
# define BSF_besv2wght_MASK 0xffff0003 /* bits 2-15 */
298
# define BSF_besv2wght_SHIFT 2
299
# define BSF_besv2wghts_MASK 0xfffeffff /* bit 16 */
300
# define BSF_besv2wghts_disable 0x0
301
# define BSF_besv2wghts_enable 0x10000
303
#define MGAREG_BESVCOORD 0x3d2c
305
# define BVC_besbot_MASK 0xfffff800 /* bits 0-10 */
306
# define BVC_besbot_SHIFT 0
307
# define BVC_bestop_MASK 0xf800ffff /* bits 16-26 */
308
# define BVC_bestop_SHIFT 16
310
#define MGAREG_BESVISCAL 0x3d34
312
# define BVISF_besviscal_MASK 0xffe00003 /* bits 2-20 */
313
# define BVISF_besviscal_SHIFT 2
315
#define MGAREG_CODECADDR 0x3e44
316
#define MGAREG_CODECCTL 0x3e40
317
#define MGAREG_CODECHARDPTR 0x3e4c
318
#define MGAREG_CODECHOSTPTR 0x3e48
319
#define MGAREG_CODECLCODE 0x3e50
320
#define MGAREG_CXBNDRY 0x1c80
322
# define CXB_cxleft_MASK 0xfffff000 /* bits 0-11 */
323
# define CXB_cxleft_SHIFT 0
324
# define CXB_cxright_MASK 0xf000ffff /* bits 16-27 */
325
# define CXB_cxright_SHIFT 16
327
#define MGAREG_CXLEFT 0x1ca0
328
#define MGAREG_CXRIGHT 0x1ca4
329
#define MGAREG_DMAMAP30 0x1e30
330
#define MGAREG_DMAMAP74 0x1e34
331
#define MGAREG_DMAMAPB8 0x1e38
332
#define MGAREG_DMAMAPFC 0x1e3c
333
#define MGAREG_DMAPAD 0x1c54
334
#define MGAREG_DR0_Z32LSB 0x2c50
335
#define MGAREG_DR0_Z32MSB 0x2c54
336
#define MGAREG_DR2_Z32LSB 0x2c60
337
#define MGAREG_DR2_Z32MSB 0x2c64
338
#define MGAREG_DR3_Z32LSB 0x2c68
339
#define MGAREG_DR3_Z32MSB 0x2c6c
340
#define MGAREG_DR0 0x1cc0
341
#define MGAREG_DR2 0x1cc8
342
#define MGAREG_DR3 0x1ccc
343
#define MGAREG_DR4 0x1cd0
344
#define MGAREG_DR6 0x1cd8
345
#define MGAREG_DR7 0x1cdc
346
#define MGAREG_DR8 0x1ce0
347
#define MGAREG_DR10 0x1ce8
348
#define MGAREG_DR11 0x1cec
349
#define MGAREG_DR12 0x1cf0
350
#define MGAREG_DR14 0x1cf8
351
#define MGAREG_DR15 0x1cfc
352
#define MGAREG_DSTORG 0x2cb8
354
# define DO_dstmap_MASK 0xfffffffe /* bit 0 */
355
# define DO_dstmap_fb 0x0
356
# define DO_dstmap_sys 0x1
357
# define DO_dstacc_MASK 0xfffffffd /* bit 1 */
358
# define DO_dstacc_pci 0x0
359
# define DO_dstacc_agp 0x2
360
# define DO_dstorg_MASK 0x7 /* bits 3-31 */
361
# define DO_dstorg_SHIFT 3
363
#define MGAREG_DWG_INDIR_WT 0x1e80
364
#define MGAREG_DWGCTL 0x1c00
366
# define DC_opcod_MASK 0xfffffff0 /* bits 0-3 */
367
# define DC_opcod_line_open 0x0 /* val 0, shift 0 */
368
# define DC_opcod_autoline_open 0x1 /* val 1, shift 0 */
369
# define DC_opcod_line_close 0x2 /* val 2, shift 0 */
370
# define DC_opcod_autoline_close 0x3 /* val 3, shift 0 */
371
# define DC_opcod_trap 0x4 /* val 4, shift 0 */
372
# define DC_opcod_texture_trap 0x6 /* val 6, shift 0 */
373
# define DC_opcod_bitblt 0x8 /* val 8, shift 0 */
374
# define DC_opcod_iload 0x9 /* val 9, shift 0 */
375
# define DC_atype_MASK 0xffffff8f /* bits 4-6 */
376
# define DC_atype_rpl 0x0 /* val 0, shift 4 */
377
# define DC_atype_rstr 0x10 /* val 1, shift 4 */
378
# define DC_atype_zi 0x30 /* val 3, shift 4 */
379
# define DC_atype_blk 0x40 /* val 4, shift 4 */
380
# define DC_atype_i 0x70 /* val 7, shift 4 */
381
# define DC_linear_MASK 0xffffff7f /* bit 7 */
382
# define DC_linear_xy 0x0
383
# define DC_linear_linear 0x80
384
# define DC_zmode_MASK 0xfffff8ff /* bits 8-10 */
385
# define DC_zmode_nozcmp 0x0 /* val 0, shift 8 */
386
# define DC_zmode_ze 0x200 /* val 2, shift 8 */
387
# define DC_zmode_zne 0x300 /* val 3, shift 8 */
388
# define DC_zmode_zlt 0x400 /* val 4, shift 8 */
389
# define DC_zmode_zlte 0x500 /* val 5, shift 8 */
390
# define DC_zmode_zgt 0x600 /* val 6, shift 8 */
391
# define DC_zmode_zgte 0x700 /* val 7, shift 8 */
392
# define DC_solid_MASK 0xfffff7ff /* bit 11 */
393
# define DC_solid_disable 0x0
394
# define DC_solid_enable 0x800
395
# define DC_arzero_MASK 0xffffefff /* bit 12 */
396
# define DC_arzero_disable 0x0
397
# define DC_arzero_enable 0x1000
398
# define DC_sgnzero_MASK 0xffffdfff /* bit 13 */
399
# define DC_sgnzero_disable 0x0
400
# define DC_sgnzero_enable 0x2000
401
# define DC_shftzero_MASK 0xffffbfff /* bit 14 */
402
# define DC_shftzero_disable 0x0
403
# define DC_shftzero_enable 0x4000
404
# define DC_bop_MASK 0xfff0ffff /* bits 16-19 */
405
# define DC_bop_SHIFT 16
406
# define DC_trans_MASK 0xff0fffff /* bits 20-23 */
407
# define DC_trans_SHIFT 20
408
# define DC_bltmod_MASK 0xe1ffffff /* bits 25-28 */
409
# define DC_bltmod_bmonolef 0x0 /* val 0, shift 25 */
410
# define DC_bltmod_bmonowf 0x8000000 /* val 4, shift 25 */
411
# define DC_bltmod_bplan 0x2000000 /* val 1, shift 25 */
412
# define DC_bltmod_bfcol 0x4000000 /* val 2, shift 25 */
413
# define DC_bltmod_bu32bgr 0x6000000 /* val 3, shift 25 */
414
# define DC_bltmod_bu32rgb 0xe000000 /* val 7, shift 25 */
415
# define DC_bltmod_bu24bgr 0x16000000 /* val 11, shift 25 */
416
# define DC_bltmod_bu24rgb 0x1e000000 /* val 15, shift 25 */
417
# define DC_pattern_MASK 0xdfffffff /* bit 29 */
418
# define DC_pattern_disable 0x0
419
# define DC_pattern_enable 0x20000000
420
# define DC_transc_MASK 0xbfffffff /* bit 30 */
421
# define DC_transc_disable 0x0
422
# define DC_transc_enable 0x40000000
423
# define DC_clipdis_MASK 0x7fffffff /* bit 31 */
424
# define DC_clipdis_disable 0x0
425
# define DC_clipdis_enable 0x80000000
427
#define MGAREG_DWGSYNC 0x2c4c
429
# define DS_dwgsyncaddr_MASK 0x3 /* bits 2-31 */
430
# define DS_dwgsyncaddr_SHIFT 2
432
#define MGAREG_FCOL 0x1c24
433
#define MGAREG_FIFOSTATUS 0x1e10
435
# define FS_fifocount_MASK 0xffffff80 /* bits 0-6 */
436
# define FS_fifocount_SHIFT 0
437
# define FS_bfull_MASK 0xfffffeff /* bit 8 */
438
# define FS_bfull_disable 0x0
439
# define FS_bfull_enable 0x100
440
# define FS_bempty_MASK 0xfffffdff /* bit 9 */
441
# define FS_bempty_disable 0x0
442
# define FS_bempty_enable 0x200
444
#define MGAREG_FOGCOL 0x1cf4
445
#define MGAREG_FOGSTART 0x1cc4
446
#define MGAREG_FOGXINC 0x1cd4
447
#define MGAREG_FOGYINC 0x1ce4
448
#define MGAREG_FXBNDRY 0x1c84
450
# define XA_fxleft_MASK 0xffff0000 /* bits 0-15 */
451
# define XA_fxleft_SHIFT 0
452
# define XA_fxright_MASK 0xffff /* bits 16-31 */
453
# define XA_fxright_SHIFT 16
455
#define MGAREG_FXLEFT 0x1ca8
456
#define MGAREG_FXRIGHT 0x1cac
457
#define MGAREG_ICLEAR 0x1e18
459
# define IC_softrapiclr_MASK 0xfffffffe /* bit 0 */
460
# define IC_softrapiclr_disable 0x0
461
# define IC_softrapiclr_enable 0x1
462
# define IC_pickiclr_MASK 0xfffffffb /* bit 2 */
463
# define IC_pickiclr_disable 0x0
464
# define IC_pickiclr_enable 0x4
465
# define IC_vlineiclr_MASK 0xffffffdf /* bit 5 */
466
# define IC_vlineiclr_disable 0x0
467
# define IC_vlineiclr_enable 0x20
468
# define IC_wiclr_MASK 0xffffff7f /* bit 7 */
469
# define IC_wiclr_disable 0x0
470
# define IC_wiclr_enable 0x80
471
# define IC_wciclr_MASK 0xfffffeff /* bit 8 */
472
# define IC_wciclr_disable 0x0
473
# define IC_wciclr_enable 0x100
475
#define MGAREG_IEN 0x1e1c
477
# define IE_softrapien_MASK 0xfffffffe /* bit 0 */
478
# define IE_softrapien_disable 0x0
479
# define IE_softrapien_enable 0x1
480
# define IE_pickien_MASK 0xfffffffb /* bit 2 */
481
# define IE_pickien_disable 0x0
482
# define IE_pickien_enable 0x4
483
# define IE_vlineien_MASK 0xffffffdf /* bit 5 */
484
# define IE_vlineien_disable 0x0
485
# define IE_vlineien_enable 0x20
486
# define IE_extien_MASK 0xffffffbf /* bit 6 */
487
# define IE_extien_disable 0x0
488
# define IE_extien_enable 0x40
489
# define IE_wien_MASK 0xffffff7f /* bit 7 */
490
# define IE_wien_disable 0x0
491
# define IE_wien_enable 0x80
492
# define IE_wcien_MASK 0xfffffeff /* bit 8 */
493
# define IE_wcien_disable 0x0
494
# define IE_wcien_enable 0x100
496
#define MGAREG_LEN 0x1c5c
497
#define MGAREG_MACCESS 0x1c04
499
# define MA_pwidth_MASK 0xfffffffc /* bits 0-1 */
500
# define MA_pwidth_8 0x0 /* val 0, shift 0 */
501
# define MA_pwidth_16 0x1 /* val 1, shift 0 */
502
# define MA_pwidth_32 0x2 /* val 2, shift 0 */
503
# define MA_pwidth_24 0x3 /* val 3, shift 0 */
504
# define MA_zwidth_MASK 0xffffffe7 /* bits 3-4 */
505
# define MA_zwidth_16 0x0 /* val 0, shift 3 */
506
# define MA_zwidth_32 0x8 /* val 1, shift 3 */
507
# define MA_zwidth_15 0x10 /* val 2, shift 3 */
508
# define MA_zwidth_24 0x18 /* val 3, shift 3 */
509
# define MA_memreset_MASK 0xffff7fff /* bit 15 */
510
# define MA_memreset_disable 0x0
511
# define MA_memreset_enable 0x8000
512
# define MA_fogen_MASK 0xfbffffff /* bit 26 */
513
# define MA_fogen_disable 0x0
514
# define MA_fogen_enable 0x4000000
515
# define MA_tlutload_MASK 0xdfffffff /* bit 29 */
516
# define MA_tlutload_disable 0x0
517
# define MA_tlutload_enable 0x20000000
518
# define MA_nodither_MASK 0xbfffffff /* bit 30 */
519
# define MA_nodither_disable 0x0
520
# define MA_nodither_enable 0x40000000
521
# define MA_dit555_MASK 0x7fffffff /* bit 31 */
522
# define MA_dit555_disable 0x0
523
# define MA_dit555_enable 0x80000000
525
#define MGAREG_MCTLWTST 0x1c08
527
# define MCWS_casltncy_MASK 0xfffffff8 /* bits 0-2 */
528
# define MCWS_casltncy_SHIFT 0
529
# define MCWS_rrddelay_MASK 0xffffffcf /* bits 4-5 */
530
# define MCWS_rcddelay_MASK 0xfffffe7f /* bits 7-8 */
531
# define MCWS_rasmin_MASK 0xffffe3ff /* bits 10-12 */
532
# define MCWS_rasmin_SHIFT 10
533
# define MCWS_rpdelay_MASK 0xffff3fff /* bits 14-15 */
534
# define MCWS_wrdelay_MASK 0xfff3ffff /* bits 18-19 */
535
# define MCWS_rddelay_MASK 0xffdfffff /* bit 21 */
536
# define MCWS_rddelay_disable 0x0
537
# define MCWS_rddelay_enable 0x200000
538
# define MCWS_smrdelay_MASK 0xfe7fffff /* bits 23-24 */
539
# define MCWS_bwcdelay_MASK 0xf3ffffff /* bits 26-27 */
540
# define MCWS_bpldelay_MASK 0x1fffffff /* bits 29-31 */
541
# define MCWS_bpldelay_SHIFT 29
543
#define MGAREG_MEMRDBK 0x1e44
545
# define MRB_mclkbrd0_MASK 0xfffffff0 /* bits 0-3 */
546
# define MRB_mclkbrd0_SHIFT 0
547
# define MRB_mclkbrd1_MASK 0xfffffe1f /* bits 5-8 */
548
# define MRB_mclkbrd1_SHIFT 5
549
# define MRB_strmfctl_MASK 0xff3fffff /* bits 22-23 */
550
# define MRB_mrsopcod_MASK 0xe1ffffff /* bits 25-28 */
551
# define MRB_mrsopcod_SHIFT 25
553
#define MGAREG_OPMODE 0x1e54
555
# define OM_dmamod_MASK 0xfffffff3 /* bits 2-3 */
556
# define OM_dmamod_general 0x0 /* val 0, shift 2 */
557
# define OM_dmamod_blit 0x4 /* val 1, shift 2 */
558
# define OM_dmamod_vector 0x8 /* val 2, shift 2 */
559
# define OM_dmamod_vertex 0xc /* val 3, shift 2 */
560
# define OM_dmadatasiz_MASK 0xfffffcff /* bits 8-9 */
561
# define OM_dmadatasiz_8 0x0 /* val 0, shift 8 */
562
# define OM_dmadatasiz_16 0x100 /* val 1, shift 8 */
563
# define OM_dmadatasiz_32 0x200 /* val 2, shift 8 */
564
# define OM_dirdatasiz_MASK 0xfffcffff /* bits 16-17 */
565
# define OM_dirdatasiz_8 0x0 /* val 0, shift 16 */
566
# define OM_dirdatasiz_16 0x10000 /* val 1, shift 16 */
567
# define OM_dirdatasiz_32 0x20000 /* val 2, shift 16 */
569
#define MGAREG_PAT0 0x1c10
570
#define MGAREG_PAT1 0x1c14
571
#define MGAREG_PITCH 0x1c8c
573
# define P_iy_MASK 0xffffe000 /* bits 0-12 */
574
# define P_iy_SHIFT 0
575
# define P_ylin_MASK 0xffff7fff /* bit 15 */
576
# define P_ylin_disable 0x0
577
# define P_ylin_enable 0x8000
579
#define MGAREG_PLNWT 0x1c1c
580
#define MGAREG_PRIMADDRESS 0x1e58
582
# define PDCA_primod_MASK 0xfffffffc /* bits 0-1 */
583
# define PDCA_primod_general 0x0 /* val 0, shift 0 */
584
# define PDCA_primod_blit 0x1 /* val 1, shift 0 */
585
# define PDCA_primod_vector 0x2 /* val 2, shift 0 */
586
# define PDCA_primod_vertex 0x3 /* val 3, shift 0 */
587
# define PDCA_primaddress_MASK 0x3 /* bits 2-31 */
588
# define PDCA_primaddress_SHIFT 2
590
#define MGAREG_PRIMEND 0x1e5c
592
# define PDEA_primnostart_MASK 0xfffffffe /* bit 0 */
593
# define PDEA_primnostart_disable 0x0
594
# define PDEA_primnostart_enable 0x1
595
# define PDEA_pagpxfer_MASK 0xfffffffd /* bit 1 */
596
# define PDEA_pagpxfer_disable 0x0
597
# define PDEA_pagpxfer_enable 0x2
598
# define PDEA_primend_MASK 0x3 /* bits 2-31 */
599
# define PDEA_primend_SHIFT 2
601
#define MGAREG_PRIMPTR 0x1e50
603
# define PLS_primptren0_MASK 0xfffffffe /* bit 0 */
604
# define PLS_primptren0_disable 0x0
605
# define PLS_primptren0_enable 0x1
606
# define PLS_primptren1_MASK 0xfffffffd /* bit 1 */
607
# define PLS_primptren1_disable 0x0
608
# define PLS_primptren1_enable 0x2
609
# define PLS_primptr_MASK 0x7 /* bits 3-31 */
610
# define PLS_primptr_SHIFT 3
612
#define MGAREG_RST 0x1e40
614
# define R_softreset_MASK 0xfffffffe /* bit 0 */
615
# define R_softreset_disable 0x0
616
# define R_softreset_enable 0x1
617
# define R_softextrst_MASK 0xfffffffd /* bit 1 */
618
# define R_softextrst_disable 0x0
619
# define R_softextrst_enable 0x2
621
#define MGAREG_SECADDRESS 0x2c40
623
# define SDCA_secmod_MASK 0xfffffffc /* bits 0-1 */
624
# define SDCA_secmod_general 0x0 /* val 0, shift 0 */
625
# define SDCA_secmod_blit 0x1 /* val 1, shift 0 */
626
# define SDCA_secmod_vector 0x2 /* val 2, shift 0 */
627
# define SDCA_secmod_vertex 0x3 /* val 3, shift 0 */
628
# define SDCA_secaddress_MASK 0x3 /* bits 2-31 */
629
# define SDCA_secaddress_SHIFT 2
631
#define MGAREG_SECEND 0x2c44
633
# define SDEA_sagpxfer_MASK 0xfffffffd /* bit 1 */
634
# define SDEA_sagpxfer_disable 0x0
635
# define SDEA_sagpxfer_enable 0x2
636
# define SDEA_secend_MASK 0x3 /* bits 2-31 */
637
# define SDEA_secend_SHIFT 2
639
#define MGAREG_SETUPADDRESS 0x2cd0
641
# define SETADD_mode_MASK 0xfffffffc /* bits 0-1 */
642
# define SETADD_mode_vertlist 0x0 /* val 0, shift 0 */
643
# define SETADD_address_MASK 0x3 /* bits 2-31 */
644
# define SETADD_address_SHIFT 2
646
#define MGAREG_SETUPEND 0x2cd4
648
# define SETEND_agpxfer_MASK 0xfffffffd /* bit 1 */
649
# define SETEND_agpxfer_disable 0x0
650
# define SETEND_agpxfer_enable 0x2
651
# define SETEND_address_MASK 0x3 /* bits 2-31 */
652
# define SETEND_address_SHIFT 2
654
#define MGAREG_SGN 0x1c58
656
# define S_sdydxl_MASK 0xfffffffe /* bit 0 */
657
# define S_sdydxl_y 0x0
658
# define S_sdydxl_x 0x1
659
# define S_scanleft_MASK 0xfffffffe /* bit 0 */
660
# define S_scanleft_disable 0x0
661
# define S_scanleft_enable 0x1
662
# define S_sdxl_MASK 0xfffffffd /* bit 1 */
663
# define S_sdxl_pos 0x0
664
# define S_sdxl_neg 0x2
665
# define S_sdy_MASK 0xfffffffb /* bit 2 */
666
# define S_sdy_pos 0x0
667
# define S_sdy_neg 0x4
668
# define S_sdxr_MASK 0xffffffdf /* bit 5 */
669
# define S_sdxr_pos 0x0
670
# define S_sdxr_neg 0x20
671
# define S_brkleft_MASK 0xfffffeff /* bit 8 */
672
# define S_brkleft_disable 0x0
673
# define S_brkleft_enable 0x100
674
# define S_errorinit_MASK 0x7fffffff /* bit 31 */
675
# define S_errorinit_disable 0x0
676
# define S_errorinit_enable 0x80000000
678
#define MGAREG_SHIFT 0x1c50
680
# define FSC_x_off_MASK 0xfffffff0 /* bits 0-3 */
681
# define FSC_x_off_SHIFT 0
682
# define FSC_funcnt_MASK 0xffffff80 /* bits 0-6 */
683
# define FSC_funcnt_SHIFT 0
684
# define FSC_y_off_MASK 0xffffff8f /* bits 4-6 */
685
# define FSC_y_off_SHIFT 4
686
# define FSC_funoff_MASK 0xffc0ffff /* bits 16-21 */
687
# define FSC_funoff_SHIFT 16
688
# define FSC_stylelen_MASK 0xffc0ffff /* bits 16-21 */
689
# define FSC_stylelen_SHIFT 16
691
#define MGAREG_SOFTRAP 0x2c48
693
# define STH_softraphand_MASK 0x3 /* bits 2-31 */
694
# define STH_softraphand_SHIFT 2
696
#define MGAREG_SPECBSTART 0x2c98
697
#define MGAREG_SPECBXINC 0x2c9c
698
#define MGAREG_SPECBYINC 0x2ca0
699
#define MGAREG_SPECGSTART 0x2c8c
700
#define MGAREG_SPECGXINC 0x2c90
701
#define MGAREG_SPECGYINC 0x2c94
702
#define MGAREG_SPECRSTART 0x2c80
703
#define MGAREG_SPECRXINC 0x2c84
704
#define MGAREG_SPECRYINC 0x2c88
705
#define MGAREG_SRC0 0x1c30
706
#define MGAREG_SRC1 0x1c34
707
#define MGAREG_SRC2 0x1c38
708
#define MGAREG_SRC3 0x1c3c
709
#define MGAREG_SRCORG 0x2cb4
711
# define SO_srcmap_MASK 0xfffffffe /* bit 0 */
712
# define SO_srcmap_fb 0x0
713
# define SO_srcmap_sys 0x1
714
# define SO_srcacc_MASK 0xfffffffd /* bit 1 */
715
# define SO_srcacc_pci 0x0
716
# define SO_srcacc_agp 0x2
717
# define SO_srcorg_MASK 0x7 /* bits 3-31 */
718
# define SO_srcorg_SHIFT 3
720
#define MGAREG_STATUS 0x1e14
722
# define STAT_softrapen_MASK 0xfffffffe /* bit 0 */
723
# define STAT_softrapen_disable 0x0
724
# define STAT_softrapen_enable 0x1
725
# define STAT_pickpen_MASK 0xfffffffb /* bit 2 */
726
# define STAT_pickpen_disable 0x0
727
# define STAT_pickpen_enable 0x4
728
# define STAT_vsyncsts_MASK 0xfffffff7 /* bit 3 */
729
# define STAT_vsyncsts_disable 0x0
730
# define STAT_vsyncsts_enable 0x8
731
# define STAT_vsyncpen_MASK 0xffffffef /* bit 4 */
732
# define STAT_vsyncpen_disable 0x0
733
# define STAT_vsyncpen_enable 0x10
734
# define STAT_vlinepen_MASK 0xffffffdf /* bit 5 */
735
# define STAT_vlinepen_disable 0x0
736
# define STAT_vlinepen_enable 0x20
737
# define STAT_extpen_MASK 0xffffffbf /* bit 6 */
738
# define STAT_extpen_disable 0x0
739
# define STAT_extpen_enable 0x40
740
# define STAT_wpen_MASK 0xffffff7f /* bit 7 */
741
# define STAT_wpen_disable 0x0
742
# define STAT_wpen_enable 0x80
743
# define STAT_wcpen_MASK 0xfffffeff /* bit 8 */
744
# define STAT_wcpen_disable 0x0
745
# define STAT_wcpen_enable 0x100
746
# define STAT_dwgengsts_MASK 0xfffeffff /* bit 16 */
747
# define STAT_dwgengsts_disable 0x0
748
# define STAT_dwgengsts_enable 0x10000
749
# define STAT_endprdmasts_MASK 0xfffdffff /* bit 17 */
750
# define STAT_endprdmasts_disable 0x0
751
# define STAT_endprdmasts_enable 0x20000
752
# define STAT_wbusy_MASK 0xfffbffff /* bit 18 */
753
# define STAT_wbusy_disable 0x0
754
# define STAT_wbusy_enable 0x40000
755
# define STAT_swflag_MASK 0xfffffff /* bits 28-31 */
756
# define STAT_swflag_SHIFT 28
758
#define MGAREG_STENCIL 0x2cc8
760
# define S_sref_MASK 0xffffff00 /* bits 0-7 */
761
# define S_sref_SHIFT 0
762
# define S_smsk_MASK 0xffff00ff /* bits 8-15 */
763
# define S_smsk_SHIFT 8
764
# define S_swtmsk_MASK 0xff00ffff /* bits 16-23 */
765
# define S_swtmsk_SHIFT 16
767
#define MGAREG_STENCILCTL 0x2ccc
769
# define SC_smode_MASK 0xfffffff8 /* bits 0-2 */
770
# define SC_smode_salways 0x0 /* val 0, shift 0 */
771
# define SC_smode_snever 0x1 /* val 1, shift 0 */
772
# define SC_smode_se 0x2 /* val 2, shift 0 */
773
# define SC_smode_sne 0x3 /* val 3, shift 0 */
774
# define SC_smode_slt 0x4 /* val 4, shift 0 */
775
# define SC_smode_slte 0x5 /* val 5, shift 0 */
776
# define SC_smode_sgt 0x6 /* val 6, shift 0 */
777
# define SC_smode_sgte 0x7 /* val 7, shift 0 */
778
# define SC_sfailop_MASK 0xffffffc7 /* bits 3-5 */
779
# define SC_sfailop_keep 0x0 /* val 0, shift 3 */
780
# define SC_sfailop_zero 0x8 /* val 1, shift 3 */
781
# define SC_sfailop_replace 0x10 /* val 2, shift 3 */
782
# define SC_sfailop_incrsat 0x18 /* val 3, shift 3 */
783
# define SC_sfailop_decrsat 0x20 /* val 4, shift 3 */
784
# define SC_sfailop_invert 0x28 /* val 5, shift 3 */
785
# define SC_sfailop_incr 0x30 /* val 6, shift 3 */
786
# define SC_sfailop_decr 0x38 /* val 7, shift 3 */
787
# define SC_szfailop_MASK 0xfffffe3f /* bits 6-8 */
788
# define SC_szfailop_keep 0x0 /* val 0, shift 6 */
789
# define SC_szfailop_zero 0x40 /* val 1, shift 6 */
790
# define SC_szfailop_replace 0x80 /* val 2, shift 6 */
791
# define SC_szfailop_incrsat 0xc0 /* val 3, shift 6 */
792
# define SC_szfailop_decrsat 0x100 /* val 4, shift 6 */
793
# define SC_szfailop_invert 0x140 /* val 5, shift 6 */
794
# define SC_szfailop_incr 0x180 /* val 6, shift 6 */
795
# define SC_szfailop_decr 0x1c0 /* val 7, shift 6 */
796
# define SC_szpassop_MASK 0xfffff1ff /* bits 9-11 */
797
# define SC_szpassop_keep 0x0 /* val 0, shift 9 */
798
# define SC_szpassop_zero 0x200 /* val 1, shift 9 */
799
# define SC_szpassop_replace 0x400 /* val 2, shift 9 */
800
# define SC_szpassop_incrsat 0x600 /* val 3, shift 9 */
801
# define SC_szpassop_decrsat 0x800 /* val 4, shift 9 */
802
# define SC_szpassop_invert 0xa00 /* val 5, shift 9 */
803
# define SC_szpassop_incr 0xc00 /* val 6, shift 9 */
804
# define SC_szpassop_decr 0xe00 /* val 7, shift 9 */
806
#define MGAREG_TDUALSTAGE0 0x2cf8
808
# define TD0_color_arg2_MASK 0xfffffffc /* bits 0-1 */
809
# define TD0_color_arg2_diffuse 0x0 /* val 0, shift 0 */
810
# define TD0_color_arg2_specular 0x1 /* val 1, shift 0 */
811
# define TD0_color_arg2_fcol 0x2 /* val 2, shift 0 */
812
# define TD0_color_arg2_prevstage 0x3 /* val 3, shift 0 */
813
# define TD0_color_alpha_MASK 0xffffffe3 /* bits 2-4 */
814
# define TD0_color_alpha_diffuse 0x0 /* val 0, shift 2 */
815
# define TD0_color_alpha_fcol 0x4 /* val 1, shift 2 */
816
# define TD0_color_alpha_currtex 0x8 /* val 2, shift 2 */
817
# define TD0_color_alpha_prevtex 0xc /* val 3, shift 2 */
818
# define TD0_color_alpha_prevstage 0x10 /* val 4, shift 2 */
819
# define TD0_color_arg1_replicatealpha_MASK 0xffffffdf /* bit 5 */
820
# define TD0_color_arg1_replicatealpha_disable 0x0
821
# define TD0_color_arg1_replicatealpha_enable 0x20
822
# define TD0_color_arg1_inv_MASK 0xffffffbf /* bit 6 */
823
# define TD0_color_arg1_inv_disable 0x0
824
# define TD0_color_arg1_inv_enable 0x40
825
# define TD0_color_arg2_replicatealpha_MASK 0xffffff7f /* bit 7 */
826
# define TD0_color_arg2_replicatealpha_disable 0x0
827
# define TD0_color_arg2_replicatealpha_enable 0x80
828
# define TD0_color_arg2_inv_MASK 0xfffffeff /* bit 8 */
829
# define TD0_color_arg2_inv_disable 0x0
830
# define TD0_color_arg2_inv_enable 0x100
831
# define TD0_color_alpha1inv_MASK 0xfffffdff /* bit 9 */
832
# define TD0_color_alpha1inv_disable 0x0
833
# define TD0_color_alpha1inv_enable 0x200
834
# define TD0_color_alpha2inv_MASK 0xfffffbff /* bit 10 */
835
# define TD0_color_alpha2inv_disable 0x0
836
# define TD0_color_alpha2inv_enable 0x400
837
# define TD0_color_arg1mul_MASK 0xfffff7ff /* bit 11 */
838
# define TD0_color_arg1mul_disable 0x0 /* val 0, shift 11 */
839
# define TD0_color_arg1mul_alpha1 0x800 /* val 1, shift 11 */
840
# define TD0_color_arg2mul_MASK 0xffffefff /* bit 12 */
841
# define TD0_color_arg2mul_disable 0x0 /* val 0, shift 12 */
842
# define TD0_color_arg2mul_alpha2 0x1000 /* val 1, shift 12 */
843
# define TD0_color_arg1add_MASK 0xffffdfff /* bit 13 */
844
# define TD0_color_arg1add_disable 0x0 /* val 0, shift 13 */
845
# define TD0_color_arg1add_mulout 0x2000 /* val 1, shift 13 */
846
# define TD0_color_arg2add_MASK 0xffffbfff /* bit 14 */
847
# define TD0_color_arg2add_disable 0x0 /* val 0, shift 14 */
848
# define TD0_color_arg2add_mulout 0x4000 /* val 1, shift 14 */
849
# define TD0_color_modbright_MASK 0xfffe7fff /* bits 15-16 */
850
# define TD0_color_modbright_disable 0x0 /* val 0, shift 15 */
851
# define TD0_color_modbright_2x 0x8000 /* val 1, shift 15 */
852
# define TD0_color_modbright_4x 0x10000 /* val 2, shift 15 */
853
# define TD0_color_add_MASK 0xfffdffff /* bit 17 */
854
# define TD0_color_add_sub 0x0 /* val 0, shift 17 */
855
# define TD0_color_add_add 0x20000 /* val 1, shift 17 */
856
# define TD0_color_add2x_MASK 0xfffbffff /* bit 18 */
857
# define TD0_color_add2x_disable 0x0
858
# define TD0_color_add2x_enable 0x40000
859
# define TD0_color_addbias_MASK 0xfff7ffff /* bit 19 */
860
# define TD0_color_addbias_disable 0x0
861
# define TD0_color_addbias_enable 0x80000
862
# define TD0_color_blend_MASK 0xffefffff /* bit 20 */
863
# define TD0_color_blend_disable 0x0
864
# define TD0_color_blend_enable 0x100000
865
# define TD0_color_sel_MASK 0xff9fffff /* bits 21-22 */
866
# define TD0_color_sel_arg1 0x0 /* val 0, shift 21 */
867
# define TD0_color_sel_arg2 0x200000 /* val 1, shift 21 */
868
# define TD0_color_sel_add 0x400000 /* val 2, shift 21 */
869
# define TD0_color_sel_mul 0x600000 /* val 3, shift 21 */
870
# define TD0_alpha_arg1_inv_MASK 0xff7fffff /* bit 23 */
871
# define TD0_alpha_arg1_inv_disable 0x0
872
# define TD0_alpha_arg1_inv_enable 0x800000
873
# define TD0_alpha_arg2_MASK 0xfcffffff /* bits 24-25 */
874
# define TD0_alpha_arg2_diffuse 0x0 /* val 0, shift 24 */
875
# define TD0_alpha_arg2_fcol 0x1000000 /* val 1, shift 24 */
876
# define TD0_alpha_arg2_prevtex 0x2000000 /* val 2, shift 24 */
877
# define TD0_alpha_arg2_prevstage 0x3000000 /* val 3, shift 24 */
878
# define TD0_alpha_arg2_inv_MASK 0xfbffffff /* bit 26 */
879
# define TD0_alpha_arg2_inv_disable 0x0
880
# define TD0_alpha_arg2_inv_enable 0x4000000
881
# define TD0_alpha_add_MASK 0xf7ffffff /* bit 27 */
882
# define TD0_alpha_add_disable 0x0
883
# define TD0_alpha_add_enable 0x8000000
884
# define TD0_alpha_addbias_MASK 0xefffffff /* bit 28 */
885
# define TD0_alpha_addbias_disable 0x0
886
# define TD0_alpha_addbias_enable 0x10000000
887
# define TD0_alpha_add2x_MASK 0xdfffffff /* bit 29 */
888
# define TD0_alpha_add2x_disable 0x0
889
# define TD0_alpha_add2x_enable 0x20000000
890
# define TD0_alpha_modbright_MASK 0xcfffffff /* bits 28-29 */
891
# define TD0_alpha_modbright_disable 0x0 /* val 0, shift 28 */
892
# define TD0_alpha_modbright_2x 0x10000000 /* val 1, shift 28 */
893
# define TD0_alpha_modbright_4x 0x20000000 /* val 2, shift 28 */
894
# define TD0_alpha_sel_MASK 0x3fffffff /* bits 30-31 */
895
# define TD0_alpha_sel_arg1 0x0 /* val 0, shift 30 */
896
# define TD0_alpha_sel_arg2 0x40000000 /* val 1, shift 30 */
897
# define TD0_alpha_sel_add 0x80000000 /* val 2, shift 30 */
898
# define TD0_alpha_sel_mul 0xc0000000 /* val 3, shift 30 */
900
#define MGAREG_TDUALSTAGE1 0x2cfc
902
# define TD1_color_arg2_MASK 0xfffffffc /* bits 0-1 */
903
# define TD1_color_arg2_diffuse 0x0 /* val 0, shift 0 */
904
# define TD1_color_arg2_specular 0x1 /* val 1, shift 0 */
905
# define TD1_color_arg2_fcol 0x2 /* val 2, shift 0 */
906
# define TD1_color_arg2_prevstage 0x3 /* val 3, shift 0 */
907
# define TD1_color_alpha_MASK 0xffffffe3 /* bits 2-4 */
908
# define TD1_color_alpha_diffuse 0x0 /* val 0, shift 2 */
909
# define TD1_color_alpha_fcol 0x4 /* val 1, shift 2 */
910
# define TD1_color_alpha_tex0 0x8 /* val 2, shift 2 */
911
# define TD1_color_alpha_prevtex 0xc /* val 3, shift 2 */
912
# define TD1_color_alpha_prevstage 0x10 /* val 4, shift 2 */
913
# define TD1_color_arg1_replicatealpha_MASK 0xffffffdf /* bit 5 */
914
# define TD1_color_arg1_replicatealpha_disable 0x0
915
# define TD1_color_arg1_replicatealpha_enable 0x20
916
# define TD1_color_arg1_inv_MASK 0xffffffbf /* bit 6 */
917
# define TD1_color_arg1_inv_disable 0x0
918
# define TD1_color_arg1_inv_enable 0x40
919
# define TD1_color_arg2_replicatealpha_MASK 0xffffff7f /* bit 7 */
920
# define TD1_color_arg2_replicatealpha_disable 0x0
921
# define TD1_color_arg2_replicatealpha_enable 0x80
922
# define TD1_color_arg2_inv_MASK 0xfffffeff /* bit 8 */
923
# define TD1_color_arg2_inv_disable 0x0
924
# define TD1_color_arg2_inv_enable 0x100
925
# define TD1_color_alpha1inv_MASK 0xfffffdff /* bit 9 */
926
# define TD1_color_alpha1inv_disable 0x0
927
# define TD1_color_alpha1inv_enable 0x200
928
# define TD1_color_alpha2inv_MASK 0xfffffbff /* bit 10 */
929
# define TD1_color_alpha2inv_disable 0x0
930
# define TD1_color_alpha2inv_enable 0x400
931
# define TD1_color_arg1mul_MASK 0xfffff7ff /* bit 11 */
932
# define TD1_color_arg1mul_disable 0x0 /* val 0, shift 11 */
933
# define TD1_color_arg1mul_alpha1 0x800 /* val 1, shift 11 */
934
# define TD1_color_arg2mul_MASK 0xffffefff /* bit 12 */
935
# define TD1_color_arg2mul_disable 0x0 /* val 0, shift 12 */
936
# define TD1_color_arg2mul_alpha2 0x1000 /* val 1, shift 12 */
937
# define TD1_color_arg1add_MASK 0xffffdfff /* bit 13 */
938
# define TD1_color_arg1add_disable 0x0 /* val 0, shift 13 */
939
# define TD1_color_arg1add_mulout 0x2000 /* val 1, shift 13 */
940
# define TD1_color_arg2add_MASK 0xffffbfff /* bit 14 */
941
# define TD1_color_arg2add_disable 0x0 /* val 0, shift 14 */
942
# define TD1_color_arg2add_mulout 0x4000 /* val 1, shift 14 */
943
# define TD1_color_modbright_MASK 0xfffe7fff /* bits 15-16 */
944
# define TD1_color_modbright_disable 0x0 /* val 0, shift 15 */
945
# define TD1_color_modbright_2x 0x8000 /* val 1, shift 15 */
946
# define TD1_color_modbright_4x 0x10000 /* val 2, shift 15 */
947
# define TD1_color_add_MASK 0xfffdffff /* bit 17 */
948
# define TD1_color_add_sub 0x0 /* val 0, shift 17 */
949
# define TD1_color_add_add 0x20000 /* val 1, shift 17 */
950
# define TD1_color_add2x_MASK 0xfffbffff /* bit 18 */
951
# define TD1_color_add2x_disable 0x0
952
# define TD1_color_add2x_enable 0x40000
953
# define TD1_color_addbias_MASK 0xfff7ffff /* bit 19 */
954
# define TD1_color_addbias_disable 0x0
955
# define TD1_color_addbias_enable 0x80000
956
# define TD1_color_blend_MASK 0xffefffff /* bit 20 */
957
# define TD1_color_blend_disable 0x0
958
# define TD1_color_blend_enable 0x100000
959
# define TD1_color_sel_MASK 0xff9fffff /* bits 21-22 */
960
# define TD1_color_sel_arg1 0x0 /* val 0, shift 21 */
961
# define TD1_color_sel_arg2 0x200000 /* val 1, shift 21 */
962
# define TD1_color_sel_add 0x400000 /* val 2, shift 21 */
963
# define TD1_color_sel_mul 0x600000 /* val 3, shift 21 */
964
# define TD1_alpha_arg1_inv_MASK 0xff7fffff /* bit 23 */
965
# define TD1_alpha_arg1_inv_disable 0x0
966
# define TD1_alpha_arg1_inv_enable 0x800000
967
# define TD1_alpha_arg2_MASK 0xfcffffff /* bits 24-25 */
968
# define TD1_alpha_arg2_diffuse 0x0 /* val 0, shift 24 */
969
# define TD1_alpha_arg2_fcol 0x1000000 /* val 1, shift 24 */
970
# define TD1_alpha_arg2_prevtex 0x2000000 /* val 2, shift 24 */
971
# define TD1_alpha_arg2_prevstage 0x3000000 /* val 3, shift 24 */
972
# define TD1_alpha_arg2_inv_MASK 0xfbffffff /* bit 26 */
973
# define TD1_alpha_arg2_inv_disable 0x0
974
# define TD1_alpha_arg2_inv_enable 0x4000000
975
# define TD1_alpha_add_MASK 0xf7ffffff /* bit 27 */
976
# define TD1_alpha_add_disable 0x0
977
# define TD1_alpha_add_enable 0x8000000
978
# define TD1_alpha_addbias_MASK 0xefffffff /* bit 28 */
979
# define TD1_alpha_addbias_disable 0x0
980
# define TD1_alpha_addbias_enable 0x10000000
981
# define TD1_alpha_add2x_MASK 0xdfffffff /* bit 29 */
982
# define TD1_alpha_add2x_disable 0x0
983
# define TD1_alpha_add2x_enable 0x20000000
984
# define TD1_alpha_modbright_MASK 0xcfffffff /* bits 28-29 */
985
# define TD1_alpha_modbright_disable 0x0 /* val 0, shift 28 */
986
# define TD1_alpha_modbright_2x 0x10000000 /* val 1, shift 28 */
987
# define TD1_alpha_modbright_4x 0x20000000 /* val 2, shift 28 */
988
# define TD1_alpha_sel_MASK 0x3fffffff /* bits 30-31 */
989
# define TD1_alpha_sel_arg1 0x0 /* val 0, shift 30 */
990
# define TD1_alpha_sel_arg2 0x40000000 /* val 1, shift 30 */
991
# define TD1_alpha_sel_add 0x80000000 /* val 2, shift 30 */
992
# define TD1_alpha_sel_mul 0xc0000000 /* val 3, shift 30 */
994
#define MGAREG_TEST0 0x1e48
996
# define TST_ramtsten_MASK 0xfffffffe /* bit 0 */
997
# define TST_ramtsten_disable 0x0
998
# define TST_ramtsten_enable 0x1
999
# define TST_ramtstdone_MASK 0xfffffffd /* bit 1 */
1000
# define TST_ramtstdone_disable 0x0
1001
# define TST_ramtstdone_enable 0x2
1002
# define TST_wramtstpass_MASK 0xfffffffb /* bit 2 */
1003
# define TST_wramtstpass_disable 0x0
1004
# define TST_wramtstpass_enable 0x4
1005
# define TST_tcachetstpass_MASK 0xfffffff7 /* bit 3 */
1006
# define TST_tcachetstpass_disable 0x0
1007
# define TST_tcachetstpass_enable 0x8
1008
# define TST_tluttstpass_MASK 0xffffffef /* bit 4 */
1009
# define TST_tluttstpass_disable 0x0
1010
# define TST_tluttstpass_enable 0x10
1011
# define TST_luttstpass_MASK 0xffffffdf /* bit 5 */
1012
# define TST_luttstpass_disable 0x0
1013
# define TST_luttstpass_enable 0x20
1014
# define TST_besramtstpass_MASK 0xffffffbf /* bit 6 */
1015
# define TST_besramtstpass_disable 0x0
1016
# define TST_besramtstpass_enable 0x40
1017
# define TST_ringen_MASK 0xfffffeff /* bit 8 */
1018
# define TST_ringen_disable 0x0
1019
# define TST_ringen_enable 0x100
1020
# define TST_apllbyp_MASK 0xfffffdff /* bit 9 */
1021
# define TST_apllbyp_disable 0x0
1022
# define TST_apllbyp_enable 0x200
1023
# define TST_hiten_MASK 0xfffffbff /* bit 10 */
1024
# define TST_hiten_disable 0x0
1025
# define TST_hiten_enable 0x400
1026
# define TST_tmode_MASK 0xffffc7ff /* bits 11-13 */
1027
# define TST_tmode_SHIFT 11
1028
# define TST_tclksel_MASK 0xfffe3fff /* bits 14-16 */
1029
# define TST_tclksel_SHIFT 14
1030
# define TST_ringcnten_MASK 0xfffdffff /* bit 17 */
1031
# define TST_ringcnten_disable 0x0
1032
# define TST_ringcnten_enable 0x20000
1033
# define TST_ringcnt_MASK 0xc003ffff /* bits 18-29 */
1034
# define TST_ringcnt_SHIFT 18
1035
# define TST_ringcntclksl_MASK 0xbfffffff /* bit 30 */
1036
# define TST_ringcntclksl_disable 0x0
1037
# define TST_ringcntclksl_enable 0x40000000
1038
# define TST_biosboot_MASK 0x7fffffff /* bit 31 */
1039
# define TST_biosboot_disable 0x0
1040
# define TST_biosboot_enable 0x80000000
1042
#define MGAREG_TEXBORDERCOL 0x2c5c
1043
#define MGAREG_TEXCTL 0x2c30
1045
# define TMC_tformat_MASK 0xfffffff0 /* bits 0-3 */
1046
# define TMC_tformat_tw4 0x0 /* val 0, shift 0 */
1047
# define TMC_tformat_tw8 0x1 /* val 1, shift 0 */
1048
# define TMC_tformat_tw15 0x2 /* val 2, shift 0 */
1049
# define TMC_tformat_tw16 0x3 /* val 3, shift 0 */
1050
# define TMC_tformat_tw12 0x4 /* val 4, shift 0 */
1051
# define TMC_tformat_tw32 0x6 /* val 6, shift 0 */
1052
# define TMC_tformat_tw8a 0x7 /* val 7, shift 0 */
1053
# define TMC_tformat_tw8al 0x8 /* val 8, shift 0 */
1054
# define TMC_tformat_tw422 0xa /* val 10, shift 0 */
1055
# define TMC_tformat_tw422uyvy 0xb /* val 11, shift 0 */
1056
# define TMC_tpitchlin_MASK 0xfffffeff /* bit 8 */
1057
# define TMC_tpitchlin_disable 0x0
1058
# define TMC_tpitchlin_enable 0x100
1059
# define TMC_tpitchext_MASK 0xfff001ff /* bits 9-19 */
1060
# define TMC_tpitchext_SHIFT 9
1061
# define TMC_tpitch_MASK 0xfff8ffff /* bits 16-18 */
1062
# define TMC_tpitch_SHIFT 16
1063
# define TMC_owalpha_MASK 0xffbfffff /* bit 22 */
1064
# define TMC_owalpha_disable 0x0
1065
# define TMC_owalpha_enable 0x400000
1066
# define TMC_azeroextend_MASK 0xff7fffff /* bit 23 */
1067
# define TMC_azeroextend_disable 0x0
1068
# define TMC_azeroextend_enable 0x800000
1069
# define TMC_decalckey_MASK 0xfeffffff /* bit 24 */
1070
# define TMC_decalckey_disable 0x0
1071
# define TMC_decalckey_enable 0x1000000
1072
# define TMC_takey_MASK 0xfdffffff /* bit 25 */
1073
# define TMC_takey_0 0x0
1074
# define TMC_takey_1 0x2000000
1075
# define TMC_tamask_MASK 0xfbffffff /* bit 26 */
1076
# define TMC_tamask_0 0x0
1077
# define TMC_tamask_1 0x4000000
1078
# define TMC_clampv_MASK 0xf7ffffff /* bit 27 */
1079
# define TMC_clampv_disable 0x0
1080
# define TMC_clampv_enable 0x8000000
1081
# define TMC_clampu_MASK 0xefffffff /* bit 28 */
1082
# define TMC_clampu_disable 0x0
1083
# define TMC_clampu_enable 0x10000000
1084
# define TMC_tmodulate_MASK 0xdfffffff /* bit 29 */
1085
# define TMC_tmodulate_disable 0x0
1086
# define TMC_tmodulate_enable 0x20000000
1087
# define TMC_strans_MASK 0xbfffffff /* bit 30 */
1088
# define TMC_strans_disable 0x0
1089
# define TMC_strans_enable 0x40000000
1090
# define TMC_itrans_MASK 0x7fffffff /* bit 31 */
1091
# define TMC_itrans_disable 0x0
1092
# define TMC_itrans_enable 0x80000000
1094
#define MGAREG_TEXCTL2 0x2c3c
1096
# define TMC_decalblend_MASK 0xfffffffe /* bit 0 */
1097
# define TMC_decalblend_disable 0x0
1098
# define TMC_decalblend_enable 0x1
1099
# define TMC_idecal_MASK 0xfffffffd /* bit 1 */
1100
# define TMC_idecal_disable 0x0
1101
# define TMC_idecal_enable 0x2
1102
# define TMC_decaldis_MASK 0xfffffffb /* bit 2 */
1103
# define TMC_decaldis_disable 0x0
1104
# define TMC_decaldis_enable 0x4
1105
# define TMC_ckstransdis_MASK 0xffffffef /* bit 4 */
1106
# define TMC_ckstransdis_disable 0x0
1107
# define TMC_ckstransdis_enable 0x10
1108
# define TMC_borderen_MASK 0xffffffdf /* bit 5 */
1109
# define TMC_borderen_disable 0x0
1110
# define TMC_borderen_enable 0x20
1111
# define TMC_specen_MASK 0xffffffbf /* bit 6 */
1112
# define TMC_specen_disable 0x0
1113
# define TMC_specen_enable 0x40
1114
# define TMC_dualtex_MASK 0xffffff7f /* bit 7 */
1115
# define TMC_dualtex_disable 0x0
1116
# define TMC_dualtex_enable 0x80
1117
# define TMC_tablefog_MASK 0xfffffeff /* bit 8 */
1118
# define TMC_tablefog_disable 0x0
1119
# define TMC_tablefog_enable 0x100
1120
# define TMC_bumpmap_MASK 0xfffffdff /* bit 9 */
1121
# define TMC_bumpmap_disable 0x0
1122
# define TMC_bumpmap_enable 0x200
1123
# define TMC_map1_MASK 0x7fffffff /* bit 31 */
1124
# define TMC_map1_disable 0x0
1125
# define TMC_map1_enable 0x80000000
1127
#define MGAREG_TEXFILTER 0x2c58
1129
# define TF_minfilter_MASK 0xfffffff0 /* bits 0-3 */
1130
# define TF_minfilter_nrst 0x0 /* val 0, shift 0 */
1131
# define TF_minfilter_bilin 0x2 /* val 2, shift 0 */
1132
# define TF_minfilter_cnst 0x3 /* val 3, shift 0 */
1133
# define TF_minfilter_mm1s 0x8 /* val 8, shift 0 */
1134
# define TF_minfilter_mm2s 0x9 /* val 9, shift 0 */
1135
# define TF_minfilter_mm4s 0xa /* val 10, shift 0 */
1136
# define TF_minfilter_mm8s 0xc /* val 12, shift 0 */
1137
# define TF_magfilter_MASK 0xffffff0f /* bits 4-7 */
1138
# define TF_magfilter_nrst 0x0 /* val 0, shift 4 */
1139
# define TF_magfilter_bilin 0x20 /* val 2, shift 4 */
1140
# define TF_magfilter_cnst 0x30 /* val 3, shift 4 */
1141
# define TF_uvoffset_SHIFT 17
1142
# define TF_uvoffset_OGL (0U << TF_uvoffset_SHIFT)
1143
# define TF_uvoffset_D3D (1U << TF_uvoffset_SHIFT)
1144
# define TF_uvoffset_MASK (~(1U << TF_uvoffset_SHIFT))
1145
# define TF_reserved_MASK (~0x1ff00) /* bits 8-16 */
1146
# define TF_mapnbhigh_SHIFT 18
1147
# define TF_mapnbhigh_MASK (~(1U << TF_mapnbhigh_SHIFT))
1148
# define TF_avgstride_MASK 0xfff7ffff /* bit 19 */
1149
# define TF_avgstride_disable 0x0
1150
# define TF_avgstride_enable 0x80000
1151
# define TF_filteralpha_MASK 0xffefffff /* bit 20 */
1152
# define TF_filteralpha_disable 0x0
1153
# define TF_filteralpha_enable 0x100000
1154
# define TF_fthres_MASK 0xe01fffff /* bits 21-28 */
1155
# define TF_fthres_SHIFT 21
1156
# define TF_mapnb_MASK 0x1fffffff /* bits 29-31 */
1157
# define TF_mapnb_SHIFT 29
1159
#define MGAREG_TEXHEIGHT 0x2c2c
1161
# define TH_th_MASK 0xffffffc0 /* bits 0-5 */
1162
# define TH_th_SHIFT 0
1163
# define TH_rfh_MASK 0xffff81ff /* bits 9-14 */
1164
# define TH_rfh_SHIFT 9
1165
# define TH_thmask_MASK 0xe003ffff /* bits 18-28 */
1166
# define TH_thmask_SHIFT 18
1168
#define MGAREG_TEXORG 0x2c24
1170
# define TO_texorgmap_MASK 0xfffffffe /* bit 0 */
1171
# define TO_texorgmap_fb 0x0
1172
# define TO_texorgmap_sys 0x1
1173
# define TO_texorgacc_MASK 0xfffffffd /* bit 1 */
1174
# define TO_texorgacc_pci 0x0
1175
# define TO_texorgacc_agp 0x2
1176
# define TO_texorgoffsetsel 0x4
1177
# define TO_texorg_MASK 0x1f /* bits 5-31 */
1178
# define TO_texorg_SHIFT 5
1180
#define MGAREG_TEXORG1 0x2ca4
1181
#define MGAREG_TEXORG2 0x2ca8
1182
#define MGAREG_TEXORG3 0x2cac
1183
#define MGAREG_TEXORG4 0x2cb0
1184
#define MGAREG_TEXTRANS 0x2c34
1186
# define TT_tckey_MASK 0xffff0000 /* bits 0-15 */
1187
# define TT_tckey_SHIFT 0
1188
# define TT_tkmask_MASK 0xffff /* bits 16-31 */
1189
# define TT_tkmask_SHIFT 16
1191
#define MGAREG_TEXTRANSHIGH 0x2c38
1193
# define TT_tckeyh_MASK 0xffff0000 /* bits 0-15 */
1194
# define TT_tckeyh_SHIFT 0
1195
# define TT_tkmaskh_MASK 0xffff /* bits 16-31 */
1196
# define TT_tkmaskh_SHIFT 16
1198
#define MGAREG_TEXWIDTH 0x2c28
1200
# define TW_tw_MASK 0xffffffc0 /* bits 0-5 */
1201
# define TW_tw_SHIFT 0
1202
# define TW_rfw_MASK 0xffff81ff /* bits 9-14 */
1203
# define TW_rfw_SHIFT 9
1204
# define TW_twmask_MASK 0xe003ffff /* bits 18-28 */
1205
# define TW_twmask_SHIFT 18
1207
#define MGAREG_TMR0 0x2c00
1208
#define MGAREG_TMR1 0x2c04
1209
#define MGAREG_TMR2 0x2c08
1210
#define MGAREG_TMR3 0x2c0c
1211
#define MGAREG_TMR4 0x2c10
1212
#define MGAREG_TMR5 0x2c14
1213
#define MGAREG_TMR6 0x2c18
1214
#define MGAREG_TMR7 0x2c1c
1215
#define MGAREG_TMR8 0x2c20
1216
#define MGAREG_VBIADDR0 0x3e08
1217
#define MGAREG_VBIADDR1 0x3e0c
1218
#define MGAREG_VCOUNT 0x1e20
1219
#define MGAREG_WACCEPTSEQ 0x1dd4
1221
# define WAS_seqdst0_MASK 0xffffffc0 /* bits 0-5 */
1222
# define WAS_seqdst0_SHIFT 0
1223
# define WAS_seqdst1_MASK 0xfffff03f /* bits 6-11 */
1224
# define WAS_seqdst1_SHIFT 6
1225
# define WAS_seqdst2_MASK 0xfffc0fff /* bits 12-17 */
1226
# define WAS_seqdst2_SHIFT 12
1227
# define WAS_seqdst3_MASK 0xff03ffff /* bits 18-23 */
1228
# define WAS_seqdst3_SHIFT 18
1229
# define WAS_seqlen_MASK 0xfcffffff /* bits 24-25 */
1230
# define WAS_wfirsttag_MASK 0xfbffffff /* bit 26 */
1231
# define WAS_wfirsttag_disable 0x0
1232
# define WAS_wfirsttag_enable 0x4000000
1233
# define WAS_wsametag_MASK 0xf7ffffff /* bit 27 */
1234
# define WAS_wsametag_disable 0x0
1235
# define WAS_wsametag_enable 0x8000000
1236
# define WAS_seqoff_MASK 0xefffffff /* bit 28 */
1237
# define WAS_seqoff_disable 0x0
1238
# define WAS_seqoff_enable 0x10000000
1240
#define MGAREG_WCODEADDR 0x1e6c
1242
# define WMA_wcodeaddr_MASK 0xff /* bits 8-31 */
1243
# define WMA_wcodeaddr_SHIFT 8
1245
#define MGAREG_WFLAG 0x1dc4
1247
# define WF_walustsflag_MASK 0xffffff00 /* bits 0-7 */
1248
# define WF_walustsflag_SHIFT 0
1249
# define WF_walucfgflag_MASK 0xffff00ff /* bits 8-15 */
1250
# define WF_walucfgflag_SHIFT 8
1251
# define WF_wprgflag_MASK 0xffff /* bits 16-31 */
1252
# define WF_wprgflag_SHIFT 16
1254
#define MGAREG_WFLAG1 0x1de0
1256
# define WF1_walustsflag1_MASK 0xffffff00 /* bits 0-7 */
1257
# define WF1_walustsflag1_SHIFT 0
1258
# define WF1_walucfgflag1_MASK 0xffff00ff /* bits 8-15 */
1259
# define WF1_walucfgflag1_SHIFT 8
1260
# define WF1_wprgflag1_MASK 0xffff /* bits 16-31 */
1261
# define WF1_wprgflag1_SHIFT 16
1263
#define MGAREG_WFLAGNB 0x1e64
1264
#define MGAREG_WFLAGNB1 0x1e08
1265
#define MGAREG_WGETMSB 0x1dc8
1267
# define WGV_wgetmsbmin_MASK 0xffffffe0 /* bits 0-4 */
1268
# define WGV_wgetmsbmin_SHIFT 0
1269
# define WGV_wgetmsbmax_MASK 0xffffe0ff /* bits 8-12 */
1270
# define WGV_wgetmsbmax_SHIFT 8
1271
# define WGV_wbrklefttop_MASK 0xfffeffff /* bit 16 */
1272
# define WGV_wbrklefttop_disable 0x0
1273
# define WGV_wbrklefttop_enable 0x10000
1274
# define WGV_wfastcrop_MASK 0xfffdffff /* bit 17 */
1275
# define WGV_wfastcrop_disable 0x0
1276
# define WGV_wfastcrop_enable 0x20000
1277
# define WGV_wcentersnap_MASK 0xfffbffff /* bit 18 */
1278
# define WGV_wcentersnap_disable 0x0
1279
# define WGV_wcentersnap_enable 0x40000
1280
# define WGV_wbrkrighttop_MASK 0xfff7ffff /* bit 19 */
1281
# define WGV_wbrkrighttop_disable 0x0
1282
# define WGV_wbrkrighttop_enable 0x80000
1284
#define MGAREG_WIADDR 0x1dc0
1286
# define WIA_wmode_MASK 0xfffffffc /* bits 0-1 */
1287
# define WIA_wmode_suspend 0x0 /* val 0, shift 0 */
1288
# define WIA_wmode_resume 0x1 /* val 1, shift 0 */
1289
# define WIA_wmode_jump 0x2 /* val 2, shift 0 */
1290
# define WIA_wmode_start 0x3 /* val 3, shift 0 */
1291
# define WIA_wagp_MASK 0xfffffffb /* bit 2 */
1292
# define WIA_wagp_pci 0x0
1293
# define WIA_wagp_agp 0x4
1294
# define WIA_wiaddr_MASK 0x7 /* bits 3-31 */
1295
# define WIA_wiaddr_SHIFT 3
1297
#define MGAREG_WIADDR2 0x1dd8
1299
# define WIA2_wmode_MASK 0xfffffffc /* bits 0-1 */
1300
# define WIA2_wmode_suspend 0x0 /* val 0, shift 0 */
1301
# define WIA2_wmode_resume 0x1 /* val 1, shift 0 */
1302
# define WIA2_wmode_jump 0x2 /* val 2, shift 0 */
1303
# define WIA2_wmode_start 0x3 /* val 3, shift 0 */
1304
# define WIA2_wagp_MASK 0xfffffffb /* bit 2 */
1305
# define WIA2_wagp_pci 0x0
1306
# define WIA2_wagp_agp 0x4
1307
# define WIA2_wiaddr_MASK 0x7 /* bits 3-31 */
1308
# define WIA2_wiaddr_SHIFT 3
1310
#define MGAREG_WIADDRNB 0x1e60
1311
#define MGAREG_WIADDRNB1 0x1e04
1312
#define MGAREG_WIADDRNB2 0x1e00
1313
#define MGAREG_WIMEMADDR 0x1e68
1315
# define WIMA_wimemaddr_MASK 0xffffff00 /* bits 0-7 */
1316
# define WIMA_wimemaddr_SHIFT 0
1318
#define MGAREG_WIMEMDATA 0x2000
1319
#define MGAREG_WIMEMDATA1 0x2100
1320
#define MGAREG_WMISC 0x1e70
1322
# define WM_wucodecache_MASK 0xfffffffe /* bit 0 */
1323
# define WM_wucodecache_disable 0x0
1324
# define WM_wucodecache_enable 0x1
1325
# define WM_wmaster_MASK 0xfffffffd /* bit 1 */
1326
# define WM_wmaster_disable 0x0
1327
# define WM_wmaster_enable 0x2
1328
# define WM_wcacheflush_MASK 0xfffffff7 /* bit 3 */
1329
# define WM_wcacheflush_disable 0x0
1330
# define WM_wcacheflush_enable 0x8
1332
#define MGAREG_WR 0x2d00
1333
#define MGAREG_WVRTXSZ 0x1dcc
1335
# define WVS_wvrtxsz_MASK 0xffffffc0 /* bits 0-5 */
1336
# define WVS_wvrtxsz_SHIFT 0
1337
# define WVS_primsz_MASK 0xffffc0ff /* bits 8-13 */
1338
# define WVS_primsz_SHIFT 8
1340
#define MGAREG_XDST 0x1cb0
1341
#define MGAREG_XYEND 0x1c44
1343
# define XYEA_x_end_MASK 0xffff0000 /* bits 0-15 */
1344
# define XYEA_x_end_SHIFT 0
1345
# define XYEA_y_end_MASK 0xffff /* bits 16-31 */
1346
# define XYEA_y_end_SHIFT 16
1348
#define MGAREG_XYSTRT 0x1c40
1350
# define XYSA_x_start_MASK 0xffff0000 /* bits 0-15 */
1351
# define XYSA_x_start_SHIFT 0
1352
# define XYSA_y_start_MASK 0xffff /* bits 16-31 */
1353
# define XYSA_y_start_SHIFT 16
1355
#define MGAREG_YBOT 0x1c9c
1356
#define MGAREG_YDST 0x1c90
1358
# define YA_ydst_MASK 0xff800000 /* bits 0-22 */
1359
# define YA_ydst_SHIFT 0
1360
# define YA_sellin_MASK 0x1fffffff /* bits 29-31 */
1361
# define YA_sellin_SHIFT 29
1363
#define MGAREG_YDSTLEN 0x1c88
1365
# define YDL_length_MASK 0xffff0000 /* bits 0-15 */
1366
# define YDL_length_SHIFT 0
1367
# define YDL_yval_MASK 0xffff /* bits 16-31 */
1368
# define YDL_yval_SHIFT 16
1370
#define MGAREG_YDSTORG 0x1c94
1371
#define MGAREG_YTOP 0x1c98
1372
#define MGAREG_ZORG 0x1c0c
1374
# define ZO_zorgmap_MASK 0xfffffffe /* bit 0 */
1375
# define ZO_zorgmap_fb 0x0
1376
# define ZO_zorgmap_sys 0x1
1377
# define ZO_zorgacc_MASK 0xfffffffd /* bit 1 */
1378
# define ZO_zorgacc_pci 0x0
1379
# define ZO_zorgacc_agp 0x2
1380
# define ZO_zorg_MASK 0x3 /* bits 2-31 */
1381
# define ZO_zorg_SHIFT 2
1386
/**************** (END) AUTOMATICLY GENERATED REGISTER FILE ******************/
1388
/* Copied from mga_drv.h kernel file.
1391
#define MGA_ILOAD_ALIGN 64
1392
#define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
1394
#endif /* _MGAREGS_H_ */
added
removed
src/mesa/drivers/dri/mga/mgaregs.h
