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/* $XConsortium: mgareg.h /main/2 1996/10/25 10:33:21 kaleb $ */
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/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/mga/mga_reg.h,v 1.18 2001/09/26 12:59:18 alanh Exp $ */
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* MGA Millennium (MGA2064W) functions
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* MGA Mystique (MGA1064SG) functions
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* Copyright 1996 The XFree86 Project, Inc.
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* Guy DESBIEF, Aix-en-provence, France
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* g.desbief@aix.pacwan.net
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* MGA1064SG Mystique register file
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#define MGAREG_DWGCTL 0x1c00
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#define MGAREG_MACCESS 0x1c04
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#define MGA_MACCESS_PW16 0x00000001
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#define MGA_MACCESS_PW32 0x00000002
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/* the following is a mystique only register */
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#define MGAREG_MCTLWTST 0x1c08
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#define MGAREG_ZORG 0x1c0c
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#define MGAREG_PAT0 0x1c10
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#define MGAREG_PAT1 0x1c14
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#define MGAREG_PLNWT 0x1c1c
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#define MGAREG_BCOL 0x1c20
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#define MGAREG_FCOL 0x1c24
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#define MGAREG_SRC0 0x1c30
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#define MGAREG_SRC1 0x1c34
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#define MGAREG_SRC2 0x1c38
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#define MGAREG_SRC3 0x1c3c
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#define MGAREG_XYSTRT 0x1c40
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#define MGAREG_XYEND 0x1c44
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#define MGAREG_SHIFT 0x1c50
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/* the following is a mystique only register */
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#define MGAREG_DMAPAD 0x1c54
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#define MGAREG_SGN 0x1c58
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#define MGAREG_LEN 0x1c5c
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#define MGAREG_AR0 0x1c60
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#define MGAREG_AR1 0x1c64
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#define MGAREG_AR2 0x1c68
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#define MGAREG_AR3 0x1c6c
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#define MGAREG_AR4 0x1c70
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#define MGAREG_AR5 0x1c74
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#define MGAREG_AR6 0x1c78
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#define MGAREG_CXBNDRY 0x1c80
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#define MGAREG_FXBNDRY 0x1c84
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#define MGAREG_YDSTLEN 0x1c88
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#define MGAREG_PITCH 0x1c8c
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#define MGAREG_YDST 0x1c90
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#define MGAREG_YDSTORG 0x1c94
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#define MGAREG_YTOP 0x1c98
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#define MGAREG_YBOT 0x1c9c
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#define MGAREG_CXLEFT 0x1ca0
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#define MGAREG_CXRIGHT 0x1ca4
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#define MGAREG_FXLEFT 0x1ca8
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#define MGAREG_FXRIGHT 0x1cac
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#define MGAREG_XDST 0x1cb0
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#define MGAREG_DR0 0x1cc0
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#define MGAREG_DR1 0x1cc4
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#define MGAREG_DR2 0x1cc8
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#define MGAREG_DR3 0x1ccc
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#define MGAREG_DR4 0x1cd0
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#define MGAREG_DR5 0x1cd4
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#define MGAREG_DR6 0x1cd8
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#define MGAREG_DR7 0x1cdc
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#define MGAREG_DR8 0x1ce0
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#define MGAREG_DR9 0x1ce4
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#define MGAREG_DR10 0x1ce8
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#define MGAREG_DR11 0x1cec
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#define MGAREG_DR12 0x1cf0
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#define MGAREG_DR13 0x1cf4
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#define MGAREG_DR14 0x1cf8
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#define MGAREG_DR15 0x1cfc
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#define MGAREG_SRCORG 0x2cb4
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#define MGAREG_DSTORG 0x2cb8
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/* add or or this to one of the previous "power registers" to start
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the drawing engine */
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#define MGAREG_EXEC 0x0100
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#define MGAREG_FIFOSTATUS 0x1e10
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#define MGAREG_Status 0x1e14
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#define MGAREG_ICLEAR 0x1e18
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#define MGAREG_IEN 0x1e1c
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#define MGAREG_VCOUNT 0x1e20
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#define MGAREG_Reset 0x1e40
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#define MGAREG_OPMODE 0x1e54
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#define MGAREG_WIADDR 0x1dc0
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#define MGAREG_WIADDR2 0x1dd8
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#define MGAREG_WGETMSB 0x1dc8
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#define MGAREG_WVRTXSZ 0x1dcc
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#define MGAREG_WACCEPTSEQ 0x1dd4
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#define MGAREG_WMISC 0x1e70
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/* OPMODE register additives */
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#define MGAOPM_DMA_GENERAL (0x00 << 2)
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#define MGAOPM_DMA_BLIT (0x01 << 2)
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#define MGAOPM_DMA_VECTOR (0x10 << 2)
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/* DWGCTL register additives */
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#define MGADWG_LINE_OPEN 0x00
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#define MGADWG_AUTOLINE_OPEN 0x01
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#define MGADWG_LINE_CLOSE 0x02
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#define MGADWG_AUTOLINE_CLOSE 0x03
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#define MGADWG_TRAP 0x04
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#define MGADWG_TEXTURE_TRAP 0x05
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#define MGADWG_BITBLT 0x08
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#define MGADWG_FBITBLT 0x0c
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#define MGADWG_ILOAD 0x09
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#define MGADWG_ILOAD_SCALE 0x0d
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#define MGADWG_ILOAD_FILTER 0x0f
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#define MGADWG_ILOAD_HIQH 0x07
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#define MGADWG_ILOAD_HIQHV 0x0e
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#define MGADWG_IDUMP 0x0a
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/* atype access to WRAM */
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#define MGADWG_RPL ( 0x00 << 4 )
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#define MGADWG_RSTR ( 0x01 << 4 )
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#define MGADWG_ZI ( 0x03 << 4 )
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#define MGADWG_BLK ( 0x04 << 4 )
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#define MGADWG_I ( 0x07 << 4 )
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/* specifies whether bit blits are linear or xy */
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#define MGADWG_LINEAR ( 0x01 << 7 )
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/* z drawing mode. use MGADWG_NOZCMP for always */
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#define MGADWG_NOZCMP ( 0x00 << 8 )
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#define MGADWG_ZE ( 0x02 << 8 )
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#define MGADWG_ZNE ( 0x03 << 8 )
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#define MGADWG_ZLT ( 0x04 << 8 )
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#define MGADWG_ZLTE ( 0x05 << 8 )
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#define MGADWG_GT ( 0x06 << 8 )
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#define MGADWG_GTE ( 0x07 << 8 )
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/* use this to force colour expansion circuitry to do its stuff */
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#define MGADWG_SOLID ( 0x01 << 11 )
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/* ar register at zero */
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#define MGADWG_ARZERO ( 0x01 << 12 )
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#define MGADWG_SGNZERO ( 0x01 << 13 )
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#define MGADWG_SHIFTZERO ( 0x01 << 14 )
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/* See table on 4-43 for bop ALU operations */
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/* See table on 4-44 for translucidity masks */
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#define MGADWG_BMONOLEF ( 0x00 << 25 )
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#define MGADWG_BMONOWF ( 0x04 << 25 )
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#define MGADWG_BPLAN ( 0x01 << 25 )
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/* note that if bfcol is specified and you're doing a bitblt, it causes
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a fbitblt to be performed, so check that you obey the fbitblt rules */
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#define MGADWG_BFCOL ( 0x02 << 25 )
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#define MGADWG_BUYUV ( 0x0e << 25 )
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#define MGADWG_BU32BGR ( 0x03 << 25 )
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#define MGADWG_BU32RGB ( 0x07 << 25 )
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#define MGADWG_BU24BGR ( 0x0b << 25 )
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#define MGADWG_BU24RGB ( 0x0f << 25 )
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#define MGADWG_PATTERN ( 0x01 << 29 )
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#define MGADWG_TRANSC ( 0x01 << 30 )
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#define MGAREG_MISC_WRITE 0x3c2
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#define MGAREG_MISC_READ 0x3cc
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#define MGAREG_MISC_IOADSEL (0x1 << 0)
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#define MGAREG_MISC_RAMMAPEN (0x1 << 1)
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#define MGAREG_MISC_CLK_SEL_VGA25 (0x0 << 2)
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#define MGAREG_MISC_CLK_SEL_VGA28 (0x1 << 2)
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#define MGAREG_MISC_CLK_SEL_MGA_PIX (0x2 << 2)
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#define MGAREG_MISC_CLK_SEL_MGA_MSK (0x3 << 2)
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#define MGAREG_MISC_VIDEO_DIS (0x1 << 4)
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#define MGAREG_MISC_HIGH_PG_SEL (0x1 << 5)
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/* MMIO VGA registers */
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#define MGAREG_SEQ_INDEX 0x1fc4
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#define MGAREG_SEQ_DATA 0x1fc5
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#define MGAREG_CRTC_INDEX 0x1fd4
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#define MGAREG_CRTC_DATA 0x1fd5
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#define MGAREG_CRTCEXT_INDEX 0x1fde
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#define MGAREG_CRTCEXT_DATA 0x1fdf
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/* MGA bits for registers PCI_OPTION_REG */
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#define MGA1064_OPT_SYS_CLK_PCI ( 0x00 << 0 )
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#define MGA1064_OPT_SYS_CLK_PLL ( 0x01 << 0 )
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#define MGA1064_OPT_SYS_CLK_EXT ( 0x02 << 0 )
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#define MGA1064_OPT_SYS_CLK_MSK ( 0x03 << 0 )
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#define MGA1064_OPT_SYS_CLK_DIS ( 0x01 << 2 )
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#define MGA1064_OPT_G_CLK_DIV_1 ( 0x01 << 3 )
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#define MGA1064_OPT_M_CLK_DIV_1 ( 0x01 << 4 )
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#define MGA1064_OPT_SYS_PLL_PDN ( 0x01 << 5 )
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#define MGA1064_OPT_VGA_ION ( 0x01 << 8 )
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/* MGA registers in PCI config space */
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#define PCI_MGA_INDEX 0x44
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#define PCI_MGA_DATA 0x48
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#define PCI_MGA_OPTION2 0x50
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#define PCI_MGA_OPTION3 0x54
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#define RAMDAC_OFFSET 0x3c00
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/* TVP3026 direct registers */
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#define TVP3026_INDEX 0x00
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#define TVP3026_WADR_PAL 0x00
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#define TVP3026_COL_PAL 0x01
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#define TVP3026_PIX_RD_MSK 0x02
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#define TVP3026_RADR_PAL 0x03
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#define TVP3026_CUR_COL_ADDR 0x04
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#define TVP3026_CUR_COL_DATA 0x05
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#define TVP3026_DATA 0x0a
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#define TVP3026_CUR_RAM 0x0b
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#define TVP3026_CUR_XLOW 0x0c
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#define TVP3026_CUR_XHI 0x0d
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#define TVP3026_CUR_YLOW 0x0e
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#define TVP3026_CUR_YHI 0x0f
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/* TVP3026 indirect registers */
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#define TVP3026_SILICON_REV 0x01
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#define TVP3026_CURSOR_CTL 0x06
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#define TVP3026_LATCH_CTL 0x0f
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#define TVP3026_TRUE_COLOR_CTL 0x18
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#define TVP3026_MUX_CTL 0x19
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#define TVP3026_CLK_SEL 0x1a
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#define TVP3026_PAL_PAGE 0x1c
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#define TVP3026_GEN_CTL 0x1d
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#define TVP3026_MISC_CTL 0x1e
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#define TVP3026_GEN_IO_CTL 0x2a
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#define TVP3026_GEN_IO_DATA 0x2b
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#define TVP3026_PLL_ADDR 0x2c
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#define TVP3026_PIX_CLK_DATA 0x2d
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#define TVP3026_MEM_CLK_DATA 0x2e
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#define TVP3026_LOAD_CLK_DATA 0x2f
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#define TVP3026_KEY_RED_LOW 0x32
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#define TVP3026_KEY_RED_HI 0x33
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#define TVP3026_KEY_GREEN_LOW 0x34
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#define TVP3026_KEY_GREEN_HI 0x35
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#define TVP3026_KEY_BLUE_LOW 0x36
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#define TVP3026_KEY_BLUE_HI 0x37
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#define TVP3026_KEY_CTL 0x38
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#define TVP3026_MCLK_CTL 0x39
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#define TVP3026_SENSE_TEST 0x3a
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#define TVP3026_TEST_DATA 0x3b
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#define TVP3026_CRC_LSB 0x3c
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#define TVP3026_CRC_MSB 0x3d
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#define TVP3026_CRC_CTL 0x3e
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#define TVP3026_ID 0x3f
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#define TVP3026_RESET 0xff
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/* MGA1064 DAC Register file */
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/* MGA1064 direct registers */
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#define MGA1064_INDEX 0x00
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#define MGA1064_WADR_PAL 0x00
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#define MGA1064_COL_PAL 0x01
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#define MGA1064_PIX_RD_MSK 0x02
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#define MGA1064_RADR_PAL 0x03
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#define MGA1064_DATA 0x0a
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#define MGA1064_CUR_XLOW 0x0c
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#define MGA1064_CUR_XHI 0x0d
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#define MGA1064_CUR_YLOW 0x0e
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#define MGA1064_CUR_YHI 0x0f
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/* MGA1064 indirect registers */
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#define MGA1064_DVI_PIPE_CTL 0x03
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#define MGA1064_CURSOR_BASE_ADR_LOW 0x04
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#define MGA1064_CURSOR_BASE_ADR_HI 0x05
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#define MGA1064_CURSOR_CTL 0x06
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#define MGA1064_CURSOR_COL0_RED 0x08
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#define MGA1064_CURSOR_COL0_GREEN 0x09
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#define MGA1064_CURSOR_COL0_BLUE 0x0a
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#define MGA1064_CURSOR_COL1_RED 0x0c
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#define MGA1064_CURSOR_COL1_GREEN 0x0d
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#define MGA1064_CURSOR_COL1_BLUE 0x0e
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#define MGA1064_CURSOR_COL2_RED 0x010
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#define MGA1064_CURSOR_COL2_GREEN 0x011
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#define MGA1064_CURSOR_COL2_BLUE 0x012
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#define MGA1064_VREF_CTL 0x018
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#define MGA1064_MUL_CTL 0x19
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#define MGA1064_MUL_CTL_8bits 0x0
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#define MGA1064_MUL_CTL_15bits 0x01
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#define MGA1064_MUL_CTL_16bits 0x02
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#define MGA1064_MUL_CTL_24bits 0x03
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#define MGA1064_MUL_CTL_32bits 0x04
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#define MGA1064_MUL_CTL_2G8V16bits 0x05
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#define MGA1064_MUL_CTL_G16V16bits 0x06
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#define MGA1064_MUL_CTL_32_24bits 0x07
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#define MGAGDAC_XVREFCTRL 0x18
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#define MGA1064_PIX_CLK_CTL 0x1a
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#define MGA1064_PIX_CLK_CTL_CLK_DIS ( 0x01 << 2 )
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#define MGA1064_PIX_CLK_CTL_CLK_POW_DOWN ( 0x01 << 3 )
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#define MGA1064_PIX_CLK_CTL_SEL_PCI ( 0x00 << 0 )
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#define MGA1064_PIX_CLK_CTL_SEL_PLL ( 0x01 << 0 )
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#define MGA1064_PIX_CLK_CTL_SEL_EXT ( 0x02 << 0 )
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#define MGA1064_PIX_CLK_CTL_SEL_MSK ( 0x03 << 0 )
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#define MGA1064_GEN_CTL 0x1d
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#define MGA1064_MISC_CTL 0x1e
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#define MGA1064_MISC_CTL_DAC_POW_DN ( 0x01 << 0 )
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#define MGA1064_MISC_CTL_VGA ( 0x01 << 1 )
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#define MGA1064_MISC_CTL_DIS_CON ( 0x03 << 1 )
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#define MGA1064_MISC_CTL_MAFC ( 0x02 << 1 )
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#define MGA1064_MISC_CTL_VGA8 ( 0x01 << 3 )
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#define MGA1064_MISC_CTL_DAC_RAM_CS ( 0x01 << 4 )
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#define MGA1064_GEN_IO_CTL 0x2a
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#define MGA1064_GEN_IO_DATA 0x2b
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#define MGA1064_SYS_PLL_M 0x2c
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#define MGA1064_SYS_PLL_N 0x2d
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#define MGA1064_SYS_PLL_P 0x2e
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#define MGA1064_SYS_PLL_STAT 0x2f
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#define MGA1064_ZOOM_CTL 0x38
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#define MGA1064_SENSE_TST 0x3a
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#define MGA1064_CRC_LSB 0x3c
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#define MGA1064_CRC_MSB 0x3d
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#define MGA1064_CRC_CTL 0x3e
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#define MGA1064_COL_KEY_MSK_LSB 0x40
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#define MGA1064_COL_KEY_MSK_MSB 0x41
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#define MGA1064_COL_KEY_LSB 0x42
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#define MGA1064_COL_KEY_MSB 0x43
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#define MGA1064_PIX_PLLA_M 0x44
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#define MGA1064_PIX_PLLA_N 0x45
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#define MGA1064_PIX_PLLA_P 0x46
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#define MGA1064_PIX_PLLB_M 0x48
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#define MGA1064_PIX_PLLB_N 0x49
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#define MGA1064_PIX_PLLB_P 0x4a
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#define MGA1064_PIX_PLLC_M 0x4c
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#define MGA1064_PIX_PLLC_N 0x4d
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#define MGA1064_PIX_PLLC_P 0x4e
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#define MGA1064_PIX_PLL_STAT 0x4f
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/*Added for G450 dual head*/
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#define __PIXEL_PLL 1
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#define __SYSTEM_PLL 2
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#define __VIDEO_PLL 3
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#define MGA1064_VID_PLL_P 0x8D
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#define MGA1064_VID_PLL_M 0x8E
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#define MGA1064_VID_PLL_N 0x8F
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#define MGA1064_DISP_CTL 0x8a
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#define MGA1064_SYNC_CTL 0x8b
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#define MGA1064_PWR_CTL 0xa0
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#define MGA1064_PAN_CTL 0xa2
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#define MGAREG2_C2CTL 0x10
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#define MGAREG2_C2HPARAM 0x14
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#define MGAREG2_C2HSYNC 0x18
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#define MGAREG2_C2VPARAM 0x1c
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#define MGAREG2_C2VSYNC 0x20
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#define MGAREG2_C2STARTADD0 0x28
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#define MGAREG2_C2OFFSET 0x40
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#define MGAREG2_C2DATACTL 0x4c
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#define MGAREG_C2CTL 0x3c10
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#define MGAREG_C2HPARAM 0x3c14
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#define MGAREG_C2HSYNC 0x3c18
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#define MGAREG_C2VPARAM 0x3c1c
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#define MGAREG_C2VSYNC 0x3c20
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#define MGAREG_C2STARTADD0 0x3c28
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#define MGAREG_C2OFFSET 0x3c40
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#define MGAREG_C2DATACTL 0x3c4c
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#define MGA1064_DISP_CTL 0x8a
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#define MGA1064_SYNC_CTL 0x8b
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#define MGA1064_PWR_CTL 0xa0
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#define MGAREG_BESA1C3ORG 0x3d60
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#define MGAREG_BESA1CORG 0x3d10
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#define MGAREG_BESA1ORG 0x3d00
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#define MGAREG_BESCTL 0x3d20
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#define MGAREG_BESGLOBCTL 0x3dc0
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#define MGAREG_BESHCOORD 0x3d28
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#define MGAREG_BESHISCAL 0x3d30
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#define MGAREG_BESHSRCEND 0x3d3c
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#define MGAREG_BESHSRCLST 0x3d50
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#define MGAREG_BESHSRCST 0x3d38
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#define MGAREG_BESLUMACTL 0x3d40
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#define MGAREG_BESPITCH 0x3d24
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#define MGAREG_BESV1SRCLST 0x3d54
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#define MGAREG_BESV1WGHT 0x3d48
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#define MGAREG_BESVCOORD 0x3d2c
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#define MGAREG_BESVISCAL 0x3d34
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/* texture engine registers */
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#define MGAREG_TMR0 0x2c00
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#define MGAREG_TMR1 0x2c04
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#define MGAREG_TMR2 0x2c08
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#define MGAREG_TMR3 0x2c0c
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#define MGAREG_TMR4 0x2c10
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#define MGAREG_TMR5 0x2c14
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#define MGAREG_TMR6 0x2c18
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#define MGAREG_TMR7 0x2c1c
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#define MGAREG_TMR8 0x2c20
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#define MGAREG_TEXORG 0x2c24
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#define MGAREG_TEXWIDTH 0x2c28
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#define MGAREG_TEXHEIGHT 0x2c2c
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#define MGAREG_TEXCTL 0x2c30
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#define MGAREG_TEXCTL2 0x2c3c
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#define MGAREG_TEXTRANS 0x2c34
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#define MGAREG_TEXTRANSHIGH 0x2c38
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#define MGAREG_TEXFILTER 0x2c58
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#define MGAREG_ALPHASTART 0x2c70
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#define MGAREG_ALPHAXINC 0x2c74
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#define MGAREG_ALPHAYINC 0x2c78
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#define MGAREG_ALPHACTRL 0x2c7c
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#define MGAREG_DWGSYNC 0x2c4c
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#define MGAREG_AGP_PLL 0x1e4c
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#define MGA_AGP2XPLL_ENABLE 0x1
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#define MGA_AGP2XPLL_DISABLE 0x0