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Viewing changes to debian/patches/ubuntu/arm64/0079-target-arm-A64-Add-Floating-point-data-processing-2-.patch

  • Committer: Package Import Robot
  • Author(s): Serge Hallyn
  • Date: 2014-02-25 22:31:43 UTC
  • mfrom: (1.8.5)
  • Revision ID: package-import@ubuntu.com-20140225223143-odhqxfc60wxrjl15
Tags: 2.0.0~rc1+dfsg-0ubuntu1
https://launchpad.net/bugs/1294823
https://launchpad.net/bugs/1295072
* Merge 2.0.0-rc1
* debian/rules: consolidate ppc filter entries.
* Move qemu-system-arch64 into qemu-system-arm
* debian/patches/define-trusty-machine-type.patch: define a trusty machine
  type, currently the same as pc-i440fx-2.0, to put is in a better position
  to enable live migrations from trusty onward.  (LP: #1294823)
* debian/control: build-dep on libfdt >= 1.4.0  (LP: #1295072)
* Merge latest upstream git to commit dc9528f
* Debian/rules:
  - remove -enable-uname-release=2.6.32
  - don't make the aarch64 target Ubuntu-specific.
* Remove patches which are now upstream:
  - fix-smb-security-share.patch
  - slirp-smb-redirect-port-445-too.patch 
  - linux-user-Implement-sendmmsg-syscall.patch (better version is upstream)
  - signal-added-a-wrapper-for-sigprocmask-function.patch
  - ubuntu/signal-sigsegv-protection-on-do_sigprocmask.patch
  - ubuntu/Don-t-block-SIGSEGV-at-more-places.patch
  - ubuntu/ppc-force-cpu-threads-count-to-be-power-of-2.patch
* add link for /usr/share/qemu/bios-256k.bin
* Remove all linaro patches.
* Remove all arm64/ patches.  Many but not all are upstream.
* Remove CVE-2013-4377.patch which is upstream.
* debian/control-in: don't make qemu-system-aarch64 ubuntu-specific

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debian/patches/ubuntu/arm64/0079-target-arm-A64-Add-Floating-point-data-processing-2-.patch
1
 
From eaaf9a2bacdda79d9af92f8d2f112aa918fa9c40 Mon Sep 17 00:00:00 2001
2
 
From: Alexander Graf <agraf@suse.de>
3
 
Date: Sat, 4 Jan 2014 22:15:50 +0000
4
 
Subject: [PATCH 079/158] target-arm: A64: Add "Floating-point data-processing
5
 
 (2 source)" insns
6
 
 
7
 
This patch adds emulation for the "Floating-point data-processing (2 source)"
8
 
group of instructions.
9
 
 
10
 
Signed-off-by: Alexander Graf <agraf@suse.de>
11
 
[WN: Commit message tweak, merge single and double precision patches. Rebase
12
 
 and update to new infrastructure. Incorporate FMIN/FMAX support patch by
13
 
 Michael Matz.]
14
 
Signed-off-by: Will Newton <will.newton@linaro.org>
15
 
[PMM:
16
 
 * added convenience accessors for FP s and d regs
17
 
 * pulled the field decode and opcode validity check up a level]
18
 
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
 
Reviewed-by: Richard Henderson <rth@twiddle.net>
20
 
---
21
 
 target-arm/translate-a64.c | 182 ++++++++++++++++++++++++++++++++++++++++++++-
22
 
 1 file changed, 181 insertions(+), 1 deletion(-)
23
 
 
24
 
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
25
 
index ba9573a..c406e2a 100644
26
 
--- a/target-arm/translate-a64.c
27
 
+++ b/target-arm/translate-a64.c
28
 
@@ -328,6 +328,60 @@ static inline int fp_reg_hi_offset(int regno)
29
 
     return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]);
30
 
 }
31
 
 
32
 
+/* Convenience accessors for reading and writing single and double
33
 
+ * FP registers. Writing clears the upper parts of the associated
34
 
+ * 128 bit vector register, as required by the architecture.
35
 
+ * Note that unlike the GP register accessors, the values returned
36
 
+ * by the read functions must be manually freed.
37
 
+ */
38
 
+static TCGv_i64 read_fp_dreg(DisasContext *s, int reg)
39
 
+{
40
 
+    TCGv_i64 v = tcg_temp_new_i64();
41
 
+
42
 
+    tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(reg, MO_64));
43
 
+    return v;
44
 
+}
45
 
+
46
 
+static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
47
 
+{
48
 
+    TCGv_i32 v = tcg_temp_new_i32();
49
 
+
50
 
+    tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(reg, MO_32));
51
 
+    return v;
52
 
+}
53
 
+
54
 
+static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
55
 
+{
56
 
+    TCGv_i64 tcg_zero = tcg_const_i64(0);
57
 
+
58
 
+    tcg_gen_st_i64(v, cpu_env, fp_reg_offset(reg, MO_64));
59
 
+    tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(reg));
60
 
+    tcg_temp_free_i64(tcg_zero);
61
 
+}
62
 
+
63
 
+static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
64
 
+{
65
 
+    TCGv_i64 tmp = tcg_temp_new_i64();
66
 
+
67
 
+    tcg_gen_extu_i32_i64(tmp, v);
68
 
+    write_fp_dreg(s, reg, tmp);
69
 
+    tcg_temp_free_i64(tmp);
70
 
+}
71
 
+
72
 
+static TCGv_ptr get_fpstatus_ptr(void)
73
 
+{
74
 
+    TCGv_ptr statusptr = tcg_temp_new_ptr();
75
 
+    int offset;
76
 
+
77
 
+    /* In A64 all instructions (both FP and Neon) use the FPCR;
78
 
+     * there is no equivalent of the A32 Neon "standard FPSCR value"
79
 
+     * and all operations use vfp.fp_status.
80
 
+     */
81
 
+    offset = offsetof(CPUARMState, vfp.fp_status);
82
 
+    tcg_gen_addi_ptr(statusptr, cpu_env, offset);
83
 
+    return statusptr;
84
 
+}
85
 
+
86
 
 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
87
 
  * than the 32 bit equivalent.
88
 
  */
89
 
@@ -3176,6 +3230,112 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
90
 
     unsupported_encoding(s, insn);
91
 
 }
92
 
 
93
 
+/* C3.6.26 Floating-point data-processing (2 source) - single precision */
94
 
+static void handle_fp_2src_single(DisasContext *s, int opcode,
95
 
+                                  int rd, int rn, int rm)
96
 
+{
97
 
+    TCGv_i32 tcg_op1;
98
 
+    TCGv_i32 tcg_op2;
99
 
+    TCGv_i32 tcg_res;
100
 
+    TCGv_ptr fpst;
101
 
+
102
 
+    tcg_res = tcg_temp_new_i32();
103
 
+    fpst = get_fpstatus_ptr();
104
 
+    tcg_op1 = read_fp_sreg(s, rn);
105
 
+    tcg_op2 = read_fp_sreg(s, rm);
106
 
+
107
 
+    switch (opcode) {
108
 
+    case 0x0: /* FMUL */
109
 
+        gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
110
 
+        break;
111
 
+    case 0x1: /* FDIV */
112
 
+        gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst);
113
 
+        break;
114
 
+    case 0x2: /* FADD */
115
 
+        gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
116
 
+        break;
117
 
+    case 0x3: /* FSUB */
118
 
+        gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
119
 
+        break;
120
 
+    case 0x4: /* FMAX */
121
 
+        gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
122
 
+        break;
123
 
+    case 0x5: /* FMIN */
124
 
+        gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
125
 
+        break;
126
 
+    case 0x6: /* FMAXNM */
127
 
+        gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
128
 
+        break;
129
 
+    case 0x7: /* FMINNM */
130
 
+        gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
131
 
+        break;
132
 
+    case 0x8: /* FNMUL */
133
 
+        gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
134
 
+        gen_helper_vfp_negs(tcg_res, tcg_res);
135
 
+        break;
136
 
+    }
137
 
+
138
 
+    write_fp_sreg(s, rd, tcg_res);
139
 
+
140
 
+    tcg_temp_free_ptr(fpst);
141
 
+    tcg_temp_free_i32(tcg_op1);
142
 
+    tcg_temp_free_i32(tcg_op2);
143
 
+    tcg_temp_free_i32(tcg_res);
144
 
+}
145
 
+
146
 
+/* C3.6.26 Floating-point data-processing (2 source) - double precision */
147
 
+static void handle_fp_2src_double(DisasContext *s, int opcode,
148
 
+                                  int rd, int rn, int rm)
149
 
+{
150
 
+    TCGv_i64 tcg_op1;
151
 
+    TCGv_i64 tcg_op2;
152
 
+    TCGv_i64 tcg_res;
153
 
+    TCGv_ptr fpst;
154
 
+
155
 
+    tcg_res = tcg_temp_new_i64();
156
 
+    fpst = get_fpstatus_ptr();
157
 
+    tcg_op1 = read_fp_dreg(s, rn);
158
 
+    tcg_op2 = read_fp_dreg(s, rm);
159
 
+
160
 
+    switch (opcode) {
161
 
+    case 0x0: /* FMUL */
162
 
+        gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
163
 
+        break;
164
 
+    case 0x1: /* FDIV */
165
 
+        gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst);
166
 
+        break;
167
 
+    case 0x2: /* FADD */
168
 
+        gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
169
 
+        break;
170
 
+    case 0x3: /* FSUB */
171
 
+        gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
172
 
+        break;
173
 
+    case 0x4: /* FMAX */
174
 
+        gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
175
 
+        break;
176
 
+    case 0x5: /* FMIN */
177
 
+        gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
178
 
+        break;
179
 
+    case 0x6: /* FMAXNM */
180
 
+        gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
181
 
+        break;
182
 
+    case 0x7: /* FMINNM */
183
 
+        gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
184
 
+        break;
185
 
+    case 0x8: /* FNMUL */
186
 
+        gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
187
 
+        gen_helper_vfp_negd(tcg_res, tcg_res);
188
 
+        break;
189
 
+    }
190
 
+
191
 
+    write_fp_dreg(s, rd, tcg_res);
192
 
+
193
 
+    tcg_temp_free_ptr(fpst);
194
 
+    tcg_temp_free_i64(tcg_op1);
195
 
+    tcg_temp_free_i64(tcg_op2);
196
 
+    tcg_temp_free_i64(tcg_res);
197
 
+}
198
 
+
199
 
 /* C3.6.26 Floating point data-processing (2 source)
200
 
  *   31  30  29 28       24 23  22  21 20  16 15    12 11 10 9    5 4    0
201
 
  * +---+---+---+-----------+------+---+------+--------+-----+------+------+
202
 
@@ -3184,7 +3344,27 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
203
 
  */
204
 
 static void disas_fp_2src(DisasContext *s, uint32_t insn)
205
 
 {
206
 
-    unsupported_encoding(s, insn);
207
 
+    int type = extract32(insn, 22, 2);
208
 
+    int rd = extract32(insn, 0, 5);
209
 
+    int rn = extract32(insn, 5, 5);
210
 
+    int rm = extract32(insn, 16, 5);
211
 
+    int opcode = extract32(insn, 12, 4);
212
 
+
213
 
+    if (opcode > 8) {
214
 
+        unallocated_encoding(s);
215
 
+        return;
216
 
+    }
217
 
+
218
 
+    switch (type) {
219
 
+    case 0:
220
 
+        handle_fp_2src_single(s, opcode, rd, rn, rm);
221
 
+        break;
222
 
+    case 1:
223
 
+        handle_fp_2src_double(s, opcode, rd, rn, rm);
224
 
+        break;
225
 
+    default:
226
 
+        unallocated_encoding(s);
227
 
+    }
228
 
 }
229
 
 
230
 
 /* C3.6.27 Floating point data-processing (3 source)
231
 
1.9.rc1
232