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Viewing changes to debian/patches/ubuntu/arm64/0140-target-arm-A64-Implement-SIMD-3-reg-same-shift-and-s.patch

  • Committer: Package Import Robot
  • Author(s): Serge Hallyn
  • Date: 2014-02-25 22:31:43 UTC
  • mfrom: (1.8.5)
  • Revision ID: package-import@ubuntu.com-20140225223143-odhqxfc60wxrjl15
Tags: 2.0.0~rc1+dfsg-0ubuntu1
https://launchpad.net/bugs/1294823
https://launchpad.net/bugs/1295072
* Merge 2.0.0-rc1
* debian/rules: consolidate ppc filter entries.
* Move qemu-system-arch64 into qemu-system-arm
* debian/patches/define-trusty-machine-type.patch: define a trusty machine
  type, currently the same as pc-i440fx-2.0, to put is in a better position
  to enable live migrations from trusty onward.  (LP: #1294823)
* debian/control: build-dep on libfdt >= 1.4.0  (LP: #1295072)
* Merge latest upstream git to commit dc9528f
* Debian/rules:
  - remove -enable-uname-release=2.6.32
  - don't make the aarch64 target Ubuntu-specific.
* Remove patches which are now upstream:
  - fix-smb-security-share.patch
  - slirp-smb-redirect-port-445-too.patch 
  - linux-user-Implement-sendmmsg-syscall.patch (better version is upstream)
  - signal-added-a-wrapper-for-sigprocmask-function.patch
  - ubuntu/signal-sigsegv-protection-on-do_sigprocmask.patch
  - ubuntu/Don-t-block-SIGSEGV-at-more-places.patch
  - ubuntu/ppc-force-cpu-threads-count-to-be-power-of-2.patch
* add link for /usr/share/qemu/bios-256k.bin
* Remove all linaro patches.
* Remove all arm64/ patches.  Many but not all are upstream.
* Remove CVE-2013-4377.patch which is upstream.
* debian/control-in: don't make qemu-system-aarch64 ubuntu-specific

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debian/patches/ubuntu/arm64/0140-target-arm-A64-Implement-SIMD-3-reg-same-shift-and-s.patch
1
 
From 245abfd6f5482644b79602292326605d4e3817df Mon Sep 17 00:00:00 2001
2
 
From: Peter Maydell <peter.maydell@linaro.org>
3
 
Date: Sat, 8 Feb 2014 14:46:55 +0000
4
 
Subject: [PATCH 140/158] target-arm: A64: Implement SIMD 3-reg-same shift and
5
 
 saturate insns
6
 
 
7
 
Implement the SIMD 3-reg-same instructions SQADD, UQADD,
8
 
SQSUB, UQSUB, SSHL, USHL, SQSHl, UQSHL, SRSHL, URSHL,
9
 
SQRSHL, UQRSHL; these are all simple calls to existing
10
 
Neon helpers. We also enable SSHL, USHL, SRSHL and URSHL
11
 
for the 3-reg-same-scalar category (but not the others
12
 
because they can have non-size-64 operands and the
13
 
scalar_3reg_same function doesn't support that yet.)
14
 
 
15
 
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
 
Reviewed-by: Richard Henderson <rth@twiddle.net>
17
 
---
18
 
 target-arm/translate-a64.c | 134 +++++++++++++++++++++++++++++++++++++--------
19
 
 1 file changed, 112 insertions(+), 22 deletions(-)
20
 
 
21
 
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
22
 
index 6c1ec1e..e67cdbb 100644
23
 
--- a/target-arm/translate-a64.c
24
 
+++ b/target-arm/translate-a64.c
25
 
@@ -74,6 +74,7 @@ typedef struct AArch64DecodeTable {
26
 
 
27
 
 /* Function prototype for gen_ functions for calling Neon helpers */
28
 
 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
29
 
+typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
30
 
 
31
 
 /* initialize TCG globals.  */
32
 
 void a64_translate_init(void)
33
 
@@ -5738,6 +5739,20 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
34
 
     TCGCond cond;
35
 
 
36
 
     switch (opcode) {
37
 
+    case 0x1: /* SQADD */
38
 
+        if (u) {
39
 
+            gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
40
 
+        } else {
41
 
+            gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
42
 
+        }
43
 
+        break;
44
 
+    case 0x5: /* SQSUB */
45
 
+        if (u) {
46
 
+            gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
47
 
+        } else {
48
 
+            gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
49
 
+        }
50
 
+        break;
51
 
     case 0x6: /* CMGT, CMHI */
52
 
         /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
53
 
          * We implement this using setcond (test) and then negating.
54
 
@@ -5760,19 +5775,41 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
55
 
         tcg_gen_setcondi_i64(TCG_COND_NE, tcg_rd, tcg_rd, 0);
56
 
         tcg_gen_neg_i64(tcg_rd, tcg_rd);
57
 
         break;
58
 
-    case 0x10: /* ADD, SUB */
59
 
+    case 0x8: /* SSHL, USHL */
60
 
         if (u) {
61
 
-            tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm);
62
 
+            gen_helper_neon_shl_u64(tcg_rd, tcg_rn, tcg_rm);
63
 
         } else {
64
 
-            tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm);
65
 
+            gen_helper_neon_shl_s64(tcg_rd, tcg_rn, tcg_rm);
66
 
         }
67
 
         break;
68
 
-    case 0x1: /* SQADD */
69
 
-    case 0x5: /* SQSUB */
70
 
-    case 0x8: /* SSHL, USHL */
71
 
     case 0x9: /* SQSHL, UQSHL */
72
 
+        if (u) {
73
 
+            gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
74
 
+        } else {
75
 
+            gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
76
 
+        }
77
 
+        break;
78
 
     case 0xa: /* SRSHL, URSHL */
79
 
+        if (u) {
80
 
+            gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm);
81
 
+        } else {
82
 
+            gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm);
83
 
+        }
84
 
+        break;
85
 
     case 0xb: /* SQRSHL, UQRSHL */
86
 
+        if (u) {
87
 
+            gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
88
 
+        } else {
89
 
+            gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
90
 
+        }
91
 
+        break;
92
 
+    case 0x10: /* ADD, SUB */
93
 
+        if (u) {
94
 
+            tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm);
95
 
+        } else {
96
 
+            tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm);
97
 
+        }
98
 
+        break;
99
 
     default:
100
 
         g_assert_not_reached();
101
 
     }
102
 
@@ -5949,10 +5986,10 @@ static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
103
 
     switch (opcode) {
104
 
     case 0x1: /* SQADD, UQADD */
105
 
     case 0x5: /* SQSUB, UQSUB */
106
 
-    case 0x8: /* SSHL, USHL */
107
 
-    case 0xa: /* SRSHL, URSHL */
108
 
         unsupported_encoding(s, insn);
109
 
         return;
110
 
+    case 0x8: /* SSHL, USHL */
111
 
+    case 0xa: /* SRSHL, URSHL */
112
 
     case 0x6: /* CMGT, CMHI */
113
 
     case 0x7: /* CMGE, CMHS */
114
 
     case 0x11: /* CMTST, CMEQ */
115
 
@@ -6621,18 +6658,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
116
 
         }
117
 
         unsupported_encoding(s, insn);
118
 
         return;
119
 
-    case 0x1: /* SQADD */
120
 
-    case 0x5: /* SQSUB */
121
 
-    case 0x8: /* SSHL, USHL */
122
 
-    case 0x9: /* SQSHL, UQSHL */
123
 
-    case 0xa: /* SRSHL, URSHL */
124
 
-    case 0xb: /* SQRSHL, UQRSHL */
125
 
-        if (size == 3 && !is_q) {
126
 
-            unallocated_encoding(s);
127
 
-            return;
128
 
-        }
129
 
-        unsupported_encoding(s, insn);
130
 
-        return;
131
 
     case 0x16: /* SQDMULH, SQRDMULH */
132
 
         if (size == 0 || size == 3) {
133
 
             unallocated_encoding(s);
134
 
@@ -6670,12 +6695,33 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
135
 
             TCGv_i32 tcg_op1 = tcg_temp_new_i32();
136
 
             TCGv_i32 tcg_op2 = tcg_temp_new_i32();
137
 
             TCGv_i32 tcg_res = tcg_temp_new_i32();
138
 
-            NeonGenTwoOpFn *genfn;
139
 
+            NeonGenTwoOpFn *genfn = NULL;
140
 
+            NeonGenTwoOpEnvFn *genenvfn = NULL;
141
 
 
142
 
             read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);
143
 
             read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
144
 
 
145
 
             switch (opcode) {
146
 
+            case 0x1: /* SQADD, UQADD */
147
 
+            {
148
 
+                static NeonGenTwoOpEnvFn * const fns[3][2] = {
149
 
+                    { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 },
150
 
+                    { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 },
151
 
+                    { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 },
152
 
+                };
153
 
+                genenvfn = fns[size][u];
154
 
+                break;
155
 
+            }
156
 
+            case 0x5: /* SQSUB, UQSUB */
157
 
+            {
158
 
+                static NeonGenTwoOpEnvFn * const fns[3][2] = {
159
 
+                    { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 },
160
 
+                    { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 },
161
 
+                    { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 },
162
 
+                };
163
 
+                genenvfn = fns[size][u];
164
 
+                break;
165
 
+            }
166
 
             case 0x6: /* CMGT, CMHI */
167
 
             {
168
 
                 static NeonGenTwoOpFn * const fns[3][2] = {
169
 
@@ -6696,6 +6742,46 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
170
 
                 genfn = fns[size][u];
171
 
                 break;
172
 
             }
173
 
+            case 0x8: /* SSHL, USHL */
174
 
+            {
175
 
+                static NeonGenTwoOpFn * const fns[3][2] = {
176
 
+                    { gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 },
177
 
+                    { gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 },
178
 
+                    { gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 },
179
 
+                };
180
 
+                genfn = fns[size][u];
181
 
+                break;
182
 
+            }
183
 
+            case 0x9: /* SQSHL, UQSHL */
184
 
+            {
185
 
+                static NeonGenTwoOpEnvFn * const fns[3][2] = {
186
 
+                    { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 },
187
 
+                    { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 },
188
 
+                    { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 },
189
 
+                };
190
 
+                genenvfn = fns[size][u];
191
 
+                break;
192
 
+            }
193
 
+            case 0xa: /* SRSHL, URSHL */
194
 
+            {
195
 
+                static NeonGenTwoOpFn * const fns[3][2] = {
196
 
+                    { gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 },
197
 
+                    { gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 },
198
 
+                    { gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 },
199
 
+                };
200
 
+                genfn = fns[size][u];
201
 
+                break;
202
 
+            }
203
 
+            case 0xb: /* SQRSHL, UQRSHL */
204
 
+            {
205
 
+                static NeonGenTwoOpEnvFn * const fns[3][2] = {
206
 
+                    { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 },
207
 
+                    { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 },
208
 
+                    { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 },
209
 
+                };
210
 
+                genenvfn = fns[size][u];
211
 
+                break;
212
 
+            }
213
 
             case 0x10: /* ADD, SUB */
214
 
             {
215
 
                 static NeonGenTwoOpFn * const fns[3][2] = {
216
 
@@ -6720,7 +6806,11 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
217
 
                 g_assert_not_reached();
218
 
             }
219
 
 
220
 
-            genfn(tcg_res, tcg_op1, tcg_op2);
221
 
+            if (genenvfn) {
222
 
+                genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2);
223
 
+            } else {
224
 
+                genfn(tcg_res, tcg_op1, tcg_op2);
225
 
+            }
226
 
 
227
 
             write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
228
 
 
229
 
1.9.rc1
230