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Viewing changes to debian/patches/ubuntu/linaro/0049-Add-triton2-twl4030-driver.patch

  • Committer: Package Import Robot
  • Author(s): Serge Hallyn
  • Date: 2014-02-25 22:31:43 UTC
  • mfrom: (1.8.5)
  • Revision ID: package-import@ubuntu.com-20140225223143-odhqxfc60wxrjl15
Tags: 2.0.0~rc1+dfsg-0ubuntu1
https://launchpad.net/bugs/1294823
https://launchpad.net/bugs/1295072
* Merge 2.0.0-rc1
* debian/rules: consolidate ppc filter entries.
* Move qemu-system-arch64 into qemu-system-arm
* debian/patches/define-trusty-machine-type.patch: define a trusty machine
  type, currently the same as pc-i440fx-2.0, to put is in a better position
  to enable live migrations from trusty onward.  (LP: #1294823)
* debian/control: build-dep on libfdt >= 1.4.0  (LP: #1295072)
* Merge latest upstream git to commit dc9528f
* Debian/rules:
  - remove -enable-uname-release=2.6.32
  - don't make the aarch64 target Ubuntu-specific.
* Remove patches which are now upstream:
  - fix-smb-security-share.patch
  - slirp-smb-redirect-port-445-too.patch 
  - linux-user-Implement-sendmmsg-syscall.patch (better version is upstream)
  - signal-added-a-wrapper-for-sigprocmask-function.patch
  - ubuntu/signal-sigsegv-protection-on-do_sigprocmask.patch
  - ubuntu/Don-t-block-SIGSEGV-at-more-places.patch
  - ubuntu/ppc-force-cpu-threads-count-to-be-power-of-2.patch
* add link for /usr/share/qemu/bios-256k.bin
* Remove all linaro patches.
* Remove all arm64/ patches.  Many but not all are upstream.
* Remove CVE-2013-4377.patch which is upstream.
* debian/control-in: don't make qemu-system-aarch64 ubuntu-specific

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Lines of Context:
debian/patches/ubuntu/linaro/0049-Add-triton2-twl4030-driver.patch
1
 
From 40d60ccbfa51b8d1049efec2ffde99e43a4d9c2d Mon Sep 17 00:00:00 2001
2
 
From: Peter Maydell <peter.maydell@linaro.org>
3
 
Date: Mon, 18 Feb 2013 16:58:31 +0000
4
 
Subject: [PATCH 49/70] Add triton2 (twl4030) driver
5
 
MIME-Version: 1.0
6
 
Content-Type: text/plain; charset=UTF-8
7
 
Content-Transfer-Encoding: 8bit
8
 
 
9
 
The swiss knife companion chip for omap3
10
 
 
11
 
includes change from Loïc Minier <lool@dooz.org>:
12
 
twl4030: Add PWMB OFF and ON regs
13
 
twl4030: add SW2 conversion channels
14
 
includes change from PMM: add dummy BCISIHCTRL
15
 
includes change from Riku: add carkit analog control registers
16
 
includes change from Riku: add rtc alarm and periodic interrupts
17
 
includes: twl4030: add callback for providing madc results
18
 
 
19
 
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
20
 
Signed-off-by: Riku Voipo <riku.voipio@nokia.com>
21
 
Signed-off-by: Loïc Minier <lool@dooz.org>
22
 
---
23
 
 hw/misc/Makefile.objs |    1 +
24
 
 hw/misc/twl4030.c     | 1808 +++++++++++++++++++++++++++++++++++++++++++++++++
25
 
 include/hw/i2c/i2c.h  |   19 +
26
 
 3 files changed, 1828 insertions(+)
27
 
 create mode 100644 hw/misc/twl4030.c
28
 
 
29
 
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
30
 
index aee75c1..70d794d 100644
31
 
--- a/hw/misc/Makefile.objs
32
 
+++ b/hw/misc/Makefile.objs
33
 
@@ -39,6 +39,7 @@ obj-$(CONFIG_OMAP) += omap_l4.o
34
 
 obj-$(CONFIG_OMAP) += omap_sdrc.o
35
 
 obj-$(CONFIG_OMAP) += omap_tap.o
36
 
 obj-$(CONFIG_OMAP) += omap3_boot.o
37
 
+obj-$(CONFIG_OMAP) += twl4030.o
38
 
 obj-$(CONFIG_SLAVIO) += slavio_misc.o
39
 
 obj-$(CONFIG_ZYNQ) += zynq_slcr.o
40
 
 
41
 
diff --git a/hw/misc/twl4030.c b/hw/misc/twl4030.c
42
 
new file mode 100644
43
 
index 0000000..2a27e04
44
 
--- /dev/null
45
 
+++ b/hw/misc/twl4030.c
46
 
@@ -0,0 +1,1808 @@
47
 
+/*
48
 
+ * TI TWL4030 emulation
49
 
+ *
50
 
+ * Copyright (C) 2008 yajin<yajin@vm-kernel.org>
51
 
+ * Copyright (C) 2009-2010 Nokia Corporation
52
 
+ *
53
 
+ * Register implementation based on TPS65950 ES1.0 specification.
54
 
+ *
55
 
+ * This program is free software; you can redistribute it and/or
56
 
+ * modify it under the terms of the GNU General Public License as
57
 
+ * published by the Free Software Foundation; either version 2 or
58
 
+ * (at your option) version 3 of the License.
59
 
+ *
60
 
+ * This program is distributed in the hope that it will be useful,
61
 
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
62
 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
63
 
+ * GNU General Public License for more details.
64
 
+ *
65
 
+ * You should have received a copy of the GNU General Public License
66
 
+ * along with this program; if not, write to the Free Software
67
 
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
68
 
+ * MA 02111-1307 USA
69
 
+ */
70
 
+
71
 
+#include "hw/hw.h"
72
 
+#include "qemu/timer.h"
73
 
+#include "hw/i2c/i2c.h"
74
 
+#include "sysemu/sysemu.h"
75
 
+#include "ui/console.h"
76
 
+#include "exec/cpu-all.h"
77
 
+
78
 
+//#define DEBUG_GENERAL
79
 
+//#define DEBUG_RTC
80
 
+
81
 
+#define DEBUG_TRACE(fmt, ...) fprintf(stderr, "%s@%d: " fmt "\n", \
82
 
+                                      __FUNCTION__, __LINE__, ##__VA_ARGS__)
83
 
+
84
 
+#ifdef DEBUG_GENERAL
85
 
+#define TRACE(...) DEBUG_TRACE(__VA_ARGS__)
86
 
+#else
87
 
+#define TRACE(...)
88
 
+#endif
89
 
+
90
 
+#ifdef DEBUG_RTC
91
 
+#define TRACE_RTC(...) DEBUG_TRACE(__VA_ARGS__)
92
 
+#else
93
 
+#define TRACE_RTC(...)
94
 
+#endif
95
 
+
96
 
+typedef struct TWL4030State TWL4030State;
97
 
+typedef struct TWL4030NodeState TWL4030NodeState;
98
 
+
99
 
+typedef uint8_t (*twl4030_read_func)(TWL4030NodeState *s,
100
 
+                                     uint8_t addr);
101
 
+typedef void (*twl4030_write_func)(TWL4030NodeState *s,
102
 
+                                   uint8_t addr, uint8_t value);
103
 
+
104
 
+struct TWL4030NodeState {
105
 
+    I2CSlave i2c;
106
 
+    int firstbyte;
107
 
+    uint8_t reg;
108
 
+
109
 
+    twl4030_read_func read_func;
110
 
+    twl4030_write_func write_func;
111
 
+    TWL4030State *twl4030;
112
 
+
113
 
+    uint8 reg_data[256];
114
 
+};
115
 
+
116
 
+struct TWL4030State {
117
 
+    qemu_irq irq1;
118
 
+    qemu_irq irq2;
119
 
+    QEMUTimer *alarm_timer;
120
 
+    QEMUTimer *periodic_timer;
121
 
+    const TWL4030KeyMap *keymap;
122
 
+    int extended_key;
123
 
+    uint8_t twl5031;
124
 
+    uint8_t twl5031_aciid;
125
 
+    twl4030_madc_callback madc_cb;
126
 
+
127
 
+    int key_cfg;
128
 
+    int key_tst;
129
 
+
130
 
+    TWL4030NodeState *i2c[4];
131
 
+
132
 
+    uint8_t seq_mem[64][4]; /* power-management sequencing memory */
133
 
+};
134
 
+
135
 
+static const uint8_t addr_48_reset_values[256] = {
136
 
+    0x51, 0x04, 0x02, 0xc0, 0x41, 0x41, 0x41, 0x10, /* 0x00...0x07 */
137
 
+    0x10, 0x10, 0x06, 0x06, 0x06, 0x1f, 0x1f, 0x1f, /* 0x08...0x0f */
138
 
+    0x1f, 0x1f, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x10...0x17 */
139
 
+    0x00, 0x00, 0x00, 0x00, 0x52, 0x00, 0x00, 0x00, /* 0x18...0x1f */
140
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0a, 0x03, /* 0x20...0x27 */
141
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x28...0x2f */
142
 
+    0x00, 0x00, 0x00, 0x04, 0x04, 0x04, 0x00, 0x00, /* 0x30...0x37 */
143
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x38...0x3f */
144
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x40...0x47 */
145
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x48...0x4f */
146
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x50...0x57 */
147
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x58...0x5f */
148
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x60...0x67 */
149
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x68...0x6f */
150
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x70...0x77 */
151
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x78...0x7f */
152
 
+    0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x00, 0x00, /* 0x80...0x87 */
153
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x88...0x8f */
154
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x90...0x97 */
155
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x98...0x9f */
156
 
+    0x00, 0x10, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, /* 0xa0...0xa7 */
157
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xa8...0xaf */
158
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xb0...0xb7 */
159
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xb8...0xb8 */
160
 
+    0xa0, 0xa0, 0x64, 0x7f, 0x6c, 0x75, 0x64, 0x20, /* 0xc0...0xc7 */
161
 
+    0x01, 0x17, 0x01, 0x02, 0x00, 0x36, 0x44, 0x07, /* 0xc8...0xcf */
162
 
+    0x3b, 0x17, 0x6b, 0x04, 0x00, 0x00, 0x00, 0x00, /* 0xd0...0xd7 */
163
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xd8...0xdf */
164
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xe0...0xe7 */
165
 
+    0x00, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, /* 0xe8...0xef */
166
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xf0...0xf7 */
167
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00  /* 0xf8...0xff */
168
 
+};
169
 
+
170
 
+static const uint8_t addr_49_reset_values[256] = {
171
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x00...0x07 */
172
 
+    0x00, 0x00, 0x0f, 0x0f, 0x0f, 0x0f, 0x00, 0x00, /* 0x08...0x0f */
173
 
+    0x3f, 0x3f, 0x3f, 0x3f, 0x25, 0x00, 0x00, 0x00, /* 0x10...0x17 */
174
 
+    0x00, 0x32, 0x32, 0x32, 0x32, 0x00, 0x00, 0x55, /* 0x18...0x1f */
175
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20...0x27 */
176
 
+    0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00, /* 0x28...0x2f */
177
 
+    0x13, 0x00, 0x00, 0x00, 0x00, 0x79, 0x11, 0x00, /* 0x30...0x37 */
178
 
+    0x00, 0x00, 0x06, 0x00, 0x44, 0x69, 0x00, 0x00, /* 0x38...0x3f */
179
 
+    0x00, 0x00, 0x00, 0x00, 0x32, 0x00, 0x00, 0x00, /* 0x40...0x47 */
180
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x48...0x4f */
181
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x50...0x57 */
182
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x58...0x5f */
183
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x60...0x67 */
184
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x68...0x6f */
185
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x70...0x77 */
186
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x78...0x7f */
187
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x80...0x87 */
188
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x88...0x8f */
189
 
+    0x00, 0x90, 0x00, 0x00, 0x55, 0x00, 0x00, 0x00, /* 0x90...0x97 */
190
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x98...0x9f */
191
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xa0...0xa7 */
192
 
+    0x00, 0x00, 0x04, 0x00, 0x55, 0x01, 0x55, 0x05, /* 0xa8...0xaf */
193
 
+    0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x03, 0x00, /* 0xb0...0xb7 */
194
 
+    0x00, 0x00, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, /* 0xb8...0xbf */
195
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, /* 0xc0...0xc7 */
196
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xc8...0xcf */
197
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xd0...0xd7 */
198
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xd8...0xdf */
199
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xe0...0xe7 */
200
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xe8...0xef */
201
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xf0...0xf7 */
202
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xf8...0xff */
203
 
+};
204
 
+
205
 
+static const uint8_t addr_4a_reset_values[256] = {
206
 
+    0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x00...0x07 */
207
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x08...0x0f */
208
 
+    0xc0, 0x8c, 0xde, 0xde, 0x00, 0x00, 0x00, 0x00, /* 0x10...0x17 */
209
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x18...0x1f */
210
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20...0x27 */
211
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x28...0x2f */
212
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30...0x37 */
213
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x38...0x3f */
214
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x40...0x47 */
215
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x48...0x4f */
216
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x50...0x57 */
217
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x58...0x5f */
218
 
+    0x00, 0x00, 0x0f, 0x00, 0x0f, 0x00, 0x55, 0x07, /* 0x60...0x67 */
219
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x68...0x6f */
220
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x70...0x77 */
221
 
+    0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x78...0x7f */
222
 
+    0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, /* 0x80...0x87 */
223
 
+    0x00, 0x68, 0x9b, 0x86, 0x48, 0x2a, 0x07, 0x28, /* 0x88...0x8f */
224
 
+    0x09, 0x69, 0x90, 0x00, 0x2a, 0x00, 0x02, 0x00, /* 0x90...0x97 */
225
 
+    0x10, 0xcd, 0x02, 0x68, 0x03, 0x00, 0x00, 0x00, /* 0x98...0x9f */
226
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xa0...0xa7 */
227
 
+    0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, /* 0xa8...0xaf */
228
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xb0...0xb7 */
229
 
+    0x00, 0x00, 0x00, 0xff, 0x0f, 0x00, 0x00, 0xff, /* 0xb8...0xbf */
230
 
+    0x0f, 0x00, 0x00, 0xbf, 0x00, 0x00, 0x01, 0x00, /* 0xc0...0xc7 */
231
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xc8...0xcf */
232
 
+    0x00, 0x00, 0x03, 0x00, 0x00, 0xe0, 0x00, 0x00, /* 0xd0...0xd7 */
233
 
+    0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xd8...0xdf */
234
 
+    0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x0f, 0x00, /* 0xe0...0xe7 */
235
 
+    0x55, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xe8...0xef */
236
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xf0...0xf7 */
237
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00  /* 0xf8...0xff */
238
 
+};
239
 
+
240
 
+static const uint8_t addr_4b_reset_values[256] = {
241
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x00...0x07 */
242
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x08...0x0f */
243
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x10...0x17 */
244
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, /* 0x18...0x1f */
245
 
+    0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, /* 0x20...0x27 */
246
 
+    0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x01, 0x00, /* 0x28...0x2f */
247
 
+    0x00, 0x00, 0x00, 0xff, 0xff, 0x01, 0xbf, 0xbf, /* 0x30...0x37 */
248
 
+    0xbf, 0xab, 0x00, 0x08, 0x3f, 0x15, 0x40, 0x0e, /* 0x38...0x3f */
249
 
+    0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x40...0x47 */
250
 
+    0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, /* 0x48...0x4f */
251
 
+    0x00, 0x02, 0x00, 0x04, 0x0d, 0x00, 0x00, 0x00, /* 0x50...0x57 */
252
 
+    0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x58...0x5f */
253
 
+    0x00, 0x00, 0x2f, 0x18, 0x0f, 0x08, 0x0f, 0x08, /* 0x60...0x67 */
254
 
+    0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x68...0x6f */
255
 
+    0x00, 0x00, 0x00, 0x00, 0x08, 0x02, 0x80, 0x03, /* 0x70...0x77 */
256
 
+    0x08, 0x09, 0x00, 0x00, 0x08, 0x03, 0x80, 0x03, /* 0x78...0x7f */
257
 
+    0x08, 0x02, 0x00, 0x00, 0x08, 0x00, 0x80, 0x03, /* 0x80...0x87 */
258
 
+    0x08, 0x08, 0x20, 0x00, 0x00, 0x02, 0x80, 0x04, /* 0x88...0x8f */
259
 
+    0x08, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, /* 0x90...0x97 */
260
 
+    0x08, 0x02, 0xe0, 0x01, 0x08, 0x00, 0xe0, 0x00, /* 0x98...0x9f */
261
 
+    0x08, 0x01, 0xe0, 0x01, 0x08, 0x04, 0xe0, 0x03, /* 0xa0...0xa7 */
262
 
+    0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xa8...0xaf */
263
 
+    0x20, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xb0...0xb7 */
264
 
+    0x00, 0x38, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, /* 0xb8...0xbf */
265
 
+    0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, /* 0xc0...0xc7 */
266
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, /* 0xc8...0xcf */
267
 
+    0x00, 0x08, 0xe0, 0x00, 0x08, 0x00, 0x00, 0x00, /* 0xd0...0xd7 */
268
 
+    0x14, 0x08, 0xe0, 0x02, 0x08, 0xe0, 0x00, 0x08, /* 0xd8...0xdf */
269
 
+    0xe0, 0x05, 0x08, 0xe0, 0x06, 0x08, 0xe0, 0x00, /* 0xe0...0xe7 */
270
 
+    0x08, 0xe0, 0x00, 0x08, 0xe0, 0x06, 0x06, 0xe0, /* 0xe8...0xef */
271
 
+    0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0xf0...0xf7 */
272
 
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00  /* 0xf8...0xff */
273
 
+};
274
 
+
275
 
+static void twl4030_interrupt_update(TWL4030State *s)
276
 
+{
277
 
+    uint8_t x = 0;
278
 
+    /* TODO: USB, BCI and GPIO interrupts */
279
 
+    if (s->irq1) {
280
 
+        /* KEYPAD */
281
 
+        if (((s->i2c[2]->reg_data[0xda] & 0x10) && /* SIR_EN */
282
 
+             s->i2c[2]->reg_data[0xe7]) ||         /* KEYP_SIR */
283
 
+            (s->i2c[2]->reg_data[0xe3] &           /* KEYP_ISR1 */
284
 
+             ~s->i2c[2]->reg_data[0xe4]))          /* KEYP_IMR1 */
285
 
+            x |= 0x02;                             /* PIH_ISR1 */
286
 
+        /* MADC */
287
 
+        if (s->i2c[2]->reg_data[0x65] ||           /* MADC_SIR */
288
 
+            (s->i2c[2]->reg_data[0x61] &           /* MADC_ISR1 */
289
 
+             ~s->i2c[2]->reg_data[0x62]))          /* MADC_IMR1 */
290
 
+            x |= 0x08;                             /* PIH_ISR3 */
291
 
+        /* PM */
292
 
+        if ((s->i2c[3]->reg_data[0x2e] &           /* PWR_ISR1 */
293
 
+             ~s->i2c[3]->reg_data[0x2f]))          /* PWR_IMR1 */
294
 
+            x |= 0x20;                             /* PIH_ISR5 */
295
 
+
296
 
+        s->i2c[1]->reg_data[0x81] = x;             /* PIH_ISR_P1 */
297
 
+        qemu_set_irq(s->irq1, x);
298
 
+    }
299
 
+    if (s->irq2) {
300
 
+        /* KEYPAD */
301
 
+        if (((s->i2c[2]->reg_data[0xda] & 0x10) && /* SIR_EN */
302
 
+             s->i2c[2]->reg_data[0xe7]) ||         /* KEYP_SIR */
303
 
+            (s->i2c[2]->reg_data[0xe5] &           /* KEYP_ISR2 */
304
 
+             ~s->i2c[2]->reg_data[0xe6]))          /* KEYP_IMR2 */
305
 
+            x |= 0x02;                             /* PIH_ISR1 */
306
 
+        /* MADC */
307
 
+        if (s->i2c[2]->reg_data[0x65] ||           /* MADC_SIR */
308
 
+            (s->i2c[2]->reg_data[0x63] &           /* MADC_ISR2 */
309
 
+             ~s->i2c[2]->reg_data[0x64]))          /* MADC_IMR2 */
310
 
+            x |= 0x08;                             /* PIH_ISR3 */
311
 
+        /* PM */
312
 
+        if ((s->i2c[3]->reg_data[0x30] &           /* PWR_ISR2 */
313
 
+             ~s->i2c[3]->reg_data[0x31]))          /* PWR_IMR2 */
314
 
+            x |= 0x20;                             /* PIH_ISR5 */
315
 
+
316
 
+        s->i2c[1]->reg_data[0x82] = x;             /* PIH_ISR_P2 */
317
 
+        qemu_set_irq(s->irq2, x);
318
 
+    }
319
 
+}
320
 
+
321
 
+static uint8_t twl4030_48_read(TWL4030NodeState *s, uint8_t addr)
322
 
+{
323
 
+    TRACE("addr=0x%02x", addr);
324
 
+    switch (addr) {
325
 
+        case 0x00: /* VENDOR_ID_LO */
326
 
+        case 0x01: /* VENDOR_ID_HI */
327
 
+        case 0x02: /* PRODUCT_ID_LO */
328
 
+        case 0x03: /* PRODUCT_ID_HI */
329
 
+            return s->reg_data[addr];
330
 
+        case 0x04: /* FUNC_CTRL */
331
 
+        case 0x05: /* FUNC_CRTL_SET */
332
 
+        case 0x06: /* FUNC_CRTL_CLR */
333
 
+            return s->reg_data[0x04];
334
 
+        case 0x07: /* IFC_CTRL */
335
 
+        case 0x08: /* IFC_CRTL_SET */
336
 
+        case 0x09: /* IFC_CRTL_CLR */
337
 
+            return s->reg_data[0x07];
338
 
+        case 0x13: /* USB_INT_STS */
339
 
+        case 0x16: /* SCRATCH_REG */
340
 
+            return s->reg_data[addr];
341
 
+        case 0xac: /* POWER_CTRL */
342
 
+        case 0xad: /* POWER_SET */
343
 
+        case 0xae: /* POWER_CLR */
344
 
+            return s->reg_data[0xac];
345
 
+        case 0xbb: /* CARKIT_AND_CTRL */
346
 
+        case 0xbc: /* CARKIT_ANA_SET */
347
 
+        case 0xbd: /* CARKIT_ANA_CLR */
348
 
+            return s->reg_data[0xbb];
349
 
+        case 0xfd: /* PHY_PWR_CTRL */
350
 
+        case 0xfe: /* PHY_CLK_CTRL */
351
 
+            return s->reg_data[addr];
352
 
+        case 0xff: /* PHY_CLK_CTRL_STS */
353
 
+            if (s->reg_data[0xfd] & 1) /* PHY_PWR_CTRL */
354
 
+                return 0;
355
 
+            if (s->reg_data[0xfe] & 1) /* REQ_PHY_DPLL_CLK */
356
 
+                return 1;
357
 
+            return (s->reg_data[0x04] >> 6) & 1; /* SUSPENDM */
358
 
+        default:
359
 
+            hw_error("%s: unknown register 0x%02x", __FUNCTION__, addr);
360
 
+            break;
361
 
+    }
362
 
+    return 0;
363
 
+}
364
 
+
365
 
+static void twl4030_48_write(TWL4030NodeState *s, uint8_t addr, uint8_t value)
366
 
+{
367
 
+    TRACE("addr=0x%02x, value=0x%02x", addr, value);
368
 
+    switch (addr) {
369
 
+        case 0x04: /* FUNC_CTRL */
370
 
+            s->reg_data[0x04] = value & 0x7f;
371
 
+            break;
372
 
+        case 0x05: /* FUNC_CRTL_SET */
373
 
+            s->reg_data[0x04] = (s->reg_data[0x04] | value) & 0x7f;
374
 
+            break;
375
 
+        case 0x06: /* FUNC_CTRL_CLEAR */
376
 
+            s->reg_data[0x04] = (s->reg_data[0x04] & ~value) & 0x7f;
377
 
+            break;
378
 
+        case 0x07: /* IFC_CTRL */
379
 
+            s->reg_data[0x07] = value & 0x9e;
380
 
+            break;
381
 
+        case 0x08: /* IFC_CRTL_SET */
382
 
+            s->reg_data[0x07] = (s->reg_data[0x07] | value) & 0x9e;
383
 
+            break;
384
 
+        case 0x09: /* IFC_CRTL_CLEAR */
385
 
+            s->reg_data[0x07] = (s->reg_data[0x07] & ~value) & 0x9e;
386
 
+            break;
387
 
+        case 0x16: /* SCRATCH_REG */
388
 
+            s->reg_data[0x16] = value;
389
 
+            break;
390
 
+        case 0xa1: /* CARKIT_SM_CTRL */
391
 
+            s->reg_data[0xa1] = value & 0x3f;
392
 
+            break;
393
 
+        case 0xa2: /* CARKIT_SM_CTRL_SET */
394
 
+            s->reg_data[0xa1] = (s->reg_data[0xa1] | value) & 0x3f;
395
 
+            break;
396
 
+        case 0xa3: /* CARKIT_SM_CTRL_CLR */
397
 
+            s->reg_data[0xa1] = (s->reg_data[0xa1] & ~value) & 0x3f;
398
 
+            break;
399
 
+        case 0xac: /* POWER_CTRL */
400
 
+            s->reg_data[0xac] = value & 0x20;
401
 
+            break;
402
 
+        case 0xad: /* POWER_SET */
403
 
+            s->reg_data[0xac] = (s->reg_data[0xac] | value) & 0x20;
404
 
+            break;
405
 
+        case 0xae: /* POWER_CLEAR */
406
 
+            s->reg_data[0xac] = (s->reg_data[0xac] & ~value) & 0x20;
407
 
+            break;
408
 
+        case 0xbb: /* CARKIT_ANA_CTRL */
409
 
+            s->reg_data[0xbb] = value;
410
 
+            break;
411
 
+        case 0xbc: /* CARKIT_ANA_CTRL_SET */
412
 
+            s->reg_data[0xbb] |= value;
413
 
+            break;
414
 
+        case 0xbd: /* CARKIT_ANA_CTRL_CLR */
415
 
+            s->reg_data[0xbb] &= ~value;
416
 
+            break;
417
 
+        case 0xfd: /* PHY_PWR_CTRL */
418
 
+            s->reg_data[addr] = value & 0x1;
419
 
+            break;
420
 
+        case 0xfe: /* PHY_CLK_CTRL */
421
 
+            s->reg_data[addr] = value & 0x7;
422
 
+            break;
423
 
+        default:
424
 
+            hw_error("%s: unknown register 0x%02x", __FUNCTION__, addr);
425
 
+                       break;
426
 
+    }
427
 
+}
428
 
+
429
 
+static uint8_t twl4030_49_read(TWL4030NodeState *s, uint8_t addr)
430
 
+{
431
 
+    TRACE("addr=0x%02x", addr);
432
 
+    switch (addr) {
433
 
+        /* AUDIO_VOICE region */
434
 
+        case 0x01 ... 0x49:
435
 
+            return s->reg_data[addr];
436
 
+        /* Test region */
437
 
+        case 0x4c ... 0x60:
438
 
+            return s->reg_data[addr];
439
 
+        /* PIH region */
440
 
+        case 0x81: /* PIH_ISR_P1 */
441
 
+        case 0x82: /* PIH_ISR_P2 */
442
 
+        case 0x83: /* PIH_SIR */
443
 
+            return s->reg_data[addr];
444
 
+        /* INTBR region */
445
 
+        case 0x85 ... 0x90:
446
 
+            if (s->reg_data[0x97] != 0x49) {
447
 
+                return 0;
448
 
+            }
449
 
+            /* fallthrough */
450
 
+        case 0x91 ... 0x97:
451
 
+            return s->reg_data[addr];
452
 
+        /* GPIO region */
453
 
+        case 0x98 ... 0xc5:
454
 
+            return s->reg_data[addr];
455
 
+        default:
456
 
+            hw_error("%s: unknown register 0x%02x", __FUNCTION__, addr);
457
 
+                       break;
458
 
+    }
459
 
+    return 0;
460
 
+}
461
 
+
462
 
+static void twl4030_49_write(TWL4030NodeState *s, uint8_t addr, uint8_t value)
463
 
+{
464
 
+    TRACE("addr=0x%02x, value=0x%02x", addr, value);
465
 
+    switch (addr) {
466
 
+        /* AUDIO_VOICE region */
467
 
+        case 0x01 ... 0x49:
468
 
+            s->reg_data[addr] = value;
469
 
+            break;
470
 
+        /* Test region */
471
 
+        case 0x4c ... 0x59:
472
 
+            s->reg_data[addr] = value;
473
 
+            break;
474
 
+        case 0x5a ... 0x60:
475
 
+            /* read-only, ignore */
476
 
+            break;
477
 
+        /* PIH region */
478
 
+        case 0x81: /* PIH_ISR_P1 */
479
 
+        case 0x82: /* PIH_ISR_P2 */
480
 
+        case 0x83: /* PIH_SIR */
481
 
+            s->reg_data[addr] = value;
482
 
+            twl4030_interrupt_update(s->twl4030);
483
 
+            break;
484
 
+        /* INTBR region */
485
 
+        case 0x85 ... 0x90:
486
 
+            /* read-only, ignore */
487
 
+            break;
488
 
+        case 0x91 ... 0x97:
489
 
+            s->reg_data[addr] = value;
490
 
+            break;
491
 
+        /* GPIO region */
492
 
+        case 0x98 ... 0x9a:
493
 
+            /* read-only, ignore */
494
 
+            break;
495
 
+        case 0x9b ... 0xae:
496
 
+            s->reg_data[addr] = value;
497
 
+            break;
498
 
+        case 0xaf: /* GPIOPUPDCTR5 */
499
 
+            s->reg_data[addr] = value & 0x0f;
500
 
+            break;
501
 
+        case 0xb0 ... 0xb5:
502
 
+            s->reg_data[addr] = value;
503
 
+            break;
504
 
+           case 0xb6: /* GPIO_IMR3A */
505
 
+            s->reg_data[addr] = value & 0x03;
506
 
+            break;
507
 
+        case 0xb7 ... 0xc4:
508
 
+            s->reg_data[addr] = value;
509
 
+            break;
510
 
+           case 0xc5: /* GPIO_SIH_CTRL */
511
 
+            s->reg_data[addr] = value & 0x07;
512
 
+            break;
513
 
+        default:
514
 
+            hw_error("%s: unknown register 0x%02x", __FUNCTION__, addr);
515
 
+            break;
516
 
+    }
517
 
+}
518
 
+
519
 
+static uint8_t twl4030_4a_read(TWL4030NodeState *s, uint8_t addr)
520
 
+{
521
 
+    static const uint8_t twl5031_aciid_data[] = {
522
 
+        0x55, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
523
 
+    };
524
 
+    TRACE("addr=0x%02x", addr);
525
 
+    switch (addr) {
526
 
+        /* MADC region */
527
 
+        case 0x00 ... 0x13:
528
 
+        case 0x62:
529
 
+        case 0x64 ... 0x67:
530
 
+            return s->reg_data[addr];
531
 
+        case 0x17 ... 0x36: /* RT conversion result */
532
 
+            if (s->twl4030->madc_cb) {
533
 
+                uint16_t x = s->twl4030->madc_cb(TWL4030_ADC_RT,
534
 
+                                                 (addr - 0x17) >> 1);
535
 
+                return (addr & 1) ? (uint8_t)((x & 3) << 6)
536
 
+                                  : (uint8_t)((x >> 2) & 0xff);
537
 
+            }
538
 
+            return s->reg_data[addr];
539
 
+        case 0x37 ... 0x56: /* GP conversion result */
540
 
+            if (s->twl4030->madc_cb) {
541
 
+                uint16_t x = s->twl4030->madc_cb(TWL4030_ADC_GP,
542
 
+                                                 (addr - 0x37) >> 1);
543
 
+                return (addr & 1) ? (uint8_t)((x & 3) << 6)
544
 
+                                  : (uint8_t)((x >> 2) & 0xff);
545
 
+            }
546
 
+            return s->reg_data[addr];
547
 
+        case 0x57 ... 0x60: /* BCI conversion result */
548
 
+            if (s->twl4030->madc_cb) {
549
 
+                uint16_t x = s->twl4030->madc_cb(TWL4030_ADC_BCI,
550
 
+                                                 (addr - 0x57) >> 1);
551
 
+                return (addr & 1) ? (uint8_t)((x & 3) << 6)
552
 
+                                  : (uint8_t)((x >> 2) & 0xff);
553
 
+            }
554
 
+            return s->reg_data[addr];
555
 
+        case 0x61: /* MADC_ISR1 */
556
 
+        case 0x63: /* MADC_ISR2 */
557
 
+            {
558
 
+                uint8_t data = s->reg_data[addr];
559
 
+                if (s->reg_data[0x67] & 0x04) { /* COR */
560
 
+                    s->reg_data[addr] = 0x00;
561
 
+                    twl4030_interrupt_update(s->twl4030);
562
 
+                }
563
 
+                return data;
564
 
+            }
565
 
+        /* MAIN_CHARGE(TWL4030) / ACCESSORY(TWL5031) region */
566
 
+        case 0x74 ... 0xa9:
567
 
+            if (s->twl4030->twl5031) {
568
 
+                switch (addr) {
569
 
+                    case 0x74: /* ACIID */
570
 
+                        if (s->twl4030->twl5031_aciid >=
571
 
+                            sizeof(twl5031_aciid_data)) {
572
 
+                            s->twl4030->twl5031_aciid = 0;
573
 
+                        }
574
 
+                        return twl5031_aciid_data[s->twl4030->twl5031_aciid++];
575
 
+                    case 0x79: /* ACIIMR_LSB */
576
 
+                    case 0x7a: /* ACIIMR_MSB */
577
 
+                    case 0x7b: /* ACIIDR_LSB */
578
 
+                    case 0x7c: /* ACIIDR_MSB */
579
 
+                    case 0x80: /* AV_CTRL */
580
 
+                    case 0x82: /* BCIA_CTRL */
581
 
+                    case 0x83: /* ACCISR1 */
582
 
+                        return s->reg_data[addr];
583
 
+                    default:
584
 
+                        hw_error("%s: unknown twl5031 register 0x%02x",
585
 
+                                 __FUNCTION__, addr);
586
 
+                        break;
587
 
+                }
588
 
+            }
589
 
+            return s->reg_data[addr];
590
 
+        /* PRECHARGE region */
591
 
+        case 0xaa ... 0xb8:
592
 
+            return s->reg_data[addr];
593
 
+        /* Interrupt region */
594
 
+        case 0xb9 ... 0xc6:
595
 
+            return s->reg_data[addr];
596
 
+        /* KEYPAD region */
597
 
+        case 0xd2 ... 0xe2:
598
 
+        case 0xe4:
599
 
+        case 0xe6 ... 0xe9:
600
 
+            return s->reg_data[addr];
601
 
+        case 0xe3: /* KEYP_ISR1 */
602
 
+        case 0xe5: /* KEYP_ISR2 */
603
 
+            {
604
 
+                uint8_t data = s->reg_data[addr];
605
 
+                if (s->reg_data[0xe9] & 0x04) { /* COR */
606
 
+                    s->reg_data[addr] = 0x00;
607
 
+                    twl4030_interrupt_update(s->twl4030);
608
 
+                }
609
 
+                return data;
610
 
+            }
611
 
+        /* LED region */
612
 
+        case 0xee: /* LEDEN */
613
 
+            return s->reg_data[addr];
614
 
+        /* PWMA region */
615
 
+        case 0xef: /* PWMAON */
616
 
+        case 0xf0: /* PWMAOFF */
617
 
+            return s->reg_data[addr];
618
 
+        /* PWMB region */
619
 
+        case 0xf1: /* PWMBON */
620
 
+        case 0xf2: /* PWMBOFF */
621
 
+            return s->reg_data[addr];
622
 
+        /* PWM0 region */
623
 
+        case 0xf8: /* PWM0ON */
624
 
+        case 0xf9: /* PWM0OFF */
625
 
+            return s->reg_data[addr];
626
 
+        /* PWM1 region */
627
 
+        case 0xfb: /* PWM1ON */
628
 
+        case 0xfc: /* PWM1OFF */
629
 
+            return s->reg_data[addr];
630
 
+        default:
631
 
+               hw_error("%s: unknown register 0x%02x", __FUNCTION__, addr);
632
 
+            break;
633
 
+    }
634
 
+    return 0;
635
 
+}
636
 
+
637
 
+static void twl4030_4a_write(TWL4030NodeState *s, uint8_t addr, uint8_t value)
638
 
+{
639
 
+    TRACE("addr=0x%02x, value=0x%02x", addr, value);
640
 
+    switch (addr) {
641
 
+        /* MADC region */
642
 
+
643
 
+        case 0x00: /* CTRL1 */
644
 
+        case 0x01: /* CTRL2 */
645
 
+            s->reg_data[addr] = value;
646
 
+            break;
647
 
+        case 0x06: /* SW1SELECT_LSB */
648
 
+        case 0x07: /* SW1SELECT_MSB */
649
 
+        case 0x08: /* SW1AVERAGE_LSB */
650
 
+        case 0x09: /* SW1AVERAGE_MSB */
651
 
+        case 0x0a: /* SW2SELECT_LSB */
652
 
+        case 0x0b: /* SW2SELECT_MSB */
653
 
+        case 0x0c: /* SW2AVERAGE_LSB */
654
 
+        case 0x0d: /* SW2AVERAGE_MSB */
655
 
+            s->reg_data[addr] = value;
656
 
+            break;
657
 
+        case 0x12: /* CTRL_SW1 */
658
 
+        case 0x13: /* CTRL_SW2 */
659
 
+            /* always set all conversions ready, not busy */
660
 
+            s->reg_data[addr] = 0x3e;
661
 
+            if (value & 0x20) { /* SW1/SW2 */
662
 
+                s->reg_data[0x61] |= 2 << (addr - 0x12); /* SW1_ISR/SW2_ISR */
663
 
+                s->reg_data[0x63] |= 2 << (addr - 0x12); /* SW1_ISR/SW2_ISR */
664
 
+                twl4030_interrupt_update(s->twl4030);
665
 
+            }
666
 
+            break;
667
 
+        case 0x17 ... 0x60: /* conversion results */
668
 
+            /* read-only, ignore */
669
 
+            break;
670
 
+        case 0x61: /* MADC_ISR1 */
671
 
+        case 0x63: /* MADC_ISR2 */
672
 
+            if (!(s->reg_data[0x67] & 0x04)) { /* COR */
673
 
+                s->reg_data[addr] &= ~(value & 0x0f);
674
 
+                twl4030_interrupt_update(s->twl4030);
675
 
+            }
676
 
+            break;
677
 
+        case 0x62: /* MADC_IMR1 */
678
 
+        case 0x64: /* MADC_IMR2 */
679
 
+        case 0x65: /* MADC_SIR */
680
 
+            s->reg_data[addr] = value & 0x0f;
681
 
+            twl4030_interrupt_update(s->twl4030);
682
 
+            break;
683
 
+        case 0x66: /* MADC_EDR */
684
 
+            s->reg_data[addr] = value;
685
 
+            break;
686
 
+        case 0x67: /* MADC_SIH_CTRL */
687
 
+            s->reg_data[addr] = value & 0x07;
688
 
+            break;
689
 
+
690
 
+        /* MAIN_CHARGE(TWL4030) / ACCESSORY(TWL5031) region */
691
 
+
692
 
+        case 0x74: /* BCIMDEN(TWL4030) / ACIID(TWL5031) */
693
 
+            if (s->twl4030->twl5031) {
694
 
+                s->twl4030->twl5031_aciid = 0;
695
 
+            } else {
696
 
+                /* read-only */
697
 
+            }
698
 
+            break;
699
 
+        case 0x75: /* BCIMDKEY(TWL4030) / ACICOMR_LSB(TWL5031) */
700
 
+            s->reg_data[addr] = value;
701
 
+            if (!s->twl4030->twl5031) {
702
 
+                switch (value) {
703
 
+                    case 0x25: s->reg_data[0x74] = 0x12; break;
704
 
+                    case 0x26: s->reg_data[0x74] = 0x11; break;
705
 
+                    case 0x27: s->reg_data[0x74] = 0x0a; break;
706
 
+                    case 0x28: s->reg_data[0x74] = 0x06; break;
707
 
+                    case 0x29: s->reg_data[0x74] = 0x05; break;
708
 
+                    default: s->reg_data[0x74] = 0; break;
709
 
+                }
710
 
+            }
711
 
+            break;
712
 
+        case 0x76 ... 0x84:
713
 
+            if (s->twl4030->twl5031) {
714
 
+                switch (addr) {
715
 
+                    case 0x79: /* ACIIMR_LSB */
716
 
+                        s->reg_data[addr] = value;
717
 
+                        twl4030_interrupt_update(s->twl4030);
718
 
+                        break;
719
 
+                    case 0x7a: /* ACIIMR_MSB */
720
 
+                        s->reg_data[addr] = value & 0x01;
721
 
+                        twl4030_interrupt_update(s->twl4030);
722
 
+                        break;
723
 
+                    case 0x7b: /* ACIIDR_LSB */
724
 
+                        s->reg_data[addr] &= ~value;
725
 
+                        twl4030_interrupt_update(s->twl4030);
726
 
+                        break;
727
 
+                    case 0x7c: /* ACIIDR_MSB */
728
 
+                        s->reg_data[addr] &= ~(value & 0x01);
729
 
+                        twl4030_interrupt_update(s->twl4030);
730
 
+                        break;
731
 
+                    case 0x7f: /* ECI_DBI_CTRL */
732
 
+                        s->reg_data[addr] = value;
733
 
+                        twl4030_interrupt_update(s->twl4030);
734
 
+                        break;
735
 
+                    case 0x80: /* ACI_AV_CTRL */
736
 
+                        s->reg_data[addr] = (s->reg_data[addr] & 0x18) |
737
 
+                                            (value & ~0x18);
738
 
+                        twl4030_interrupt_update(s->twl4030);
739
 
+                        break;
740
 
+                    case 0x82: /* BCIA_CTRL */
741
 
+                        s->reg_data[addr] = value & 0x07;
742
 
+                        break;
743
 
+                    case 0x83: /* ACCISR1 */
744
 
+                        s->reg_data[addr] &= ~(value & 0x03);
745
 
+                        twl4030_interrupt_update(s->twl4030);
746
 
+                        break;
747
 
+                    case 0x84: /* ACCIMR1 */
748
 
+                        s->reg_data[addr] = value & 0x03;
749
 
+                        twl4030_interrupt_update(s->twl4030);
750
 
+                        break;
751
 
+                    default:
752
 
+                        hw_error("%s: unknown twl5031 register 0x%02x",
753
 
+                                 __FUNCTION__, addr);
754
 
+                        break;
755
 
+                }
756
 
+            } else {
757
 
+                /* read-only registers */
758
 
+            }
759
 
+            break;
760
 
+        case 0x97: /* BCICTL1 */
761
 
+            if (!s->twl4030->twl5031) {
762
 
+                s->reg_data[addr] = value;
763
 
+            } else {
764
 
+                hw_error("%s: unknown twl5031 register 0x%02x",
765
 
+                         __FUNCTION__, addr);
766
 
+            }
767
 
+            break;
768
 
+
769
 
+        /* PRECHARGE region */
770
 
+
771
 
+        case 0xaa ... 0xb8: /* FIXME: unknown registers */
772
 
+            s->reg_data[addr] = value;
773
 
+            break;
774
 
+
775
 
+        /* Interrupt region */
776
 
+
777
 
+        case 0xb9: /* BCIISR1A */
778
 
+            s->reg_data[addr] &= ~value;
779
 
+            break;
780
 
+        case 0xba: /* BCIISR2A */
781
 
+            s->reg_data[addr] &= ~(value & 0x0f);
782
 
+            break;
783
 
+        case 0xbb: /* BCIIMR1A */
784
 
+            s->reg_data[addr] = value;
785
 
+            break;
786
 
+        case 0xbc: /* BCIIMR2A */
787
 
+            s->reg_data[addr] = value & 0x0f;
788
 
+            break;
789
 
+        case 0xc6: /* BCISIHCTRL */
790
 
+            s->reg_data[addr] = value & 0x07;
791
 
+            break;
792
 
+
793
 
+        /* KEYPAD region */
794
 
+
795
 
+        case 0xd2: /* KEYP_CTRL_REG */
796
 
+            s->reg_data[addr] = value & 0x7f;
797
 
+            break;
798
 
+        case 0xd3: /* KEYP_DEB_REG */
799
 
+            s->reg_data[addr] = value & 0x3f;
800
 
+            break;
801
 
+        case 0xd5: /* LK_PTV_REG */
802
 
+            s->reg_data[addr] = value & 0xef;
803
 
+            break;
804
 
+        case 0xda: /* KEYP_SMS */
805
 
+            s->reg_data[addr] = (s->reg_data[addr] & ~0x30) | (value & 0x30);
806
 
+            twl4030_interrupt_update(s->twl4030);
807
 
+            break;
808
 
+        case 0xe3: /* KEYP_ISR1 */
809
 
+        case 0xe5: /* KEYP_ISR2 */
810
 
+            if (!(s->reg_data[0xe9] & 0x04)) { /* COR */
811
 
+                s->reg_data[addr] &= ~value;
812
 
+                twl4030_interrupt_update(s->twl4030);
813
 
+            }
814
 
+            break;
815
 
+        case 0xe4: /* KEYP_IMR1 */
816
 
+        case 0xe6: /* KEYP_IMR2 */
817
 
+        case 0xe7: /* KEYP_SIR */
818
 
+            s->reg_data[addr] = value & 0x0f;
819
 
+            twl4030_interrupt_update(s->twl4030);
820
 
+            break;
821
 
+        case 0xe9: /* KEYP_SIH_CTRL */
822
 
+            s->reg_data[addr] = value & 0x07;
823
 
+            break;
824
 
+        case 0xd4: /* LONG_KEY_REG1 */
825
 
+        case 0xd6: /* TIME_OUT_REG1 */
826
 
+        case 0xd7: /* TIME_OUT_REG2 */
827
 
+        case 0xd8: /* KBC_REG */
828
 
+        case 0xe8: /* KEYP_EDR */
829
 
+            s->reg_data[addr] = value;
830
 
+            break;
831
 
+        case 0xd9: /* KBR_REG */
832
 
+        case 0xdb ... 0xe2: /* FULL_CODE_xx_yy */
833
 
+            /* read-only, ignore */
834
 
+            break;
835
 
+
836
 
+        /* LED region */
837
 
+
838
 
+        case 0xee: /* LEDEN */
839
 
+            s->reg_data[addr] = value;
840
 
+            TRACE("LEDA power=%s/enable=%s, LEDB power=%s/enable=%s",
841
 
+                    value & 0x10 ? "on" : "off", value & 0x01 ? "yes" : "no",
842
 
+                    value & 0x20 ? "on" : "off", value & 0x02 ? "yes" : "no");
843
 
+            break;
844
 
+
845
 
+        /* PWMA/B/0/1 regions */
846
 
+
847
 
+        case 0xef: /* PWMAON */
848
 
+        case 0xf1: /* PWMBON */
849
 
+        case 0xf8: /* PWM0ON */
850
 
+        case 0xfb: /* PWM1ON */
851
 
+            s->reg_data[addr] = value;
852
 
+            break;
853
 
+        case 0xf0: /* PWMAOFF */
854
 
+        case 0xf2: /* PWMBOFF */
855
 
+        case 0xf9: /* PWM0OFF */
856
 
+        case 0xfc: /* PWM1OFF */
857
 
+            s->reg_data[addr] = value & 0x7f;
858
 
+            break;
859
 
+
860
 
+        default:
861
 
+               hw_error("%s: unknown register 0x%02x", __FUNCTION__, addr);
862
 
+            break;
863
 
+    }
864
 
+}
865
 
+
866
 
+static inline struct tm *twl4030_gettime(void)
867
 
+{
868
 
+    time_t epoch_time = time(NULL);
869
 
+    return gmtime(&epoch_time);//localtime(&epoch_time);
870
 
+}
871
 
+
872
 
+static uint8_t twl4030_4b_read(TWL4030NodeState *s, uint8_t addr)
873
 
+{
874
 
+    uint8_t x;
875
 
+       TRACE("addr=0x%02x value=0x%02x", addr, s->reg_data[addr]);
876
 
+    switch (addr) {
877
 
+        /* SECURED_REG region */
878
 
+        case 0x00 ... 0x13:
879
 
+            return s->reg_data[addr];
880
 
+        /* BACKUP_REG region */
881
 
+        case 0x14 ... 0x1b:
882
 
+            return s->reg_data[addr];
883
 
+        /* RTC region */
884
 
+        case 0x1c: /* SECONDS_REG */
885
 
+            x = s->reg_data[addr];
886
 
+            if (x == 0xff) {
887
 
+                struct tm *t = twl4030_gettime();
888
 
+                x = ((t->tm_sec / 10) << 4) | (t->tm_sec % 10);
889
 
+            } else {
890
 
+                s->reg_data[addr] = 0xff;
891
 
+            }
892
 
+            TRACE_RTC("SECONDS_REG returns 0x%02x", x);
893
 
+            return x;
894
 
+        case 0x1d: /* MINUTES_REG */
895
 
+            x = s->reg_data[addr];
896
 
+            if (x == 0xff) {
897
 
+                struct tm *t = twl4030_gettime();
898
 
+                x = ((t->tm_min / 10) << 4) | (t->tm_min % 10);
899
 
+            } else {
900
 
+                s->reg_data[addr] = 0xff;
901
 
+            }
902
 
+            TRACE_RTC("MINUTES_REG returns 0x%02x", x);
903
 
+            return x;
904
 
+        case 0x1e: /* HOURS_REG */
905
 
+            x = s->reg_data[addr];
906
 
+            if (x == 0xff) {
907
 
+                struct tm *t = twl4030_gettime();
908
 
+                if (s->reg_data[0x29] & 0x08) { /* MODE_12_24 */
909
 
+                    int h12 = t->tm_hour;
910
 
+                    if (h12 > 11) {
911
 
+                        h12 -= 12;
912
 
+                        x = ((h12 / 10) << 4) | (h12 % 10) | 0x80; /* PM_NAM */
913
 
+                    } else {
914
 
+                        x = ((h12 / 10) << 4) | (h12 % 10);
915
 
+                    }
916
 
+                } else {
917
 
+                    x = ((t->tm_hour / 10) << 4) | (t->tm_hour % 10);
918
 
+                }
919
 
+            } else {
920
 
+                s->reg_data[addr] = 0xff;
921
 
+            }
922
 
+            TRACE_RTC("HOURS_REG returns 0x%02x", x);
923
 
+            return x;
924
 
+        case 0x1f: /* DAYS_REG */
925
 
+            x = s->reg_data[addr];
926
 
+            if (x == 0xff) {
927
 
+                struct tm *t = twl4030_gettime();
928
 
+                x = ((t->tm_mday / 10) << 4) | (t->tm_mday % 10);
929
 
+            } else {
930
 
+                s->reg_data[addr] = 0xff;
931
 
+            }
932
 
+            TRACE_RTC("DAYS_REG returns 0x%02x", x);
933
 
+            return x;
934
 
+        case 0x20: /* MONTHS_REG */
935
 
+            x = s->reg_data[addr];
936
 
+            if (x == 0xff) {
937
 
+                struct tm *t = twl4030_gettime();
938
 
+                x = (((t->tm_mon + 1) / 10) << 4) | ((t->tm_mon + 1) % 10);
939
 
+            } else {
940
 
+                s->reg_data[addr] = 0xff;
941
 
+            }
942
 
+            TRACE_RTC("MONTHS_REG returns 0x%02x", x);
943
 
+            return x;
944
 
+        case 0x21: /* YEARS_REG */
945
 
+            x = s->reg_data[addr];
946
 
+            if (x == 0xff) {
947
 
+                struct tm *t = twl4030_gettime();
948
 
+                x = (((t->tm_year % 100) / 10) << 4) | (t->tm_year % 10);
949
 
+            } else {
950
 
+                s->reg_data[addr] = 0xff;
951
 
+            }
952
 
+            TRACE_RTC("YEARS_REG returns 0x%02x", x);
953
 
+            return x;
954
 
+        case 0x22: /* WEEKS_REG */
955
 
+            x = s->reg_data[addr];
956
 
+            if (x == 0xff) {
957
 
+                struct tm *t = twl4030_gettime();
958
 
+                x = t->tm_wday;
959
 
+            } else {
960
 
+                s->reg_data[addr] = 0xff;
961
 
+            }
962
 
+            TRACE_RTC("WEEKS_REG returns 0x%02x", x);
963
 
+            return x;
964
 
+        case 0x23: /* ALARM_SECONDS_REG */
965
 
+            x = s->reg_data[addr];
966
 
+            TRACE_RTC("ALARM_SECONDS_REG returns 0x%02x", x);
967
 
+            return x;
968
 
+        case 0x24: /* ALARM_MINUTES_REG */
969
 
+            x = s->reg_data[addr];
970
 
+            TRACE_RTC("ALARM_MINUTES_REG returns 0x%02x", x);
971
 
+            return x;
972
 
+        case 0x25: /* ALARM_HOURS_REG */
973
 
+            x = s->reg_data[addr];
974
 
+            TRACE_RTC("ALARM_HOURS_REG returns 0x%02x", x);
975
 
+            return x;
976
 
+        case 0x26: /* ALARM_DAYS_REG */
977
 
+            x = s->reg_data[addr];
978
 
+            TRACE_RTC("ALARM_DAYS_REG returns 0x%02x", x);
979
 
+            return x;
980
 
+        case 0x27: /* ALARM_MONTHS_REG */
981
 
+            x = s->reg_data[addr];
982
 
+            TRACE_RTC("ALARM_MONTHS_REG returns 0x%02x", x);
983
 
+            return x;
984
 
+        case 0x28: /* ALARM_YEARS_REG */
985
 
+            x = s->reg_data[addr];
986
 
+            TRACE_RTC("ALARM_YEARS_REG returns 0x%02x", x);
987
 
+            return x;
988
 
+        case 0x29: /* RTC_CTRL_REG */
989
 
+            x = s->reg_data[addr];
990
 
+            TRACE_RTC("RTC_CTRL_REG returns 0x%02x", x);
991
 
+            return x;
992
 
+        case 0x2a: /* RTC_STATUS_REG */
993
 
+            x = s->reg_data[addr];
994
 
+            TRACE_RTC("RTC_STATUS_REG returns 0x%02x", x);
995
 
+            return x;
996
 
+        case 0x2b: /* RTC_INTERRUPTS_REG */
997
 
+            x = s->reg_data[addr];
998
 
+            TRACE_RTC("RTC_INTERRUPTS_REG returns 0x%02x", x);
999
 
+            return x;
1000
 
+        case 0x2c: /* RTC_COMP_LSB_REG */
1001
 
+            x = s->reg_data[addr];
1002
 
+            TRACE_RTC("RTC_COMP_LSB_REG returns 0x%02x", x);
1003
 
+            return x;
1004
 
+        case 0x2d: /* RTC_COMP_MSB_REG */
1005
 
+            x = s->reg_data[addr];
1006
 
+            TRACE_RTC("RTC_CTRL_REG returns 0x%02x", x);
1007
 
+            return x;
1008
 
+        /* INT region */
1009
 
+        case 0x2f:
1010
 
+        case 0x31 ... 0x35:
1011
 
+            return s->reg_data[addr];
1012
 
+        case 0x2e: /* PWR_ISR1 */
1013
 
+        case 0x30: /* PWR_ISR2 */
1014
 
+            {
1015
 
+                uint8_t data = s->reg_data[addr];
1016
 
+                if (s->reg_data[0x35] & 0x04) { /* COR */
1017
 
+                    s->reg_data[addr] = 0x00;
1018
 
+                    twl4030_interrupt_update(s->twl4030);
1019
 
+                }
1020
 
+                return data;
1021
 
+            }
1022
 
+        /* PM_MASTER region */
1023
 
+        case 0x36 ... 0x44:
1024
 
+            return s->reg_data[addr];
1025
 
+        case 0x45: /* STS_HW_CONDITIONS */
1026
 
+            /* FIXME: force USB always connected, no VBUS (host usb) */
1027
 
+            return (s->reg_data[addr] & ~0x80) | 0x04;
1028
 
+        case 0x46 ... 0x5a:
1029
 
+            return s->reg_data[addr];
1030
 
+        /* PM_RECEIVER region */
1031
 
+        case 0x5b ... 0xf1:
1032
 
+            return s->reg_data[addr];
1033
 
+        default:
1034
 
+               hw_error("%s: unknown register 0x%02x", __FUNCTION__, addr);
1035
 
+            break;
1036
 
+    }
1037
 
+    return 0;
1038
 
+}
1039
 
+
1040
 
+static void twl4030_setup_alarm(TWL4030NodeState *s)
1041
 
+{
1042
 
+    if (s->reg_data[0x2b] & 0x08) { /* IT_ALARM */
1043
 
+        struct tm a = {
1044
 
+            .tm_sec = ((s->reg_data[0x23] >> 4) & 7) * 10
1045
 
+                      + (s->reg_data[0x23] & 0x0f),
1046
 
+            .tm_min = ((s->reg_data[0x24] >> 4) & 7) * 10
1047
 
+                      + (s->reg_data[0x24] & 0x0f),
1048
 
+            .tm_hour = ((s->reg_data[0x29] & 0x08)
1049
 
+                        ? (s->reg_data[0x25] >> 7) * 12 : 0)
1050
 
+                       + ((s->reg_data[0x25] >> 4) & 3) * 10
1051
 
+                       + (s->reg_data[0x25] & 0x0f),
1052
 
+            .tm_mday = ((s->reg_data[0x26] >> 4) & 3) * 10
1053
 
+                       + (s->reg_data[0x26] & 0x0f),
1054
 
+            .tm_mon = ((s->reg_data[0x27] >> 4) & 1) * 10
1055
 
+                      + (s->reg_data[0x27] & 0x0f)
1056
 
+                      - 1,
1057
 
+            .tm_year = (s->reg_data[0x28] >> 4) * 10
1058
 
+                       + (s->reg_data[0x28] & 0x0f)
1059
 
+                       + 100,
1060
 
+            .tm_isdst = -1,
1061
 
+        };
1062
 
+        TRACE_RTC("enable alarm on %02d/%02d/%04d at %02d:%02d:%02d (UTC)",
1063
 
+                  a.tm_mday, a.tm_mon + 1, a.tm_year + 1900,
1064
 
+                  a.tm_hour, a.tm_min, a.tm_sec);
1065
 
+        time_t at = mktime(&a); /* alarm time interpreted in local time */
1066
 
+        if (at < 0) {
1067
 
+            TRACE_RTC("unable to parse alarm calendar time");
1068
 
+        } else {
1069
 
+            /* fix alarm time to utc */
1070
 
+            struct timezone tz;
1071
 
+            struct timeval tv;
1072
 
+            if (!gettimeofday(&tv, &tz)) {
1073
 
+                at -= tz.tz_minuteswest * 60;
1074
 
+            }
1075
 
+            int64_t delta = (int64_t)difftime(at, time(NULL));
1076
 
+            if (delta <= 0) {
1077
 
+                TRACE_RTC("alarm is in the past");
1078
 
+            } else {
1079
 
+                TRACE_RTC("new alarm interrupt in %" PRId64 " seconds", delta);
1080
 
+                timer_mod(s->twl4030->alarm_timer,
1081
 
+                          qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
1082
 
+                          + get_ticks_per_sec() * delta);
1083
 
+            }
1084
 
+        }
1085
 
+    } else {
1086
 
+        timer_del(s->twl4030->alarm_timer);
1087
 
+    }
1088
 
+}
1089
 
+
1090
 
+static void twl4030_setup_periodic(TWL4030NodeState *s)
1091
 
+{
1092
 
+    if (s->reg_data[0x2b] & 0x04) { /* IT_TIMER */
1093
 
+        uint32_t t = 0;
1094
 
+        switch (s->reg_data[0x2b] & 3) {
1095
 
+            case 0: t = 1; break;
1096
 
+            case 1: t = 60; break;
1097
 
+            case 2: t = 60 * 60; break;
1098
 
+            case 3: t = 24 * 60 * 60; break;
1099
 
+        }
1100
 
+        TRACE_RTC("new periodic interrupt in %u seconds", t);
1101
 
+        timer_mod(s->twl4030->periodic_timer,
1102
 
+                  qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
1103
 
+                  + get_ticks_per_sec() * t);
1104
 
+    } else {
1105
 
+        timer_del(s->twl4030->periodic_timer);
1106
 
+    }
1107
 
+}
1108
 
+
1109
 
+static void twl4030_alarm(void *opaque)
1110
 
+{
1111
 
+    TWL4030State *s = opaque;
1112
 
+    s->i2c[3]->reg_data[0x2a] |= 0x40;      /* RTC_STATUS_REG |= ALARM */
1113
 
+    if (s->i2c[3]->reg_data[0x33] & 0xc0) { /* RTC_IT_RISING|RTC_IT_FALLING */
1114
 
+        TRACE_RTC("triggering RTC alarm interrupt");
1115
 
+        s->i2c[3]->reg_data[0x2e] |= 0x08;  /* PWR_ISR1 |= RTC_IT */
1116
 
+        s->i2c[3]->reg_data[0x30] |= 0x08;  /* PWR_ISR2 |= RTC_IT */
1117
 
+        twl4030_interrupt_update(s);
1118
 
+    }
1119
 
+    timer_del(s->alarm_timer);
1120
 
+}
1121
 
+
1122
 
+static void twl4030_periodic(void *opaque)
1123
 
+{
1124
 
+    TWL4030State *s = opaque;
1125
 
+    uint8_t b = 0x04 << (s->i2c[3]->reg_data[0x2b] & 3);
1126
 
+    s->i2c[3]->reg_data[0x2a] |= b;         /* TODO: when are these cleared? */
1127
 
+    if (s->i2c[3]->reg_data[0x33] & 0xc0) { /* RTC_IT_RISING|RTC_IT_FALLING */
1128
 
+        TRACE_RTC("triggering RTC periodic interrupt");
1129
 
+        s->i2c[3]->reg_data[0x2e] |= 0x08;  /* PWR_ISR1 |= RTC_IT */
1130
 
+        s->i2c[3]->reg_data[0x30] |= 0x08;  /* PWR_ISR2 |= RTC_IT */
1131
 
+        twl4030_interrupt_update(s);
1132
 
+    }
1133
 
+    twl4030_setup_periodic(s->i2c[3]);
1134
 
+}
1135
 
+
1136
 
+static void twl4030_4b_write(TWL4030NodeState *s, uint8_t addr, uint8_t value)
1137
 
+{
1138
 
+    uint8_t seq_addr, seq_sub;
1139
 
+
1140
 
+       TRACE("addr=0x%02x, value=0x%02x", addr, value);
1141
 
+    switch (addr) {
1142
 
+        case 0x1c: /* SECONDS_REG */
1143
 
+            TRACE_RTC("SECONDS_REG = 0x%02x", value);
1144
 
+            s->reg_data[addr] = value & 0x7f;
1145
 
+            break;
1146
 
+        case 0x1d: /* MINUTES_REG */
1147
 
+            TRACE_RTC("MINUTES_REG = 0x%02x", value);
1148
 
+            s->reg_data[addr] = value & 0x7f;
1149
 
+            break;
1150
 
+        case 0x1e: /* HOURS_REG */
1151
 
+            TRACE_RTC("HOURS_REG = 0x%02x", value);
1152
 
+            s->reg_data[addr] = value & 0xbf;
1153
 
+            break;
1154
 
+        case 0x1f: /* DAYS_REG */
1155
 
+            TRACE_RTC("DAYS_REG = 0x%02x", value);
1156
 
+            s->reg_data[addr] = value & 0x3f;
1157
 
+            break;
1158
 
+        case 0x20: /* MONTHS_REG */
1159
 
+            TRACE_RTC("MONTHS_REG = 0x%02x", value);
1160
 
+            s->reg_data[addr] = value & 0x1f;
1161
 
+            break;
1162
 
+        case 0x21: /* YEARS_REG */
1163
 
+            TRACE_RTC("YEARS_REG = 0x%02x", value);
1164
 
+            s->reg_data[addr] = value;
1165
 
+            break;
1166
 
+        case 0x22: /* WEEKS_REG */
1167
 
+            TRACE_RTC("WEEKS_REG = 0x%02x", value);
1168
 
+            s->reg_data[addr] = value & 0x07;
1169
 
+            break;
1170
 
+        case 0x23: /* ALARM_SECONDS_REG */
1171
 
+            TRACE_RTC("ALARM_SECONDS_REG = 0x%02x", value);
1172
 
+            s->reg_data[addr] = value & 0x7f;
1173
 
+            twl4030_setup_alarm(s);
1174
 
+            break;
1175
 
+        case 0x24: /* ALARM_MINUTES_REG */
1176
 
+            TRACE_RTC("ALARM_MINUTES_REG = 0x%02x", value);
1177
 
+            s->reg_data[addr] = value & 0x7f;
1178
 
+            twl4030_setup_alarm(s);
1179
 
+            break;
1180
 
+        case 0x25: /* ALARM_HOURS_REG */
1181
 
+            TRACE_RTC("ALARM_HOURS_REG = 0x%02x", value);
1182
 
+            s->reg_data[addr] = value & 0xbf;
1183
 
+            twl4030_setup_alarm(s);
1184
 
+            break;
1185
 
+        case 0x26: /* ALARM_DAYS_REG */
1186
 
+            TRACE_RTC("ALARM_DAYS_REG = 0x%02x", value);
1187
 
+            s->reg_data[addr] = value & 0x3f;
1188
 
+            twl4030_setup_alarm(s);
1189
 
+            break;
1190
 
+        case 0x27: /* ALARM_MONTHS_REG */
1191
 
+            TRACE_RTC("ALARM_MONTHS_REG = 0x%02x", value);
1192
 
+            s->reg_data[addr] = value & 0x1f;
1193
 
+            twl4030_setup_alarm(s);
1194
 
+            break;
1195
 
+        case 0x28: /* ALARM_YEARS_REG */
1196
 
+            TRACE_RTC("ALARM_YEARS_REG = 0x%02x", value);
1197
 
+            s->reg_data[addr] = value;
1198
 
+            twl4030_setup_alarm(s);
1199
 
+            break;
1200
 
+        case 0x29: /* RTC_CTRL_REG */
1201
 
+            TRACE_RTC("RTC_CTRL_REG = 0x%02x", value);
1202
 
+            s->reg_data[addr] = value & 0x3f;
1203
 
+            s->reg_data[0x2a] = (s->reg_data[0x2a] & ~0x02) |
1204
 
+                                ((value & 0x01) << 1);
1205
 
+            if (value & 0x40) { /* GET_TIME */
1206
 
+                struct tm *t = twl4030_gettime();
1207
 
+                s->reg_data[0x1c] = ((t->tm_sec / 10) << 4) | (t->tm_sec % 10);
1208
 
+                s->reg_data[0x1d] = ((t->tm_min / 10) << 4) | (t->tm_min % 10);
1209
 
+                if (value & 0x08) { /* MODE_12_24 */
1210
 
+                    int h12 = t->tm_hour;
1211
 
+                    /* TODO: should we report hours 0-11 or 1-12? */
1212
 
+                    if (h12 > 11) {
1213
 
+                        h12 -= 12;
1214
 
+                        s->reg_data[0x1e] = ((h12 / 10) << 4) | (h12 % 10) |
1215
 
+                                            0x80; /* PM_NAM */
1216
 
+                    } else {
1217
 
+                        s->reg_data[0x1e] = ((h12 / 10) << 4) | (h12 % 10);
1218
 
+                    }
1219
 
+                } else {
1220
 
+                    s->reg_data[0x1e] = ((t->tm_hour / 10) << 4) |
1221
 
+                                        (t->tm_hour % 10);
1222
 
+                }
1223
 
+                s->reg_data[0x1f] = ((t->tm_mday / 10) << 4) |
1224
 
+                                    (t->tm_mday % 10);
1225
 
+                s->reg_data[0x20] = (((t->tm_mon + 1) / 10) << 4) |
1226
 
+                                    ((t->tm_mon + 1) % 10);
1227
 
+                s->reg_data[0x21] = (((t->tm_year % 100) / 10) << 4) |
1228
 
+                                    (t->tm_year % 10);
1229
 
+                s->reg_data[0x22] = t->tm_wday;
1230
 
+            }
1231
 
+            /* TODO: support bits 1, 2, 4 and 5 */
1232
 
+            break;
1233
 
+        case 0x2a: /* RTC_STATUS_REG */
1234
 
+            TRACE_RTC("RTC_STATUS_REG = 0x%02x", value);
1235
 
+            s->reg_data[addr] &= ~(value & 0xc0);
1236
 
+            break;
1237
 
+        case 0x2b: /* RTC_INTERRUPTS_REG */
1238
 
+            TRACE_RTC("RTC_INTERRUPTS_REG = 0x%02x", value);
1239
 
+            {
1240
 
+                uint8_t change = s->reg_data[addr] ^ value;
1241
 
+                s->reg_data[addr] = value & 0x0f;
1242
 
+                if (change & 0x08) { /* IT_ALARM */
1243
 
+                    twl4030_setup_alarm(s);
1244
 
+                }
1245
 
+                if (change & 0x04) { /* IT_TIMER */
1246
 
+                    twl4030_setup_periodic(s);
1247
 
+                }
1248
 
+            }
1249
 
+            break;
1250
 
+        case 0x2c: /* RTC_COMP_LSB_REG */
1251
 
+        case 0x2d: /* RTC_COMP_MSB_REG */
1252
 
+            TRACE_RTC("RTC_COMP_%s_REG = 0x%02x",
1253
 
+                      (addr == 0x2c) ? "LSB" : "MSB", value);
1254
 
+            s->reg_data[addr] = value;
1255
 
+            break;
1256
 
+        case 0x2e: /* PWR_ISR1 */
1257
 
+        case 0x30: /* PWR_ISR2 */
1258
 
+            if (!(s->reg_data[0x35] & 0x04)) { /* COR */
1259
 
+                s->reg_data[addr] &= ~value;
1260
 
+                twl4030_interrupt_update(s->twl4030);
1261
 
+            }
1262
 
+            break;
1263
 
+        case 0x2f: /* PWR_IMR1 */
1264
 
+        case 0x31: /* PWR_IMR2 */
1265
 
+            s->reg_data[addr] = value;
1266
 
+            twl4030_interrupt_update(s->twl4030);
1267
 
+            break;
1268
 
+        case 0x33: /* PWR_EDR1 */
1269
 
+        case 0x34: /* PWR_EDR2 */
1270
 
+            s->reg_data[addr] = value;
1271
 
+            break;
1272
 
+        case 0x35: /* PWR_SIH_CTRL */
1273
 
+            s->reg_data[addr] = value & 0x07;
1274
 
+            break;
1275
 
+        case 0x36: /* CFG_P1_TRANSITION */
1276
 
+        case 0x37: /* CFG_P2_TRANSITION */
1277
 
+        case 0x38: /* CFG_P3_TRANSITION */
1278
 
+            if (s->twl4030->key_cfg)
1279
 
+                s->reg_data[addr] = (s->reg_data[addr] & 0x40) | (value & 0xbf);
1280
 
+            break;
1281
 
+        case 0x39: /* CFG_P123_TRANSITION */
1282
 
+            if (s->twl4030->key_cfg)
1283
 
+                s->reg_data[addr] = value;
1284
 
+            break;
1285
 
+        case 0x3a: /* STS_BOOT */
1286
 
+            s->reg_data[addr] = value;
1287
 
+            break;
1288
 
+        case 0x3b: /* CFG_BOOT */
1289
 
+            if (s->twl4030->key_cfg)
1290
 
+                s->reg_data[addr] = (s->reg_data[addr] & 0x70) | (value & 0x8f);
1291
 
+            break;
1292
 
+        case 0x3c: /* SHUNDAN */
1293
 
+            s->reg_data[addr] = value & 0x3f;
1294
 
+            break;
1295
 
+        case 0x3d: /* BOOT_BCI */
1296
 
+            s->reg_data[addr] = (s->reg_data[addr] & 0x20) | (value & 0x17);
1297
 
+            break;
1298
 
+        case 0x3e: /* CFG_PWRANA1 */
1299
 
+            if (s->twl4030->key_tst)
1300
 
+                s->reg_data[addr] = value & 0x7f;
1301
 
+            break;
1302
 
+        case 0x3f: /* CFG_PWRANA2 */
1303
 
+            if (s->twl4030->key_tst)
1304
 
+                s->reg_data[addr] = value;
1305
 
+            break;
1306
 
+        case 0x44: /* PROTECT_KEY */
1307
 
+            s->twl4030->key_cfg = 0;
1308
 
+            s->twl4030->key_tst = 0;
1309
 
+            switch (value) {
1310
 
+                case 0x0C:
1311
 
+                    if (s->reg_data[addr] == 0xC0)
1312
 
+                        s->twl4030->key_cfg = 1;
1313
 
+                    break;
1314
 
+                case 0xE0:
1315
 
+                    if (s->reg_data[addr] == 0x0E)
1316
 
+                        s->twl4030->key_tst = 1;
1317
 
+                    break;
1318
 
+                case 0xEC:
1319
 
+                    if (s->reg_data[addr] == 0xCE) {
1320
 
+                        s->twl4030->key_cfg = 1;
1321
 
+                        s->twl4030->key_tst = 1;
1322
 
+                    }
1323
 
+                    break;
1324
 
+                default:
1325
 
+                    break;
1326
 
+            }
1327
 
+            s->reg_data[addr] = value;
1328
 
+            break;
1329
 
+        case 0x46: /* P1_SW_EVENTS */
1330
 
+        case 0x47: /* P2_SW_EVENTS */
1331
 
+        case 0x48: /* P3_SW_EVENTS */
1332
 
+            s->reg_data[addr] = value & 0x78;
1333
 
+            if (value & 0x01) { /* DEVOFF */
1334
 
+                TRACE("device power off sequence requested");
1335
 
+                qemu_system_shutdown_request();
1336
 
+            }
1337
 
+            break;
1338
 
+        case 0x4a: /* PB_CFG */
1339
 
+            s->reg_data[addr] = value & 0xf;
1340
 
+            break;
1341
 
+        case 0x4b: /* PB_MSB */
1342
 
+        case 0x4c: /* PB_LSB */
1343
 
+            s->reg_data[addr] = value;
1344
 
+            break;
1345
 
+        case 0x52: /* SEQ_ADD_W2P */
1346
 
+        case 0x53: /* SEQ_ADD_P2A */
1347
 
+        case 0x54: /* SEQ_ADD_A2W */
1348
 
+        case 0x55: /* SEQ_ADD_A2S */
1349
 
+        case 0x56: /* SEQ_ADD_S2A12 */
1350
 
+        case 0x57: /* SEQ_ADD_S2A3 */
1351
 
+        case 0x58: /* SEQ_ADD_WARM */
1352
 
+            if (s->twl4030->key_cfg)
1353
 
+                s->reg_data[addr] = value & 0x3f;
1354
 
+            break;
1355
 
+        case 0x59: /* MEMORY_ADDRESS */
1356
 
+            if (s->twl4030->key_cfg)
1357
 
+                s->reg_data[addr] = value;
1358
 
+            break;
1359
 
+        case 0x5a: /* MEMORY_DATA */
1360
 
+            if (s->twl4030->key_cfg) {
1361
 
+                s->reg_data[addr] = value;
1362
 
+                seq_addr = s->reg_data[0x59];
1363
 
+                seq_sub = seq_addr & 3;
1364
 
+                seq_addr >>= 2;
1365
 
+                if ((seq_addr >= 0x2b && seq_addr <= 0x3e) ||
1366
 
+                    (seq_addr <= 0x0e && seq_sub == 3))
1367
 
+                    s->twl4030->seq_mem[seq_addr][seq_sub] = value;
1368
 
+            }
1369
 
+            /* TODO: check if autoincrement is write-protected as well */
1370
 
+            s->reg_data[0x59]++;
1371
 
+            break;
1372
 
+        case 0x5e: /* WATCHDOG_CFG */
1373
 
+        case 0x60: /* VIBRATOR_CFG */
1374
 
+        case 0x6d: /* BB_CFG */
1375
 
+        case 0x73: /* VAUX1_TYPE */
1376
 
+        case 0x77: /* VAUX2_TYPE */
1377
 
+        case 0x7b: /* VAUX3_TYPE */
1378
 
+        case 0x7f: /* VAUX4_TYPE */
1379
 
+        case 0x83: /* VMMC1_TYPE */
1380
 
+        case 0x87: /* VMMC2_TYPE */
1381
 
+        case 0x8b: /* VPLL1_TYPE */
1382
 
+        case 0x8f: /* VPLL2_TYPE */
1383
 
+        case 0x93: /* VSIM_TYPE */
1384
 
+        case 0x97: /* VDAC_TYPE */
1385
 
+        case 0x9b: /* VINTANA1_TYPE */
1386
 
+        case 0x9f: /* VINTANA2_TYPE */
1387
 
+        case 0xa3: /* VINTDIG_TYPE */
1388
 
+        case 0xa7: /* VIO_TYPE */
1389
 
+        case 0xaa: /* VIO_MISC_CFG */
1390
 
+        case 0xb1: /* VDD1_TYPE */
1391
 
+        case 0xb4: /* VDD1_MISC_CFG */
1392
 
+        case 0xbd: /* VDD1_STEP */
1393
 
+        case 0xbf: /* VDD2_TYPE */
1394
 
+        case 0xc2: /* VDD2_MISC_CFG */
1395
 
+        case 0xcb: /* VDD2_STEP */
1396
 
+        case 0xcd: /* VUSB1V5_TYPE */
1397
 
+        case 0xd0: /* VUSB1V8_TYPE */
1398
 
+        case 0xd3: /* VUSB3V1_TYPE */
1399
 
+        case 0xdb: /* REGEN_TYPE */
1400
 
+        case 0xde: /* NRESPWRON_TYPE */
1401
 
+        case 0xe1: /* CLKEN_TYPE */
1402
 
+        case 0xe4: /* SYSEN_TYPE */
1403
 
+        case 0xe7: /* HFCLKOUT_TYPE */
1404
 
+        case 0xea: /* 2KCLKOUT_TYPE */
1405
 
+        case 0xed: /* TRITON_RESET_TYPE */
1406
 
+        case 0xf0: /* MAINREF_TYPE */
1407
 
+            s->reg_data[addr] = value & 0x1f;
1408
 
+            break;
1409
 
+        case 0x5f: /* IT_CHECK_CFG */
1410
 
+        case 0xb9: /* VDD1_VSEL */
1411
 
+        case 0xbb: /* VDD1_VFLOOR */
1412
 
+        case 0xbc: /* VDD1_VROOF */
1413
 
+        case 0xc7: /* VDD2_VSEL */
1414
 
+        case 0xc9: /* VDD2_VFLOOR */
1415
 
+        case 0xca: /* VDD2_VROOF */
1416
 
+            s->reg_data[addr] = value & 0x7f;
1417
 
+            break;
1418
 
+        case 0x61: /* DC/DC_GLOBAL_CFG */
1419
 
+        case 0x68: /* MISC_CFG */
1420
 
+            s->reg_data[addr] = value;
1421
 
+            break;
1422
 
+        case 0x62: /* VDD1_TRIM1 */
1423
 
+        case 0x64: /* VDD2_TRIM1 */
1424
 
+        case 0x66: /* VIO_TRIM1 */
1425
 
+        case 0xac: /* VIO_TEST2 */
1426
 
+        case 0xb6: /* VDD1_TEST2 */
1427
 
+        case 0xc4: /* VDD2_TEST2 */
1428
 
+            if (s->twl4030->key_tst)
1429
 
+                s->reg_data[addr] = value & 0x7f;
1430
 
+            break;
1431
 
+        case 0x63: /* VDD1_TRIM2 */
1432
 
+        case 0x65: /* VDD2_TRIM2 */
1433
 
+        case 0x67: /* VIO_TRIM2 */
1434
 
+            if (s->twl4030->key_tst)
1435
 
+                s->reg_data[addr] = value & 0x3f;
1436
 
+            break;
1437
 
+        case 0x72: /* VAUX1_DEV_GRP */
1438
 
+        case 0x76: /* VAUX2_DEV_GRP */
1439
 
+        case 0x7a: /* VAUX3_DEV_GRP */
1440
 
+        case 0x7e: /* VAUX4_DEV_GRP */
1441
 
+        case 0x82: /* VMMC1_DEV_GRP */
1442
 
+        case 0x86: /* VMMC2_DEV_GRP */
1443
 
+        case 0x8a: /* VPLL1_DEV_GRP */
1444
 
+        case 0x8e: /* VPLL2_DEV_GRP */
1445
 
+        case 0x92: /* VSIM_DEV_GRP */
1446
 
+        case 0x96: /* VDAC_DEV_GRP */
1447
 
+        case 0x9a: /* VINTANA1_DEV_GRP */
1448
 
+        case 0x9e: /* VINTANA2_DEV_GRP */
1449
 
+        case 0xa2: /* VINTDIG_DEV_GRP */
1450
 
+        case 0xa6: /* VIO_DEV_GRP */
1451
 
+        case 0xb0: /* VDD1_DEV_GRP */
1452
 
+        case 0xbe: /* VDD2_DEV_GRP */
1453
 
+        case 0xcc: /* VUSB1V5_DEV_GRP */
1454
 
+        case 0xcf: /* VUSB1V8_DEV_GRP */
1455
 
+        case 0xd2: /* VUSB3V1_DEV_GRP */
1456
 
+        case 0xda: /* REGEN_DEV_GRP */
1457
 
+        case 0xdd: /* NRESPWRON_DEV_GRP */
1458
 
+        case 0xe0: /* CLKEN_DEV_GRP */
1459
 
+        case 0xe3: /* SYSEN_DEV_GRP */
1460
 
+        case 0xe6: /* HFCLKOUT_DEV_GRP */
1461
 
+        case 0xe9: /* 2KCLKOUT_DEV_GRP */
1462
 
+        case 0xec: /* TRITON_RESET_DEV_GRP */
1463
 
+        case 0xef: /* MAINREF_DEV_GRP */
1464
 
+            s->reg_data[addr] = (s->reg_data[addr] & 0x0f) | (value & 0xf0);
1465
 
+            break;
1466
 
+        case 0x75: /* VAUX1_DEDICATED */
1467
 
+        case 0x7d: /* VAUX3_DEDICATED */
1468
 
+        case 0x8d: /* VPLL1_DEDICATED */
1469
 
+        case 0x95: /* VSIM_DEDICATED */
1470
 
+            if (s->twl4030->key_tst)
1471
 
+                s->reg_data[addr] = value & 0x77;
1472
 
+            else
1473
 
+                s->reg_data[addr] = (s->reg_data[addr] & 0x70) | (value & 0x07);
1474
 
+            break;
1475
 
+        case 0x79: /* VAUX2_DEDICATED */
1476
 
+        case 0x81: /* VAUX4_DEDICATED */
1477
 
+        case 0x91: /* VPLL2_DEDICATED */
1478
 
+        case 0xa5: /* VINTDIG_DEDICATED */
1479
 
+            if (s->twl4030->key_tst)
1480
 
+                s->reg_data[addr] = value & 0x7f;
1481
 
+            else
1482
 
+                s->reg_data[addr] = (s->reg_data[addr] & 0x70) | (value & 0x0f);
1483
 
+            break;
1484
 
+        case 0x85: /* VMMC1_DEDICATED */
1485
 
+        case 0x99: /* VDAC_DEDICATED */
1486
 
+            if (s->twl4030->key_tst)
1487
 
+                s->reg_data[addr] = value & 0x73;
1488
 
+            else
1489
 
+                s->reg_data[addr] = (s->reg_data[addr] & 0x70) | (value & 0x03);
1490
 
+            break;
1491
 
+        case 0x89: /* VMMC2_DEDICATED */
1492
 
+            if (s->twl4030->key_tst)
1493
 
+                s->reg_data[addr] = value & 0x7f;
1494
 
+            else
1495
 
+                s->reg_data[addr] = (s->reg_data[addr] & 0x70) | (value & 0x0f);
1496
 
+            break;
1497
 
+        case 0x9d: /* VINTANA1_DEDICATED */
1498
 
+            if (s->twl4030->key_tst)
1499
 
+                s->reg_data[addr] = value & 0x70;
1500
 
+            break;
1501
 
+        case 0xa1: /* VINTANA2_DEDICATED */
1502
 
+            if (s->twl4030->key_tst)
1503
 
+                s->reg_data[addr] = value & 0x71;
1504
 
+            else
1505
 
+                s->reg_data[addr] = (s->reg_data[addr] & 0x70) | (value & 0x01);
1506
 
+            break;
1507
 
+        case 0x74: /* VAUX1_REMAP */
1508
 
+        case 0x78: /* VAUX2_REMAP */
1509
 
+        case 0x7c: /* VAUX3_REMAP */
1510
 
+        case 0x80: /* VAUX4_REMAP */
1511
 
+        case 0x84: /* VMMC1_REMAP */
1512
 
+        case 0x88: /* VMMC2_REMAP */
1513
 
+        case 0x8c: /* VPLL1_REMAP */
1514
 
+        case 0x90: /* VPLL2_REMAP */
1515
 
+        case 0x94: /* VSIM_REMAP */
1516
 
+        case 0x98: /* VDAC_REMAP */
1517
 
+        case 0x9c: /* VINTANA1_REMAP */
1518
 
+        case 0xa0: /* VINTANA2_REMAP */
1519
 
+        case 0xa4: /* VINTDIG_REMAP */
1520
 
+        case 0xa8: /* VIO_REMAP */
1521
 
+        case 0xb2: /* VDD1_REMAP */
1522
 
+        case 0xc0: /* VDD2_REMAP */
1523
 
+        case 0xce: /* VUSB1V5_REMAP */
1524
 
+        case 0xd1: /* VUSB1V8_REMAP */
1525
 
+        case 0xd4: /* VUSB3V1_REMAP */
1526
 
+        case 0xdc: /* REGEN_REMAP */
1527
 
+        case 0xdf: /* NRESPWRON_REMAP */
1528
 
+        case 0xe2: /* CLKEN_REMAP */
1529
 
+        case 0xe5: /* SYSEN_REMAP */
1530
 
+        case 0xe8: /* HFCLKOUT_REMAP */
1531
 
+        case 0xeb: /* 2KCLKOUT_REMAP */
1532
 
+        case 0xee: /* TRITON_RESET_REMAP */
1533
 
+        case 0xf1: /* MAINREF_REMAP */
1534
 
+            s->reg_data[addr] = value;
1535
 
+            break;
1536
 
+        case 0xa9: /* VIO_CFG */
1537
 
+        case 0xb3: /* VDD1_CFG */
1538
 
+        case 0xc1: /* VDD2_CFG */
1539
 
+            s->reg_data[addr] = value & 0x03;
1540
 
+            break;
1541
 
+        case 0xab: /* VIO_TEST1 */
1542
 
+        case 0xb5: /* VDD1_TEST1 */
1543
 
+        case 0xc3: /* VDD2_TEST1 */
1544
 
+            if (s->twl4030->key_tst)
1545
 
+                s->reg_data[addr] = value;
1546
 
+            break;
1547
 
+        case 0xad: /* VIO_OSC */
1548
 
+        case 0xb7: /* VDD1_OSC */
1549
 
+        case 0xc5: /* VDD2_OSC */
1550
 
+            s->reg_data[addr] = value & 0x5f;
1551
 
+            break;
1552
 
+        case 0xae: /* VIO_RESERVED */
1553
 
+        case 0xb8: /* VDD1_RESERVED */
1554
 
+        case 0xc6: /* VDD2_RESERVED */
1555
 
+            break;
1556
 
+        case 0xaf: /* VIO_VSEL */
1557
 
+            s->reg_data[addr] = value & 0x01;
1558
 
+            break;
1559
 
+        case 0xba: /* VDD1_VMODE_CFG */
1560
 
+        case 0xc8: /* VDD2_VMODE_CFG */
1561
 
+            s->reg_data[addr] = (s->reg_data[addr] & 0x38) | (value & 0x07);
1562
 
+            break;
1563
 
+        case 0xd8: /* VUSB_DEDICATED1 */
1564
 
+            s->reg_data[addr] = value & 0x1f;
1565
 
+            break;
1566
 
+        case 0xd9: /* VUSB_DEDICATED2 */
1567
 
+            s->reg_data[addr] = value & 0x08;
1568
 
+            break;
1569
 
+
1570
 
+        default:
1571
 
+               hw_error("%s: unknown register 0x%02x value 0x%02x",
1572
 
+                    __FUNCTION__, addr, value);
1573
 
+            break;
1574
 
+    }
1575
 
+}
1576
 
+
1577
 
+static void twl4030_key_setstate(TWL4030NodeState *s,
1578
 
+                                 int col, int row, int state)
1579
 
+{
1580
 
+    TRACE("col=%d, row=%d, state=%d", col, row, state);
1581
 
+    if (col >= 0 && col < 8 && row >= 0 && row < 8) {
1582
 
+        s->reg_data[0xd8] = col; /* KBC_REG */
1583
 
+        s->reg_data[0xd9] = row; /* KBR_REG */
1584
 
+        int gen_int = 0;
1585
 
+        if (state) {
1586
 
+            s->reg_data[0xdb + row] |= 1 << col; /* FULL_CODE_xx_yy */
1587
 
+            gen_int = s->reg_data[0xe8] & 0x02;  /* ITKPRISING */
1588
 
+        } else {
1589
 
+            s->reg_data[0xdb + row] &= ~(1 << col); /* FULL_CODE_xx_yy */
1590
 
+            gen_int = s->reg_data[0xe8] & 0x01;     /* ITKPFALLING */
1591
 
+        }
1592
 
+        if (gen_int) {
1593
 
+            s->reg_data[0xe3] |= 0x01; /* ITKPISR1 */
1594
 
+            s->reg_data[0xe5] |= 0x01; /* ITKPISR2 */
1595
 
+            twl4030_interrupt_update(s->twl4030);
1596
 
+        }
1597
 
+    }
1598
 
+}
1599
 
+
1600
 
+static void twl4030_key_handler(void *opaque, int keycode)
1601
 
+{
1602
 
+    TWL4030NodeState *s = (TWL4030NodeState *)opaque;
1603
 
+    if (!s->twl4030->extended_key && keycode == 0xe0) {
1604
 
+        s->twl4030->extended_key = 0x80;
1605
 
+    } else {
1606
 
+        const TWL4030KeyMap *k = s->twl4030->keymap;
1607
 
+        int fullcode = (keycode & 0x7f) | (s->twl4030->extended_key);
1608
 
+        for (; k && k->code >= 0; k++) {
1609
 
+            if (k->code == fullcode) {
1610
 
+                twl4030_key_setstate(s, k->column, k->row, !(keycode & 0x80));
1611
 
+            }
1612
 
+        }
1613
 
+        s->twl4030->extended_key = 0;
1614
 
+    }
1615
 
+}
1616
 
+
1617
 
+static void twl4030_node_reset(TWL4030NodeState *s,
1618
 
+                               const uint8_t *reset_values)
1619
 
+{
1620
 
+    s->firstbyte = 0;
1621
 
+    s->reg = 0x00;
1622
 
+    memcpy(s->reg_data, reset_values, 256);
1623
 
+}
1624
 
+
1625
 
+static void twl4030_node_init(TWL4030NodeState *s,
1626
 
+                              twl4030_read_func read,
1627
 
+                              twl4030_write_func write,
1628
 
+                              const uint8_t *reset_values)
1629
 
+{
1630
 
+    s->read_func = read;
1631
 
+    s->write_func = write;
1632
 
+    twl4030_node_reset(s, reset_values);
1633
 
+}
1634
 
+
1635
 
+static int twl4030_48_init(I2CSlave *i2c)
1636
 
+{
1637
 
+    twl4030_node_init(FROM_I2C_SLAVE(TWL4030NodeState, i2c),
1638
 
+                      twl4030_48_read, twl4030_48_write,
1639
 
+                      addr_48_reset_values);
1640
 
+    return 0;
1641
 
+}
1642
 
+
1643
 
+static int twl4030_49_init(I2CSlave *i2c)
1644
 
+{
1645
 
+    twl4030_node_init(FROM_I2C_SLAVE(TWL4030NodeState, i2c),
1646
 
+                      twl4030_49_read, twl4030_49_write,
1647
 
+                      addr_49_reset_values);
1648
 
+    return 0;
1649
 
+}
1650
 
+
1651
 
+static int twl4030_4a_init(I2CSlave *i2c)
1652
 
+{
1653
 
+    TWL4030NodeState *s = FROM_I2C_SLAVE(TWL4030NodeState, i2c);
1654
 
+    twl4030_node_init(s,
1655
 
+                      twl4030_4a_read, twl4030_4a_write,
1656
 
+                      addr_4a_reset_values);
1657
 
+    qemu_add_kbd_event_handler(twl4030_key_handler, s);
1658
 
+    return 0;
1659
 
+}
1660
 
+
1661
 
+static int twl4030_4b_init(I2CSlave *i2c)
1662
 
+{
1663
 
+    twl4030_node_init(FROM_I2C_SLAVE(TWL4030NodeState, i2c),
1664
 
+                      twl4030_4b_read, twl4030_4b_write,
1665
 
+                      addr_4b_reset_values);
1666
 
+    return 0;
1667
 
+}
1668
 
+
1669
 
+static void twl4030_event(I2CSlave *i2c, enum i2c_event event)
1670
 
+{
1671
 
+    if (event == I2C_START_SEND) {
1672
 
+        TWL4030NodeState *s = FROM_I2C_SLAVE(TWL4030NodeState, i2c);
1673
 
+        s->firstbyte = 1;
1674
 
+    }
1675
 
+}
1676
 
+
1677
 
+static int twl4030_rx(I2CSlave *i2c)
1678
 
+{
1679
 
+    TWL4030NodeState *s = FROM_I2C_SLAVE(TWL4030NodeState, i2c);
1680
 
+    return s->read_func(s, s->reg++);
1681
 
+}
1682
 
+
1683
 
+static int twl4030_tx(I2CSlave *i2c, uint8_t data)
1684
 
+{
1685
 
+    TWL4030NodeState *s = FROM_I2C_SLAVE(TWL4030NodeState, i2c);
1686
 
+    if (s->firstbyte) {
1687
 
+        s->reg = data;
1688
 
+        s->firstbyte = 0;
1689
 
+    } else {
1690
 
+        s->write_func(s, s->reg++, data);
1691
 
+       }
1692
 
+    return 1;
1693
 
+}
1694
 
+
1695
 
+static void twl4030_reset(void *opaque)
1696
 
+{
1697
 
+    TWL4030State *s = opaque;
1698
 
+    
1699
 
+    timer_del(s->alarm_timer);
1700
 
+    timer_del(s->periodic_timer);
1701
 
+
1702
 
+    twl4030_node_reset(s->i2c[0], addr_48_reset_values);
1703
 
+    twl4030_node_reset(s->i2c[1], addr_49_reset_values);
1704
 
+    twl4030_node_reset(s->i2c[2], addr_4a_reset_values);
1705
 
+    twl4030_node_reset(s->i2c[3], addr_4b_reset_values);
1706
 
+
1707
 
+    s->extended_key = 0;
1708
 
+    s->key_cfg = 0;
1709
 
+    s->key_tst = 0;
1710
 
+    
1711
 
+    memset(s->seq_mem, 0, sizeof(s->seq_mem));
1712
 
+
1713
 
+    /* TODO: indicate correct reset reason */
1714
 
+}
1715
 
+
1716
 
+static void twl4030_48_class_init(ObjectClass *klass, void *data)
1717
 
+{
1718
 
+    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
1719
 
+    k->init = twl4030_48_init;
1720
 
+    k->event = twl4030_event;
1721
 
+    k->recv = twl4030_rx;
1722
 
+    k->send = twl4030_tx;
1723
 
+}
1724
 
+
1725
 
+static void twl4030_49_class_init(ObjectClass *klass, void *data)
1726
 
+{
1727
 
+    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
1728
 
+    k->init = twl4030_49_init;
1729
 
+    k->event = twl4030_event;
1730
 
+    k->recv = twl4030_rx;
1731
 
+    k->send = twl4030_tx;
1732
 
+}
1733
 
+
1734
 
+static void twl4030_4a_class_init(ObjectClass *klass, void *data)
1735
 
+{
1736
 
+    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
1737
 
+    k->init = twl4030_4a_init;
1738
 
+    k->event = twl4030_event;
1739
 
+    k->recv = twl4030_rx;
1740
 
+    k->send = twl4030_tx;
1741
 
+}
1742
 
+static void twl4030_4b_class_init(ObjectClass *klass, void *data)
1743
 
+{
1744
 
+    I2CSlaveClass *k = I2C_SLAVE_CLASS(klass);
1745
 
+    k->init = twl4030_4b_init;
1746
 
+    k->event = twl4030_event;
1747
 
+    k->recv = twl4030_rx;
1748
 
+    k->send = twl4030_tx;
1749
 
+}
1750
 
+
1751
 
+static TypeInfo twl4030_info[] = {
1752
 
+    {
1753
 
+        .name = "twl4030_48",
1754
 
+        .parent = TYPE_I2C_SLAVE,
1755
 
+        .instance_size = sizeof(TWL4030NodeState),
1756
 
+        .class_init = twl4030_48_class_init,
1757
 
+    },
1758
 
+    {
1759
 
+        .name = "twl4030_49",
1760
 
+        .parent = TYPE_I2C_SLAVE,
1761
 
+        .instance_size = sizeof(TWL4030NodeState),
1762
 
+        .class_init = twl4030_49_class_init,
1763
 
+    },
1764
 
+    {
1765
 
+        .name = "twl4030_4a",
1766
 
+        .parent = TYPE_I2C_SLAVE,
1767
 
+        .instance_size = sizeof(TWL4030NodeState),
1768
 
+        .class_init = twl4030_4a_class_init,
1769
 
+    },
1770
 
+    {
1771
 
+        .name = "twl4030_4b",
1772
 
+        .parent = TYPE_I2C_SLAVE,
1773
 
+        .instance_size = sizeof(TWL4030NodeState),
1774
 
+        .class_init = twl4030_4b_class_init,
1775
 
+    },
1776
 
+};
1777
 
+
1778
 
+void *twl4030_init(i2c_bus *bus, qemu_irq irq1, qemu_irq irq2,
1779
 
+                   const TWL4030KeyMap *keymap)
1780
 
+{
1781
 
+    TWL4030State *s = (TWL4030State *)g_malloc0(sizeof(*s));
1782
 
+
1783
 
+    s->irq1 = irq1;
1784
 
+    s->irq2 = irq2;
1785
 
+    s->key_cfg = 0;
1786
 
+    s->key_tst = 0;
1787
 
+    s->keymap = keymap;
1788
 
+
1789
 
+    s->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, twl4030_alarm, s);
1790
 
+    s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, twl4030_periodic, s);
1791
 
+
1792
 
+    int i;
1793
 
+    for (i = 0; i < ARRAY_SIZE(twl4030_info); i++) {
1794
 
+        DeviceState *ds = i2c_create_slave(bus, twl4030_info[i].name,
1795
 
+                                           0x48 + i);
1796
 
+        s->i2c[i] = FROM_I2C_SLAVE(TWL4030NodeState, I2C_SLAVE(ds));
1797
 
+        s->i2c[i]->twl4030 = s;
1798
 
+    }
1799
 
+
1800
 
+    qemu_register_reset(twl4030_reset, s);
1801
 
+    return s;
1802
 
+}
1803
 
+
1804
 
+void *twl5031_init(i2c_bus *bus, qemu_irq irq1, qemu_irq irq2,
1805
 
+                   const TWL4030KeyMap *keymap)
1806
 
+{
1807
 
+    TWL4030State *s = twl4030_init(bus, irq1, irq2, keymap);
1808
 
+    s->twl5031 = 1;
1809
 
+    return s;
1810
 
+}
1811
 
+
1812
 
+void twl4030_set_powerbutton_state(void *opaque, int pressed)
1813
 
+{
1814
 
+    TWL4030State *s = opaque;
1815
 
+    if (pressed) {
1816
 
+        if (!(s->i2c[3]->reg_data[0x45] & 0x01) && /* STS_PWON */
1817
 
+            (s->i2c[3]->reg_data[0x33] & 0x02)) {  /* PWRON_RISING */
1818
 
+            s->i2c[3]->reg_data[0x2e] |= 0x01;     /* PWRON */
1819
 
+            s->i2c[3]->reg_data[0x30] |= 0x01;     /* PWRON */
1820
 
+            twl4030_interrupt_update(s);
1821
 
+        }
1822
 
+        s->i2c[3]->reg_data[0x45] |= 0x01;         /* STS_PWON */
1823
 
+    } else {
1824
 
+        if ((s->i2c[3]->reg_data[0x45] & 0x01) &&  /* STS_PWON */
1825
 
+            (s->i2c[3]->reg_data[0x33] & 0x01)) {  /* PWRON_FALLING */
1826
 
+            s->i2c[3]->reg_data[0x2e] |= 0x01;     /* PWRON */
1827
 
+            s->i2c[3]->reg_data[0x30] |= 0x01;     /* PWRON */
1828
 
+            twl4030_interrupt_update(s);
1829
 
+        }
1830
 
+        s->i2c[3]->reg_data[0x45] &= ~0x01;        /* STS_PWON */
1831
 
+    }
1832
 
+}
1833
 
+
1834
 
+void twl4030_madc_attach(void *opaque, twl4030_madc_callback cb)
1835
 
+{
1836
 
+    TWL4030State *s = opaque;
1837
 
+    if (s->madc_cb) {
1838
 
+        fprintf(stderr,
1839
 
+                "%s: warning - overriding previously registered callback\n",
1840
 
+                __FUNCTION__);
1841
 
+    }
1842
 
+    s->madc_cb = cb;
1843
 
+}
1844
 
+
1845
 
+static void twl4030_register_types(void)
1846
 
+{
1847
 
+    TypeInfo *p = twl4030_info;
1848
 
+    int i;
1849
 
+    for (i = 0; i < ARRAY_SIZE(twl4030_info); p++, i++) {
1850
 
+        type_register_static(p);
1851
 
+    }
1852
 
+}
1853
 
+
1854
 
+type_init(twl4030_register_types);
1855
 
diff --git a/include/hw/i2c/i2c.h b/include/hw/i2c/i2c.h
1856
 
index 461392f..701164d 100644
1857
 
--- a/include/hw/i2c/i2c.h
1858
 
+++ b/include/hw/i2c/i2c.h
1859
 
@@ -75,6 +75,25 @@ void wm8750_set_bclk_in(void *opaque, int new_hz);
1860
 
 /* lm832x.c */
1861
 
 void lm832x_key_event(DeviceState *dev, int key, int state);
1862
 
 
1863
 
+/* twl4030.c */
1864
 
+typedef struct {
1865
 
+    int code;
1866
 
+    int column;
1867
 
+    int row;
1868
 
+} TWL4030KeyMap;
1869
 
+typedef enum twl4030_adc_type {
1870
 
+    TWL4030_ADC_RT,
1871
 
+    TWL4030_ADC_GP,
1872
 
+    TWL4030_ADC_BCI
1873
 
+} twl4030_adc_type;
1874
 
+typedef uint16_t (*twl4030_madc_callback)(twl4030_adc_type type, int ch);
1875
 
+void *twl4030_init(i2c_bus *bus, qemu_irq irq1, qemu_irq irq2,
1876
 
+                   const TWL4030KeyMap *keymap);
1877
 
+void *twl5031_init(i2c_bus *bus, qemu_irq irq1, qemu_irq irq2,
1878
 
+                   const TWL4030KeyMap *keymap);
1879
 
+void twl4030_set_powerbutton_state(void *opaque, int pressed);
1880
 
+void twl4030_madc_attach(void *opaque, twl4030_madc_callback cb);
1881
 
+
1882
 
 extern const VMStateDescription vmstate_i2c_slave;
1883
 
 
1884
 
 #define VMSTATE_I2C_SLAVE(_field, _state) {                          \
1885
 
1.8.5.2
1886