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Viewing changes to debian/patches/ubuntu/arm64/0150-target-arm-A64-Add-narrowing-2-reg-misc-instructions.patch

  • Committer: Package Import Robot
  • Author(s): Serge Hallyn
  • Date: 2014-02-25 22:31:43 UTC
  • mfrom: (1.8.5)
  • Revision ID: package-import@ubuntu.com-20140225223143-odhqxfc60wxrjl15
Tags: 2.0.0~rc1+dfsg-0ubuntu1
https://launchpad.net/bugs/1294823
https://launchpad.net/bugs/1295072
* Merge 2.0.0-rc1
* debian/rules: consolidate ppc filter entries.
* Move qemu-system-arch64 into qemu-system-arm
* debian/patches/define-trusty-machine-type.patch: define a trusty machine
  type, currently the same as pc-i440fx-2.0, to put is in a better position
  to enable live migrations from trusty onward.  (LP: #1294823)
* debian/control: build-dep on libfdt >= 1.4.0  (LP: #1295072)
* Merge latest upstream git to commit dc9528f
* Debian/rules:
  - remove -enable-uname-release=2.6.32
  - don't make the aarch64 target Ubuntu-specific.
* Remove patches which are now upstream:
  - fix-smb-security-share.patch
  - slirp-smb-redirect-port-445-too.patch 
  - linux-user-Implement-sendmmsg-syscall.patch (better version is upstream)
  - signal-added-a-wrapper-for-sigprocmask-function.patch
  - ubuntu/signal-sigsegv-protection-on-do_sigprocmask.patch
  - ubuntu/Don-t-block-SIGSEGV-at-more-places.patch
  - ubuntu/ppc-force-cpu-threads-count-to-be-power-of-2.patch
* add link for /usr/share/qemu/bios-256k.bin
* Remove all linaro patches.
* Remove all arm64/ patches.  Many but not all are upstream.
* Remove CVE-2013-4377.patch which is upstream.
* debian/control-in: don't make qemu-system-aarch64 ubuntu-specific

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debian/patches/ubuntu/arm64/0150-target-arm-A64-Add-narrowing-2-reg-misc-instructions.patch
1
 
From ebce42385269c9cd63c1f9471aa825ef2b911165 Mon Sep 17 00:00:00 2001
2
 
From: Peter Maydell <peter.maydell@linaro.org>
3
 
Date: Mon, 3 Feb 2014 23:31:52 +0000
4
 
Subject: [PATCH 150/158] target-arm: A64: Add narrowing 2-reg-misc
5
 
 instructions
6
 
 
7
 
Add the narrowing integer instructions in the 2-reg-misc class.
8
 
 
9
 
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
 
Reviewed-by: Richard Henderson <rth@twiddle.net>
11
 
---
12
 
 target-arm/translate-a64.c | 85 ++++++++++++++++++++++++++++++++++++++++++++--
13
 
 1 file changed, 83 insertions(+), 2 deletions(-)
14
 
 
15
 
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
16
 
index dd1bbeb..42457e4 100644
17
 
--- a/target-arm/translate-a64.c
18
 
+++ b/target-arm/translate-a64.c
19
 
@@ -75,6 +75,8 @@ typedef struct AArch64DecodeTable {
20
 
 /* Function prototype for gen_ functions for calling Neon helpers */
21
 
 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
22
 
 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
23
 
+typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
24
 
+typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
25
 
 
26
 
 /* initialize TCG globals.  */
27
 
 void a64_translate_init(void)
28
 
@@ -7371,6 +7373,79 @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
29
 
     }
30
 
 }
31
 
 
32
 
+static void handle_2misc_narrow(DisasContext *s, int opcode, bool u, bool is_q,
33
 
+                                int size, int rn, int rd)
34
 
+{
35
 
+    /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
36
 
+     * in the source becomes a size element in the destination).
37
 
+     */
38
 
+    int pass;
39
 
+    TCGv_i32 tcg_res[2];
40
 
+    int destelt = is_q ? 2 : 0;
41
 
+
42
 
+    for (pass = 0; pass < 2; pass++) {
43
 
+        TCGv_i64 tcg_op = tcg_temp_new_i64();
44
 
+        NeonGenNarrowFn *genfn = NULL;
45
 
+        NeonGenNarrowEnvFn *genenvfn = NULL;
46
 
+
47
 
+        read_vec_element(s, tcg_op, rn, pass, MO_64);
48
 
+        tcg_res[pass] = tcg_temp_new_i32();
49
 
+
50
 
+        switch (opcode) {
51
 
+        case 0x12: /* XTN, SQXTUN */
52
 
+        {
53
 
+            static NeonGenNarrowFn * const xtnfns[3] = {
54
 
+                gen_helper_neon_narrow_u8,
55
 
+                gen_helper_neon_narrow_u16,
56
 
+                tcg_gen_trunc_i64_i32,
57
 
+            };
58
 
+            static NeonGenNarrowEnvFn * const sqxtunfns[3] = {
59
 
+                gen_helper_neon_unarrow_sat8,
60
 
+                gen_helper_neon_unarrow_sat16,
61
 
+                gen_helper_neon_unarrow_sat32,
62
 
+            };
63
 
+            if (u) {
64
 
+                genenvfn = sqxtunfns[size];
65
 
+            } else {
66
 
+                genfn = xtnfns[size];
67
 
+            }
68
 
+            break;
69
 
+        }
70
 
+        case 0x14: /* SQXTN, UQXTN */
71
 
+        {
72
 
+            static NeonGenNarrowEnvFn * const fns[3][2] = {
73
 
+                { gen_helper_neon_narrow_sat_s8,
74
 
+                  gen_helper_neon_narrow_sat_u8 },
75
 
+                { gen_helper_neon_narrow_sat_s16,
76
 
+                  gen_helper_neon_narrow_sat_u16 },
77
 
+                { gen_helper_neon_narrow_sat_s32,
78
 
+                  gen_helper_neon_narrow_sat_u32 },
79
 
+            };
80
 
+            genenvfn = fns[size][u];
81
 
+            break;
82
 
+        }
83
 
+        default:
84
 
+            g_assert_not_reached();
85
 
+        }
86
 
+
87
 
+        if (genfn) {
88
 
+            genfn(tcg_res[pass], tcg_op);
89
 
+        } else {
90
 
+            genenvfn(tcg_res[pass], cpu_env, tcg_op);
91
 
+        }
92
 
+
93
 
+        tcg_temp_free_i64(tcg_op);
94
 
+    }
95
 
+
96
 
+    for (pass = 0; pass < 2; pass++) {
97
 
+        write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32);
98
 
+        tcg_temp_free_i32(tcg_res[pass]);
99
 
+    }
100
 
+    if (!is_q) {
101
 
+        clear_vec_high(s, rd);
102
 
+    }
103
 
+}
104
 
+
105
 
 /* C3.6.17 AdvSIMD two reg misc
106
 
  *   31  30  29 28       24 23  22 21       17 16    12 11 10 9    5 4    0
107
 
  * +---+---+---+-----------+------+-----------+--------+-----+------+------+
108
 
@@ -7405,11 +7480,17 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
109
 
         }
110
 
         unallocated_encoding(s);
111
 
         return;
112
 
+    case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
113
 
+    case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
114
 
+        if (size == 3) {
115
 
+            unallocated_encoding(s);
116
 
+            return;
117
 
+        }
118
 
+        handle_2misc_narrow(s, opcode, u, is_q, size, rn, rd);
119
 
+        return;
120
 
     case 0x2: /* SADDLP, UADDLP */
121
 
     case 0x4: /* CLS, CLZ */
122
 
     case 0x6: /* SADALP, UADALP */
123
 
-    case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
124
 
-    case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
125
 
         if (size == 3) {
126
 
             unallocated_encoding(s);
127
 
             return;
128
 
1.9.rc1
129