← Back to branch summary

~ubuntu-branches/ubuntu/vivid/qemu/vivid

« back to all changes in this revision

Viewing changes to target-i386/seg_helper.c

  • Committer: Package Import Robot
  • Author(s): Serge Hallyn
  • Date: 2014-02-25 22:31:43 UTC
  • mfrom: (1.8.5)
  • Revision ID: package-import@ubuntu.com-20140225223143-odhqxfc60wxrjl15
Tags: 2.0.0~rc1+dfsg-0ubuntu1
https://launchpad.net/bugs/1294823
https://launchpad.net/bugs/1295072
* Merge 2.0.0-rc1
* debian/rules: consolidate ppc filter entries.
* Move qemu-system-arch64 into qemu-system-arm
* debian/patches/define-trusty-machine-type.patch: define a trusty machine
  type, currently the same as pc-i440fx-2.0, to put is in a better position
  to enable live migrations from trusty onward.  (LP: #1294823)
* debian/control: build-dep on libfdt >= 1.4.0  (LP: #1295072)
* Merge latest upstream git to commit dc9528f
* Debian/rules:
  - remove -enable-uname-release=2.6.32
  - don't make the aarch64 target Ubuntu-specific.
* Remove patches which are now upstream:
  - fix-smb-security-share.patch
  - slirp-smb-redirect-port-445-too.patch 
  - linux-user-Implement-sendmmsg-syscall.patch (better version is upstream)
  - signal-added-a-wrapper-for-sigprocmask-function.patch
  - ubuntu/signal-sigsegv-protection-on-do_sigprocmask.patch
  - ubuntu/Don-t-block-SIGSEGV-at-more-places.patch
  - ubuntu/ppc-force-cpu-threads-count-to-be-power-of-2.patch
* add link for /usr/share/qemu/bios-256k.bin
* Remove all linaro patches.
* Remove all arm64/ patches.  Many but not all are upstream.
* Remove CVE-2013-4377.patch which is upstream.
* debian/control-in: don't make qemu-system-aarch64 ubuntu-specific

Show diffs side-by-side

added added

removed removed

Lines of Context:
target-i386/seg_helper.c
95
95
static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr,
96
96
                                       uint32_t *esp_ptr, int dpl)
97
97
{
 
98
    X86CPU *cpu = x86_env_get_cpu(env);
98
99
    int type, index, shift;
99
100
 
100
101
#if 0
112
113
#endif
113
114
 
114
115
    if (!(env->tr.flags & DESC_P_MASK)) {
115
 
        cpu_abort(env, "invalid tss");
 
116
        cpu_abort(CPU(cpu), "invalid tss");
116
117
    }
117
118
    type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
118
119
    if ((type & 7) != 1) {
119
 
        cpu_abort(env, "invalid tss type");
 
120
        cpu_abort(CPU(cpu), "invalid tss type");
120
121
    }
121
122
    shift = type >> 3;
122
123
    index = (dpl * 4 + 2) << shift;
782
783
 
783
784
static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level)
784
785
{
 
786
    X86CPU *cpu = x86_env_get_cpu(env);
785
787
    int index;
786
788
 
787
789
#if 0
790
792
#endif
791
793
 
792
794
    if (!(env->tr.flags & DESC_P_MASK)) {
793
 
        cpu_abort(env, "invalid tss");
 
795
        cpu_abort(CPU(cpu), "invalid tss");
794
796
    }
795
797
    index = 8 * level + 4;
796
798
    if ((index + 7) > env->tr.limit) {
935
937
#if defined(CONFIG_USER_ONLY)
936
938
void helper_syscall(CPUX86State *env, int next_eip_addend)
937
939
{
938
 
    env->exception_index = EXCP_SYSCALL;
 
940
    CPUState *cs = CPU(x86_env_get_cpu(env));
 
941
 
 
942
    cs->exception_index = EXCP_SYSCALL;
939
943
    env->exception_next_eip = env->eip + next_eip_addend;
940
 
    cpu_loop_exit(env);
 
944
    cpu_loop_exit(cs);
941
945
}
942
946
#else
943
947
void helper_syscall(CPUX86State *env, int next_eip_addend)
1131
1135
static void handle_even_inj(CPUX86State *env, int intno, int is_int,
1132
1136
                            int error_code, int is_hw, int rm)
1133
1137
{
1134
 
    uint32_t event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
 
1138
    CPUState *cs = CPU(x86_env_get_cpu(env));
 
1139
    uint32_t event_inj = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
1135
1140
                                                          control.event_inj));
1136
1141
 
1137
1142
    if (!(event_inj & SVM_EVTINJ_VALID)) {
1145
1150
        event_inj = intno | type | SVM_EVTINJ_VALID;
1146
1151
        if (!rm && exception_has_error_code(intno)) {
1147
1152
            event_inj |= SVM_EVTINJ_VALID_ERR;
1148
 
            stl_phys(env->vm_vmcb + offsetof(struct vmcb,
 
1153
            stl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
1149
1154
                                             control.event_inj_err),
1150
1155
                     error_code);
1151
1156
        }
1152
 
        stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
 
1157
        stl_phys(cs->as,
 
1158
                 env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
1153
1159
                 event_inj);
1154
1160
    }
1155
1161
}
1225
1231
 
1226
1232
#if !defined(CONFIG_USER_ONLY)
1227
1233
    if (env->hflags & HF_SVMI_MASK) {
1228
 
        uint32_t event_inj = ldl_phys(env->vm_vmcb +
 
1234
        CPUState *cs = CPU(cpu);
 
1235
        uint32_t event_inj = ldl_phys(cs->as, env->vm_vmcb +
1229
1236
                                      offsetof(struct vmcb,
1230
1237
                                               control.event_inj));
1231
1238
 
1232
 
        stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
 
1239
        stl_phys(cs->as,
 
1240
                 env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
1233
1241
                 event_inj & ~SVM_EVTINJ_VALID);
1234
1242
    }
1235
1243
#endif
1244
1252
    /* if user mode only, we simulate a fake exception
1245
1253
       which will be handled outside the cpu execution
1246
1254
       loop */
1247
 
    do_interrupt_user(env, env->exception_index,
 
1255
    do_interrupt_user(env, cs->exception_index,
1248
1256
                      env->exception_is_int,
1249
1257
                      env->error_code,
1250
1258
                      env->exception_next_eip);
1254
1262
    /* simulate a real cpu exception. On i386, it can
1255
1263
       trigger new exceptions, but we do not handle
1256
1264
       double or triple faults yet. */
1257
 
    do_interrupt_all(cpu, env->exception_index,
 
1265
    do_interrupt_all(cpu, cs->exception_index,
1258
1266
                     env->exception_is_int,
1259
1267
                     env->error_code,
1260
1268
                     env->exception_next_eip, 0);