59
58
#define EXCP_HLT 0x10001 /* hlt instruction reached */
60
59
#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
61
60
#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
63
#define TB_JMP_CACHE_BITS 12
64
#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
61
#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
66
63
/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
67
64
addresses on the same page. The top bits are the same. This allows
120
#ifdef HOST_WORDS_BIGENDIAN
121
typedef struct icount_decr_u16 {
126
typedef struct icount_decr_u16 {
132
typedef struct CPUBreakpoint {
134
int flags; /* BP_* */
135
QTAILQ_ENTRY(CPUBreakpoint) entry;
138
typedef struct CPUWatchpoint {
140
target_ulong len_mask;
141
int flags; /* BP_* */
142
QTAILQ_ENTRY(CPUWatchpoint) entry;
145
117
#define CPU_TEMP_BUF_NLONGS 128
146
118
#define CPU_COMMON \
147
119
/* soft mmu support */ \
148
/* in order to avoid passing too many arguments to the MMIO \
149
helpers, we store some rarely used information in the CPU \
151
uintptr_t mem_io_pc; /* host pc at which the memory was \
153
target_ulong mem_io_vaddr; /* target virtual addr at which the \
154
memory was accessed */ \
156
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
158
int64_t icount_extra; /* Instructions until next timer event. */ \
159
/* Number of cycles left, with interrupt flag in high bit. \
160
This allows a single read-compare-cbranch-write sequence to test \
161
for both decrementer underflow and exceptions. */ \
164
icount_decr_u16 u16; \
166
uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
168
/* from this point: preserved by CPU reset */ \
169
/* ice debug support */ \
170
QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
172
QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
173
CPUWatchpoint *watchpoint_hit; \
175
/* Core interrupt code */ \
176
sigjmp_buf jmp_env; \
177
int exception_index; \