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Viewing changes to debian/patches/ubuntu/linaro/0021-omap_i2c.c-Support-byte-reads-to-registers.patch

  • Committer: Package Import Robot
  • Author(s): Serge Hallyn
  • Date: 2014-02-25 22:31:43 UTC
  • mfrom: (1.8.5)
  • Revision ID: package-import@ubuntu.com-20140225223143-odhqxfc60wxrjl15
Tags: 2.0.0~rc1+dfsg-0ubuntu1
https://launchpad.net/bugs/1294823
https://launchpad.net/bugs/1295072
* Merge 2.0.0-rc1
* debian/rules: consolidate ppc filter entries.
* Move qemu-system-arch64 into qemu-system-arm
* debian/patches/define-trusty-machine-type.patch: define a trusty machine
  type, currently the same as pc-i440fx-2.0, to put is in a better position
  to enable live migrations from trusty onward.  (LP: #1294823)
* debian/control: build-dep on libfdt >= 1.4.0  (LP: #1295072)
* Merge latest upstream git to commit dc9528f
* Debian/rules:
  - remove -enable-uname-release=2.6.32
  - don't make the aarch64 target Ubuntu-specific.
* Remove patches which are now upstream:
  - fix-smb-security-share.patch
  - slirp-smb-redirect-port-445-too.patch 
  - linux-user-Implement-sendmmsg-syscall.patch (better version is upstream)
  - signal-added-a-wrapper-for-sigprocmask-function.patch
  - ubuntu/signal-sigsegv-protection-on-do_sigprocmask.patch
  - ubuntu/Don-t-block-SIGSEGV-at-more-places.patch
  - ubuntu/ppc-force-cpu-threads-count-to-be-power-of-2.patch
* add link for /usr/share/qemu/bios-256k.bin
* Remove all linaro patches.
* Remove all arm64/ patches.  Many but not all are upstream.
* Remove CVE-2013-4377.patch which is upstream.
* debian/control-in: don't make qemu-system-aarch64 ubuntu-specific

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debian/patches/ubuntu/linaro/0021-omap_i2c.c-Support-byte-reads-to-registers.patch
1
 
From 093f316f0db143475efeec7ed06debb2c87495a9 Mon Sep 17 00:00:00 2001
2
 
From: Matt Waddel <matt.waddel@ubuntu.com>
3
 
Date: Mon, 18 Feb 2013 16:58:26 +0000
4
 
Subject: [PATCH 21/70] omap_i2c.c: Support byte reads to registers
5
 
 
6
 
Added support for the byte read of the omap i2c system.
7
 
Handling is similar to the way i2c_write and i2c_writeb work.
8
 
---
9
 
 hw/i2c/omap_i2c.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-
10
 
 1 file changed, 56 insertions(+), 1 deletion(-)
11
 
 
12
 
diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c
13
 
index 9a1b0d2..0278390 100644
14
 
--- a/hw/i2c/omap_i2c.c
15
 
+++ b/hw/i2c/omap_i2c.c
16
 
@@ -326,6 +326,61 @@ static uint32_t omap_i2c_read(void *opaque, hwaddr addr)
17
 
     return 0;
18
 
 }
19
 
 
20
 
+static uint32_t omap_i2c_readb(void *opaque, hwaddr addr)
21
 
+{
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+    OMAPI2CState *s = opaque;
23
 
+    int offset = addr & OMAP_MPUI_REG_MASK;
24
 
+    uint8_t ret;
25
 
+
26
 
+    switch (offset) {
27
 
+    case 0x1c: /* I2C_DATA */
28
 
+        ret = 0;
29
 
+        if (s->fifolen) {
30
 
+            if (s->revision < OMAP3_INTR_REV) {
31
 
+                if (s->control & (1 << 14)) /* BE */
32
 
+                    ret = (((uint8_t)s->fifo[s->fifostart]) << 8)
33
 
+                        | s->fifo[(s->fifostart + 1) & I2C_FIFO_SIZE_MASK];
34
 
+                else
35
 
+                    ret = (((uint8_t)s->fifo[(s->fifostart + 1) & I2C_FIFO_SIZE_MASK]) << 8)
36
 
+                        | s->fifo[s->fifostart];
37
 
+                s->fifostart = (s->fifostart + 2) & I2C_FIFO_SIZE_MASK;
38
 
+                if (s->fifolen == 1) {
39
 
+                    s->stat |= 1 << 15; /* SBD */
40
 
+                    s->fifolen = 0;
41
 
+                } else
42
 
+                    s->fifolen -= 2;
43
 
+                if (!s->fifolen) {
44
 
+                    s->stat &= ~(1 << 3); /* RRDY */
45
 
+                    s->stat |= 1 << 2;    /* ARDY */
46
 
+                }
47
 
+            } else {
48
 
+                s->stat &= ~(1 << 7); /* AERR */
49
 
+                ret = (uint8_t)s->fifo[s->fifostart++];
50
 
+                s->fifostart &= I2C_FIFO_SIZE_MASK;
51
 
+                if (--s->fifolen) {
52
 
+                    if (s->fifolen <= ((s->dma >> 8) & 0x3f)) {
53
 
+                        s->stat &= ~(1 << 3); /* RRDY */
54
 
+                        s->stat |= 1 << 13;   /* RDR */
55
 
+                    }
56
 
+                } else {
57
 
+                    s->stat &= ~((1 << 3) | (1 << 13)); /* RRDY | RDR */
58
 
+                    s->stat |= 1 << 2;                  /* ARDY */
59
 
+                }
60
 
+            }
61
 
+            s->stat &= ~(1 << 11); /* ROVR */
62
 
+        } else if (s->revision >= OMAP3_INTR_REV)
63
 
+            s->stat |= (1 << 7); /* AERR */
64
 
+        omap_i2c_fifo_run(s);
65
 
+        omap_i2c_interrupts_update(s);
66
 
+        return ret;
67
 
+    default:
68
 
+        break;
69
 
+    }
70
 
+
71
 
+    OMAP_BAD_REG(addr);
72
 
+    return 0;
73
 
+}
74
 
+
75
 
 static void omap_i2c_write(void *opaque, hwaddr addr,
76
 
                 uint32_t value)
77
 
 {
78
 
@@ -589,7 +644,7 @@ static void omap_i2c_writeb(void *opaque, hwaddr addr,
79
 
 static const MemoryRegionOps omap_i2c_ops = {
80
 
     .old_mmio = {
81
 
         .read = {
82
 
-            omap_badwidth_read16,
83
 
+            omap_i2c_readb,
84
 
             omap_i2c_read,
85
 
             omap_badwidth_read16,
86
 
         },
87
 
1.8.5.2
88