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* QEMU model of the Canon DIGIC UART block.
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* Copyright (C) 2013 Antony Pavlov <antonynpavlov@gmail.com>
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* This model is based on reverse engineering efforts
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* made by CHDK (http://chdk.wikia.com) and
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* Magic Lantern (http://www.magiclantern.fm) projects
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* See "Serial terminal" docs here:
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* http://magiclantern.wikia.com/wiki/Register_Map#Misc_Registers
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* The QEMU model of the Milkymist UART block by Michael Walle
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* is used as a template.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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#include "hw/sysbus.h"
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#include "sysemu/char.h"
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#include "hw/char/digic-uart.h"
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static uint64_t digic_uart_read(void *opaque, hwaddr addr,
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DigicUartState *s = opaque;
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s->reg_st &= ~(ST_RX_RDY);
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qemu_log_mask(LOG_UNIMP,
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"digic-uart: read access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value,
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DigicUartState *s = opaque;
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unsigned char ch = value;
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qemu_chr_fe_write_all(s->chr, &ch, 1);
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* Ignore write to R_ST.
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* The point is that this register is actively used
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* during receiving and transmitting symbols,
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* but we don't know the function of most of bits.
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* Ignoring writes to R_ST is only a simplification
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* of the model. It has no perceptible side effects
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* for existing guests.
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qemu_log_mask(LOG_UNIMP,
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"digic-uart: write access to unknown register 0x"
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TARGET_FMT_plx, addr << 2);
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static const MemoryRegionOps uart_mmio_ops = {
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.read = digic_uart_read,
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.write = digic_uart_write,
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.min_access_size = 4,
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.max_access_size = 4,
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.endianness = DEVICE_NATIVE_ENDIAN,
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static int uart_can_rx(void *opaque)
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DigicUartState *s = opaque;
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return !(s->reg_st & ST_RX_RDY);
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static void uart_rx(void *opaque, const uint8_t *buf, int size)
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DigicUartState *s = opaque;
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assert(uart_can_rx(opaque));
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s->reg_st |= ST_RX_RDY;
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static void uart_event(void *opaque, int event)
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static void digic_uart_reset(DeviceState *d)
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DigicUartState *s = DIGIC_UART(d);
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s->reg_st = ST_TX_RDY;
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static void digic_uart_realize(DeviceState *dev, Error **errp)
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DigicUartState *s = DIGIC_UART(dev);
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s->chr = qemu_char_get_next_serial();
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qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
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static void digic_uart_init(Object *obj)
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DigicUartState *s = DIGIC_UART(obj);
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memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
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TYPE_DIGIC_UART, 0x18);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->regs_region);
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static const VMStateDescription vmstate_digic_uart = {
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.name = "digic-uart",
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(reg_rx, DigicUartState),
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VMSTATE_UINT32(reg_st, DigicUartState),
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VMSTATE_END_OF_LIST()
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static void digic_uart_class_init(ObjectClass *klass, void *data)
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = digic_uart_realize;
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dc->reset = digic_uart_reset;
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dc->vmsd = &vmstate_digic_uart;
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static const TypeInfo digic_uart_info = {
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.name = TYPE_DIGIC_UART,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(DigicUartState),
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.instance_init = digic_uart_init,
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.class_init = digic_uart_class_init,
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static void digic_uart_register_types(void)
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type_register_static(&digic_uart_info);
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type_init(digic_uart_register_types)