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Viewing changes to target-openrisc/mmu.c

  • Committer: Package Import Robot
  • Author(s): Serge Hallyn
  • Date: 2014-02-25 22:31:43 UTC
  • mfrom: (1.8.5)
  • Revision ID: package-import@ubuntu.com-20140225223143-odhqxfc60wxrjl15
Tags: 2.0.0~rc1+dfsg-0ubuntu1
https://launchpad.net/bugs/1294823
https://launchpad.net/bugs/1295072
* Merge 2.0.0-rc1
* debian/rules: consolidate ppc filter entries.
* Move qemu-system-arch64 into qemu-system-arm
* debian/patches/define-trusty-machine-type.patch: define a trusty machine
  type, currently the same as pc-i440fx-2.0, to put is in a better position
  to enable live migrations from trusty onward.  (LP: #1294823)
* debian/control: build-dep on libfdt >= 1.4.0  (LP: #1295072)
* Merge latest upstream git to commit dc9528f
* Debian/rules:
  - remove -enable-uname-release=2.6.32
  - don't make the aarch64 target Ubuntu-specific.
* Remove patches which are now upstream:
  - fix-smb-security-share.patch
  - slirp-smb-redirect-port-445-too.patch 
  - linux-user-Implement-sendmmsg-syscall.patch (better version is upstream)
  - signal-added-a-wrapper-for-sigprocmask-function.patch
  - ubuntu/signal-sigsegv-protection-on-do_sigprocmask.patch
  - ubuntu/Don-t-block-SIGSEGV-at-more-places.patch
  - ubuntu/ppc-force-cpu-threads-count-to-be-power-of-2.patch
* add link for /usr/share/qemu/bios-256k.bin
* Remove all linaro patches.
* Remove all arm64/ patches.  Many but not all are upstream.
* Remove CVE-2013-4377.patch which is upstream.
* debian/control-in: don't make qemu-system-aarch64 ubuntu-specific

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Lines of Context:
target-openrisc/mmu.c
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                                             target_ulong address,
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                                             int rw, int tlb_error)
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{
 
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    CPUState *cs = CPU(cpu);
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    int exception = 0;
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    switch (tlb_error) {
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#endif
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    }
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    cpu->env.exception_index = exception;
 
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    cs->exception_index = exception;
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    cpu->env.eear = address;
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}
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#ifndef CONFIG_USER_ONLY
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int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
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                                  target_ulong address, int rw, int mmu_idx)
 
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int openrisc_cpu_handle_mmu_fault(CPUState *cs,
 
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                                  vaddr address, int rw, int mmu_idx)
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{
 
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    OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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    int ret = 0;
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    hwaddr physical = 0;
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    int prot = 0;
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    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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    ret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot,
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                                     address, rw);
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    if (ret == TLBRET_MATCH) {
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        tlb_set_page(env, address & TARGET_PAGE_MASK,
 
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        tlb_set_page(cs, address & TARGET_PAGE_MASK,
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                     physical & TARGET_PAGE_MASK, prot,
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                     mmu_idx, TARGET_PAGE_SIZE);
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        ret = 0;
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    return ret;
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}
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#else
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int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
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                                  target_ulong address, int rw, int mmu_idx)
 
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int openrisc_cpu_handle_mmu_fault(CPUState *cs,
 
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                                  vaddr address, int rw, int mmu_idx)
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{
 
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    OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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    int ret = 0;
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    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
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    cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
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    ret = 1;