236
236
POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
237
237
POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
238
238
POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
239
/* VSX Unavailable (Power ISA 2.06 and later) */
240
POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
240
242
POWERPC_EXCP_NB = 96,
241
243
/* QEMU exceptions: used internally during code translation */
332
334
void (*hea_write)(void *opaque, int spr_num, int gpr_num);
334
336
const char *name;
337
target_ulong default_value;
335
338
#ifdef CONFIG_KVM
336
339
/* We (ab)use the fact that all the SPRs will have ids for the
337
340
* ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
427
434
#define MSR_VR 25 /* altivec available x hflags */
428
435
#define MSR_SPE 25 /* SPE enable for BookE x hflags */
429
436
#define MSR_AP 23 /* Access privilege state on 602 hflags */
437
#define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
430
438
#define MSR_SA 22 /* Supervisor access mode on 602 hflags */
431
439
#define MSR_KEY 19 /* key bit on 603e */
432
440
#define MSR_POW 18 /* Power management */
467
475
#define msr_vr ((env->msr >> MSR_VR) & 1)
468
476
#define msr_spe ((env->msr >> MSR_SPE) & 1)
469
477
#define msr_ap ((env->msr >> MSR_AP) & 1)
478
#define msr_vsx ((env->msr >> MSR_VSX) & 1)
470
479
#define msr_sa ((env->msr >> MSR_SA) & 1)
471
480
#define msr_key ((env->msr >> MSR_KEY) & 1)
472
481
#define msr_pow ((env->msr >> MSR_POW) & 1)
549
558
POWERPC_FLAG_BUS_CLK = 0x00020000,
551
560
POWERPC_FLAG_CFAR = 0x00040000,
562
POWERPC_FLAG_VSX = 0x00080000,
554
565
/*****************************************************************************/
920
931
target_ulong reserve_addr;
921
932
/* Reservation value */
922
933
target_ulong reserve_val;
934
target_ulong reserve_val2;
923
935
/* Reservation store address */
924
936
target_ulong reserve_ea;
925
937
/* Reserved store source register and size */
1100
1113
void ppc_hw_interrupt (CPUPPCState *env);
1101
1114
#if defined(CONFIG_USER_ONLY)
1102
int cpu_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
1115
int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1106
1119
#if !defined(CONFIG_USER_ONLY)
1244
1257
#define SPR_MPC_EIE (0x050)
1245
1258
#define SPR_MPC_EID (0x051)
1246
1259
#define SPR_MPC_NRI (0x052)
1247
#define SPR_CTRL (0x088)
1260
#define SPR_UCTRL (0x088)
1248
1261
#define SPR_MPC_CMPA (0x090)
1249
1262
#define SPR_MPC_CMPB (0x091)
1250
1263
#define SPR_MPC_CMPC (0x092)
1253
1266
#define SPR_MPC_DER (0x095)
1254
1267
#define SPR_MPC_COUNTA (0x096)
1255
1268
#define SPR_MPC_COUNTB (0x097)
1256
#define SPR_UCTRL (0x098)
1269
#define SPR_CTRL (0x098)
1257
1270
#define SPR_MPC_CMPE (0x098)
1258
1271
#define SPR_MPC_CMPF (0x099)
1259
1272
#define SPR_MPC_CMPG (0x09A)
1316
1329
#define SPR_BOOKE_IAC3 (0x13A)
1317
1330
#define SPR_HSRR1 (0x13B)
1318
1331
#define SPR_BOOKE_IAC4 (0x13B)
1319
#define SPR_LPCR (0x13C)
1320
1332
#define SPR_BOOKE_DAC1 (0x13C)
1321
1333
#define SPR_LPIDR (0x13D)
1322
1334
#define SPR_DABR2 (0x13D)
1323
1335
#define SPR_BOOKE_DAC2 (0x13D)
1324
1336
#define SPR_BOOKE_DVC1 (0x13E)
1337
#define SPR_LPCR (0x13E)
1325
1338
#define SPR_BOOKE_DVC2 (0x13F)
1326
1339
#define SPR_BOOKE_TSR (0x150)
1327
1340
#define SPR_BOOKE_TCR (0x154)
1502
1515
#define SPR_RCPU_L2U_RA2 (0x32A)
1503
1516
#define SPR_MPC_MD_DBRAM1 (0x32A)
1504
1517
#define SPR_RCPU_L2U_RA3 (0x32B)
1518
#define SPR_TAR (0x32F)
1505
1519
#define SPR_440_INV0 (0x370)
1506
1520
#define SPR_440_INV1 (0x371)
1507
1521
#define SPR_440_INV2 (0x372)
1869
1883
PPC2_DBRX = 0x0000000000000010ULL,
1870
1884
/* Book I 2.05 PowerPC specification */
1871
1885
PPC2_ISA205 = 0x0000000000000020ULL,
1886
/* VSX additions in ISA 2.07 */
1887
PPC2_VSX207 = 0x0000000000000040ULL,
1888
/* ISA 2.06B bpermd */
1889
PPC2_PERM_ISA206 = 0x0000000000000080ULL,
1890
/* ISA 2.06B divide extended variants */
1891
PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
1892
/* ISA 2.06B larx/stcx. instructions */
1893
PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
1894
/* ISA 2.06B floating point integer conversion */
1895
PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
1896
/* ISA 2.06B floating point test instructions */
1897
PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
1898
/* ISA 2.07 bctar instruction */
1899
PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
1900
/* ISA 2.07 load/store quadword */
1901
PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
1902
/* ISA 2.07 Altivec */
1903
PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
1904
/* PowerISA 2.07 Book3s specification */
1905
PPC2_ISA207S = 0x0000000000008000ULL,
1873
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_DBRX | PPC2_ISA205)
1907
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
1908
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
1909
PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
1910
PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
1911
PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
1876
1915
/*****************************************************************************/
2136
2175
extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2138
static inline bool cpu_has_work(CPUState *cpu)
2140
PowerPCCPU *ppc_cpu = POWERPC_CPU(cpu);
2141
CPUPPCState *env = &ppc_cpu->env;
2143
return msr_ee && (cpu->interrupt_request & CPU_INTERRUPT_HARD);
2146
2177
#include "exec/exec-all.h"
2148
2179
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2182
* ppc_get_vcpu_dt_id:
2183
* @cs: a PowerPCCPU struct.
2185
* Returns a device-tree ID for a CPU.
2187
int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2190
* ppc_get_vcpu_by_dt_id:
2191
* @cpu_dt_id: a device tree id
2193
* Searches for a CPU by @cpu_dt_id.
2195
* Returns: a PowerPCCPU struct
2197
PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2150
2199
#endif /* !defined (__CPU_PPC_H__) */