220
220
#define CIRRUS_HOOK_NOT_HANDLED 0
221
221
#define CIRRUS_HOOK_HANDLED 1
223
#define ABS(a) ((signed)(a) > 0 ? a : -a)
225
#define BLTUNSAFE(s) \
227
( /* check dst is within bounds */ \
228
(s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
229
+ ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
232
( /* check src is within bounds */ \
233
(s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
234
+ ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
223
239
struct CirrusVGAState;
224
240
typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
225
241
uint8_t * dst, const uint8_t * src,
706
730
s->get_resolution((VGAState *)s, &width, &height);
709
sx = (src % (width * depth)) / depth;
710
sy = (src / (width * depth));
711
dx = (dst % (width *depth)) / depth;
712
dy = (dst / (width * depth));
733
sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
734
sy = (src / ABS(s->cirrus_blt_srcpitch));
735
dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
736
dy = (dst / ABS(s->cirrus_blt_dstpitch));
714
738
/* normalize width */
744
(*s->cirrus_rop) (s, s->vram_ptr + s->cirrus_blt_dstaddr,
745
s->vram_ptr + s->cirrus_blt_srcaddr,
768
(*s->cirrus_rop) (s, s->vram_ptr +
769
(s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
771
(s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
746
772
s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
747
773
s->cirrus_blt_width, s->cirrus_blt_height);
750
s->ds->dpy_copy(s->ds,
752
s->cirrus_blt_width / depth,
753
s->cirrus_blt_height);
776
qemu_console_copy(s->ds,
778
s->cirrus_blt_width / depth,
779
s->cirrus_blt_height);
755
781
/* we don't have to notify the display that this portion has
756
changed since dpy_copy implies this */
782
changed since qemu_console_copy implies this */
759
cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
760
s->cirrus_blt_dstpitch, s->cirrus_blt_width,
761
s->cirrus_blt_height);
784
cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
785
s->cirrus_blt_dstpitch, s->cirrus_blt_width,
786
s->cirrus_blt_height);
764
789
static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
766
if (s->ds->dpy_copy) {
767
cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
768
s->cirrus_blt_srcaddr - s->start_addr,
769
s->cirrus_blt_width, s->cirrus_blt_height);
771
(*s->cirrus_rop) (s, s->vram_ptr + s->cirrus_blt_dstaddr,
772
s->vram_ptr + s->cirrus_blt_srcaddr,
773
s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
774
s->cirrus_blt_width, s->cirrus_blt_height);
776
cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
777
s->cirrus_blt_dstpitch, s->cirrus_blt_width,
778
s->cirrus_blt_height);
794
cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
795
s->cirrus_blt_srcaddr - s->start_addr,
796
s->cirrus_blt_width, s->cirrus_blt_height);
802
819
/* at least one scan line */
804
(*s->cirrus_rop)(s, s->vram_ptr + s->cirrus_blt_dstaddr,
805
s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
821
(*s->cirrus_rop)(s, s->vram_ptr +
822
(s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
823
s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
806
824
cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
807
825
s->cirrus_blt_width, 1);
808
826
s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
1202
1226
if (limit > 0) {
1227
/* Thinking about changing bank base? First, drop the dirty bitmap information
1228
* on the current location, otherwise we lose this pointer forever */
1229
if (s->lfb_vram_mapped) {
1230
target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1231
cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1203
1233
s->cirrus_bank_base[bank_index] = offset;
1204
1234
s->cirrus_bank_limit[bank_index] = limit;
1597
1629
case 0x17: // Standard VGA
1598
1630
case 0x18: // Standard VGA
1599
1631
return CIRRUS_HOOK_NOT_HANDLED;
1632
case 0x24: // Attribute Controller Toggle Readback (R)
1633
*reg_value = (s->ar_flip_flop << 7);
1600
1635
case 0x19: // Interlace End
1601
1636
case 0x1a: // Miscellaneous Control
1602
1637
case 0x1b: // Extended Display Control
1603
1638
case 0x1c: // Sync Adjust and Genlock
1604
1639
case 0x1d: // Overlay Extended Control
1605
1640
case 0x22: // Graphics Data Latches Readback (R)
1606
case 0x24: // Attribute Controller Toggle Readback (R)
1607
1641
case 0x25: // Part Status
1608
1642
case 0x27: // Part ID (R)
1609
1643
*reg_value = s->cr[reg_index];
2588
2622
cirrus_linear_bitblt_writel,
2625
static void map_linear_vram(CirrusVGAState *s)
2627
vga_dirty_log_stop((VGAState *)s);
2629
if (!s->map_addr && s->lfb_addr && s->lfb_end) {
2630
s->map_addr = s->lfb_addr;
2631
s->map_end = s->lfb_end;
2632
cpu_register_physical_memory(s->map_addr, s->map_end - s->map_addr, s->vram_offset);
2638
s->lfb_vram_mapped = 0;
2640
cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2641
(s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_UNASSIGNED);
2642
cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2643
(s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_UNASSIGNED);
2644
if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2645
&& !((s->sr[0x07] & 0x01) == 0)
2646
&& !((s->gr[0x0B] & 0x14) == 0x14)
2647
&& !(s->gr[0x0B] & 0x02)) {
2649
vga_dirty_log_stop((VGAState *)s);
2650
cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2651
(s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2652
cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2653
(s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2655
s->lfb_vram_mapped = 1;
2658
cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2662
vga_dirty_log_start((VGAState *)s);
2665
static void unmap_linear_vram(CirrusVGAState *s)
2667
vga_dirty_log_stop((VGAState *)s);
2669
if (s->map_addr && s->lfb_addr && s->lfb_end)
2670
s->map_addr = s->map_end = 0;
2672
cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2675
vga_dirty_log_start((VGAState *)s);
2591
2678
/* Compute the memory access functions */
2592
2679
static void cirrus_update_memory_access(CirrusVGAState *s)
3073
3176
***************************************/
3178
static void cirrus_reset(void *opaque)
3180
CirrusVGAState *s = opaque;
3183
unmap_linear_vram(s);
3185
if (s->device_id == CIRRUS_ID_CLGD5446) {
3186
/* 4MB 64 bit memory config, always PCI */
3187
s->sr[0x1F] = 0x2d; // MemClock
3188
s->gr[0x18] = 0x0f; // fastest memory configuration
3191
s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3193
s->sr[0x1F] = 0x22; // MemClock
3194
s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3195
s->sr[0x17] = s->bustype;
3196
s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3198
s->cr[0x27] = s->device_id;
3200
/* Win2K seems to assume that the pattern buffer is at 0xff
3202
memset(s->vram_ptr, 0xff, s->real_vram_size);
3204
s->cirrus_hidden_dac_lockindex = 5;
3205
s->cirrus_hidden_dac_data = 0;
3075
3208
static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3077
int vga_io_memory, i;
3078
3211
static int inited;
3113
3251
register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3114
3252
register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3116
vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3254
s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3117
3255
cirrus_vga_mem_write, s);
3118
3256
cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3122
if (device_id == CIRRUS_ID_CLGD5446) {
3123
/* 4MB 64 bit memory config, always PCI */
3124
s->sr[0x1F] = 0x2d; // MemClock
3125
s->gr[0x18] = 0x0f; // fastest memory configuration
3129
s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3130
s->real_vram_size = 4096 * 1024;
3134
s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3135
s->real_vram_size = 2048 * 1024;
3138
s->sr[0x1F] = 0x22; // MemClock
3139
s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3141
s->sr[0x17] = CIRRUS_BUSTYPE_PCI;
3143
s->sr[0x17] = CIRRUS_BUSTYPE_ISA;
3144
s->real_vram_size = 2048 * 1024;
3145
s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3147
s->cr[0x27] = device_id;
3149
/* Win2K seems to assume that the pattern buffer is at 0xff
3151
memset(s->vram_ptr, 0xff, s->real_vram_size);
3153
s->cirrus_hidden_dac_lockindex = 5;
3154
s->cirrus_hidden_dac_data = 0;
3258
qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3156
3260
/* I/O handler for LFB */
3157
3261
s->cirrus_linear_io_addr =
3158
cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write,
3262
cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write, s);
3160
3263
s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3162
3265
/* I/O handler for LFB */
3163
3266
s->cirrus_linear_bitblt_io_addr =
3164
cpu_register_io_memory(0, cirrus_linear_bitblt_read, cirrus_linear_bitblt_write,
3267
cpu_register_io_memory(0, cirrus_linear_bitblt_read,
3268
cirrus_linear_bitblt_write, s);
3167
3270
/* I/O handler for memory-mapped I/O */
3168
3271
s->cirrus_mmio_io_addr =
3169
cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3272
cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3275
(s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3171
3277
/* XXX: s->vram_size must be a power of two */
3172
3278
s->cirrus_addr_mask = s->real_vram_size - 1;
3188
3296
***************************************/
3190
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
3191
unsigned long vga_ram_offset, int vga_ram_size)
3298
void isa_cirrus_vga_init(uint8_t *vga_ram_base,
3299
ram_addr_t vga_ram_offset, int vga_ram_size)
3193
3301
CirrusVGAState *s;
3195
3303
s = qemu_mallocz(sizeof(CirrusVGAState));
3197
3305
vga_common_init((VGAState *)s,
3198
ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3306
vga_ram_base, vga_ram_offset, vga_ram_size);
3199
3307
cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3308
s->ds = graphic_console_init(s->update, s->invalidate,
3309
s->screen_dump, s->text_update, s);
3200
3310
/* XXX ISA-LFB support */
3212
3322
CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3324
vga_dirty_log_stop((VGAState *)s);
3214
3326
/* XXX: add byte swapping apertures */
3215
3327
cpu_register_physical_memory(addr, s->vram_size,
3216
3328
s->cirrus_linear_io_addr);
3217
3329
cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3218
3330
s->cirrus_linear_bitblt_io_addr);
3332
s->map_addr = s->map_end = 0;
3333
s->lfb_addr = addr & TARGET_PAGE_MASK;
3334
s->lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3335
/* account for overflow */
3336
if (s->lfb_end < addr + VGA_RAM_SIZE)
3337
s->lfb_end = addr + VGA_RAM_SIZE;
3339
vga_dirty_log_start((VGAState *)s);
3221
3342
static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3227
3348
s->cirrus_mmio_io_addr);
3230
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
3231
unsigned long vga_ram_offset, int vga_ram_size)
3351
static void pci_cirrus_write_config(PCIDevice *d,
3352
uint32_t address, uint32_t val, int len)
3354
PCICirrusVGAState *pvs = container_of(d, PCICirrusVGAState, dev);
3355
CirrusVGAState *s = &pvs->cirrus_vga;
3357
vga_dirty_log_stop((VGAState *)s);
3359
pci_default_write_config(d, address, val, len);
3360
if (s->map_addr && pvs->dev.io_regions[0].addr == -1)
3362
cirrus_update_memory_access(s);
3364
vga_dirty_log_start((VGAState *)s);
3367
void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
3368
ram_addr_t vga_ram_offset, int vga_ram_size)
3233
3370
PCICirrusVGAState *d;
3234
3371
uint8_t *pci_conf;
3240
3377
/* setup PCI configuration registers */
3241
3378
d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3242
3379
sizeof(PCICirrusVGAState),
3380
-1, NULL, pci_cirrus_write_config);
3244
3381
pci_conf = d->dev.config;
3245
pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
3246
pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
3247
pci_conf[0x02] = (uint8_t) (device_id & 0xff);
3248
pci_conf[0x03] = (uint8_t) (device_id >> 8);
3382
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
3383
pci_config_set_device_id(pci_conf, device_id);
3249
3384
pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3250
pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3251
pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
3385
pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
3252
3386
pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3254
3388
/* setup VGA */
3255
3389
s = &d->cirrus_vga;
3256
3390
vga_common_init((VGAState *)s,
3257
ds, vga_ram_base, vga_ram_offset, vga_ram_size);
3391
vga_ram_base, vga_ram_offset, vga_ram_size);
3258
3392
cirrus_init_common(s, device_id, 1);
3260
graphic_console_init(s->ds, s->update, s->invalidate, s->screen_dump, s);
3394
s->ds = graphic_console_init(s->update, s->invalidate,
3395
s->screen_dump, s->text_update, s);
3262
3397
s->pci_dev = (PCIDevice *)d;