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- Committer: Bazaar Package Importer
- Author(s): Aurelien Jarno, Aurelien Jarno
- Date: 2009-03-22 10:13:17 UTC
- mfrom: (1.2.1 upstream) (6.1.1 sid)
- Revision ID: james.westby@ubuntu.com-20090322101317-iigjtnu5qil35dtb
Tags: 0.10.1-1
[ Aurelien Jarno ]
* New upstream stable release:
- patches/80_stable-branch.patch: remove.
* debian/control:
- Remove depends on proll.
- Move depends on device-tree-compiler to build-depends.
- Bump Standards-Version to 3.8.1 (no changes).
* patches/82_qemu-img_decimal.patch: new patch from upstream to make
qemu-img accept sizes with decimal values (closes: bug#501400).
* New upstream stable release:
- patches/80_stable-branch.patch: remove.
* debian/control:
- Remove depends on proll.
- Move depends on device-tree-compiler to build-depends.
- Bump Standards-Version to 3.8.1 (no changes).
* patches/82_qemu-img_decimal.patch: new patch from upstream to make
qemu-img accept sizes with decimal values (closes: bug#501400).
- files added:
- MAINTAINERS
- bsd-user
- bsd-user/freebsd
- bsd-user/netbsd
- bsd-user/openbsd
- bsd-user/sparc
- bsd-user/sparc64
- debian/patches/security
- gdb-xml
- linux-user/arm/nwfpe
- pc-bios/bios-pq
- pc-bios/vgabios-pq
- tcg
- tcg/arm
- tcg/hppa
- tcg/i386
- tcg/ppc
- tcg/ppc64
- tcg/sparc
- tcg/x86_64
- tests/alpha
- files removed:
- audio/sys-queue.h
- linux-user/ppc64
- target-arm/nwfpe
- files modified:
- COPYING
- linux-user/elfload32.c *
added
removed
target-sparc/translate.c
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16
17
17
You should have received a copy of the GNU Lesser General Public
18
18
License along with this library; if not, write to the Free Software
19
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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*/
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21
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/*
23
TODO-list:
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25
Rest of V9 instructions, VIS instructions
26
NPC/PC static optimisations (use JUMP_TB when possible)
27
Optimize synthetic instructions
28
*/
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30
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#include <stdarg.h>
31
23
#include <stdlib.h>
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24
#include <stdio.h>
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28
#include "cpu.h"
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29
#include "exec-all.h"
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30
#include "disas.h"
31
#include "helper.h"
32
#include "tcg-op.h"
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34
#define GEN_HELPER 1
35
#include "helper.h"
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36
40
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#define DEBUG_DISAS
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38
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#define JUMP_PC 2 /* dynamic pc value which takes only two values
44
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according to jump_pc[T2] */
45
42
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/* global register indexes */
44
static TCGv_ptr cpu_env, cpu_regwptr;
45
static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
46
static TCGv_i32 cpu_psr;
47
static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
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static TCGv cpu_y;
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#ifndef CONFIG_USER_ONLY
50
static TCGv cpu_tbr;
51
#endif
52
static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
53
#ifdef TARGET_SPARC64
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static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
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static TCGv cpu_gsr;
56
static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
57
static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
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static TCGv_i32 cpu_softint;
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#else
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static TCGv cpu_wim;
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#endif
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/* local register indexes (only used inside old micro ops) */
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static TCGv cpu_tmp0;
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static TCGv_i32 cpu_tmp32;
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static TCGv_i64 cpu_tmp64;
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/* Floating point registers */
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static TCGv_i32 cpu_fpr[TARGET_FPREGS];
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#include "gen-icount.h"
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46
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typedef struct DisasContext {
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target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */
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target_ulong npc; /* next PC: integer or DYNAMIC_PC or JUMP_PC */
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int is_br;
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int mem_idx;
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int fpu_enabled;
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int address_mask_32bit;
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struct TranslationBlock *tb;
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sparc_def_t *def;
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} DisasContext;
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82
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typedef struct sparc_def_t sparc_def_t;
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struct sparc_def_t {
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const unsigned char *name;
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target_ulong iu_version;
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uint32_t fpu_version;
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uint32_t mmu_version;
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uint32_t mmu_bm;
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};
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static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name);
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static uint16_t *gen_opc_ptr;
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static uint32_t *gen_opparam_ptr;
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extern FILE *logfile;
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extern int loglevel;
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enum {
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#define DEF(s,n,copy_size) INDEX_op_ ## s,
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#include "opc.h"
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#undef DEF
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NB_OPS
78
};
79
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#include "gen-op.h"
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// This function uses non-native bit order
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#define GET_FIELD(X, FROM, TO) \
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((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
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#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
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#ifdef TARGET_SPARC64
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#define FFPREG(r) (r)
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#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
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#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
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#else
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#define FFPREG(r) (r)
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#define DFPREG(r) (r & 0x1e)
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#define QFPREG(r) (r & 0x1c)
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#endif
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#ifdef USE_DIRECT_JUMP
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#define TBPARAM(x)
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#else
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#define TBPARAM(x) (long)(x)
105
#endif
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#define UA2005_HTRAP_MASK 0xff
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#define V8_TRAP_MASK 0x7f
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static int sign_extend(int x, int len)
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{
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#define IS_IMM (insn & (1<<13))
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static void disas_sparc_insn(DisasContext * dc);
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static GenOpFunc * const gen_op_movl_TN_reg[2][32] = {
118
{
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gen_op_movl_g0_T0,
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gen_op_movl_g1_T0,
121
gen_op_movl_g2_T0,
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gen_op_movl_g3_T0,
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gen_op_movl_g4_T0,
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gen_op_movl_g5_T0,
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gen_op_movl_g6_T0,
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gen_op_movl_g7_T0,
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gen_op_movl_o0_T0,
128
gen_op_movl_o1_T0,
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gen_op_movl_o2_T0,
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gen_op_movl_o3_T0,
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gen_op_movl_o4_T0,
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gen_op_movl_o5_T0,
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gen_op_movl_o6_T0,
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gen_op_movl_o7_T0,
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gen_op_movl_l0_T0,
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gen_op_movl_l1_T0,
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gen_op_movl_l2_T0,
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gen_op_movl_l3_T0,
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gen_op_movl_l4_T0,
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gen_op_movl_l5_T0,
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gen_op_movl_l6_T0,
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gen_op_movl_l7_T0,
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gen_op_movl_i0_T0,
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gen_op_movl_i1_T0,
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gen_op_movl_i2_T0,
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gen_op_movl_i3_T0,
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gen_op_movl_i4_T0,
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gen_op_movl_i5_T0,
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gen_op_movl_i6_T0,
150
gen_op_movl_i7_T0,
151
},
152
{
153
gen_op_movl_g0_T1,
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gen_op_movl_g1_T1,
155
gen_op_movl_g2_T1,
156
gen_op_movl_g3_T1,
157
gen_op_movl_g4_T1,
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gen_op_movl_g5_T1,
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gen_op_movl_g6_T1,
160
gen_op_movl_g7_T1,
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gen_op_movl_o0_T1,
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gen_op_movl_o1_T1,
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gen_op_movl_o2_T1,
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gen_op_movl_o3_T1,
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gen_op_movl_o4_T1,
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gen_op_movl_o5_T1,
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gen_op_movl_o6_T1,
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gen_op_movl_o7_T1,
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gen_op_movl_l0_T1,
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gen_op_movl_l1_T1,
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gen_op_movl_l2_T1,
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gen_op_movl_l3_T1,
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gen_op_movl_l4_T1,
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gen_op_movl_l5_T1,
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gen_op_movl_l6_T1,
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gen_op_movl_l7_T1,
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gen_op_movl_i0_T1,
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gen_op_movl_i1_T1,
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gen_op_movl_i2_T1,
180
gen_op_movl_i3_T1,
181
gen_op_movl_i4_T1,
182
gen_op_movl_i5_T1,
183
gen_op_movl_i6_T1,
184
gen_op_movl_i7_T1,
185
}
186
};
187
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static GenOpFunc * const gen_op_movl_reg_TN[3][32] = {
189
{
190
gen_op_movl_T0_g0,
191
gen_op_movl_T0_g1,
192
gen_op_movl_T0_g2,
193
gen_op_movl_T0_g3,
194
gen_op_movl_T0_g4,
195
gen_op_movl_T0_g5,
196
gen_op_movl_T0_g6,
197
gen_op_movl_T0_g7,
198
gen_op_movl_T0_o0,
199
gen_op_movl_T0_o1,
200
gen_op_movl_T0_o2,
201
gen_op_movl_T0_o3,
202
gen_op_movl_T0_o4,
203
gen_op_movl_T0_o5,
204
gen_op_movl_T0_o6,
205
gen_op_movl_T0_o7,
206
gen_op_movl_T0_l0,
207
gen_op_movl_T0_l1,
208
gen_op_movl_T0_l2,
209
gen_op_movl_T0_l3,
210
gen_op_movl_T0_l4,
211
gen_op_movl_T0_l5,
212
gen_op_movl_T0_l6,
213
gen_op_movl_T0_l7,
214
gen_op_movl_T0_i0,
215
gen_op_movl_T0_i1,
216
gen_op_movl_T0_i2,
217
gen_op_movl_T0_i3,
218
gen_op_movl_T0_i4,
219
gen_op_movl_T0_i5,
220
gen_op_movl_T0_i6,
221
gen_op_movl_T0_i7,
222
},
223
{
224
gen_op_movl_T1_g0,
225
gen_op_movl_T1_g1,
226
gen_op_movl_T1_g2,
227
gen_op_movl_T1_g3,
228
gen_op_movl_T1_g4,
229
gen_op_movl_T1_g5,
230
gen_op_movl_T1_g6,
231
gen_op_movl_T1_g7,
232
gen_op_movl_T1_o0,
233
gen_op_movl_T1_o1,
234
gen_op_movl_T1_o2,
235
gen_op_movl_T1_o3,
236
gen_op_movl_T1_o4,
237
gen_op_movl_T1_o5,
238
gen_op_movl_T1_o6,
239
gen_op_movl_T1_o7,
240
gen_op_movl_T1_l0,
241
gen_op_movl_T1_l1,
242
gen_op_movl_T1_l2,
243
gen_op_movl_T1_l3,
244
gen_op_movl_T1_l4,
245
gen_op_movl_T1_l5,
246
gen_op_movl_T1_l6,
247
gen_op_movl_T1_l7,
248
gen_op_movl_T1_i0,
249
gen_op_movl_T1_i1,
250
gen_op_movl_T1_i2,
251
gen_op_movl_T1_i3,
252
gen_op_movl_T1_i4,
253
gen_op_movl_T1_i5,
254
gen_op_movl_T1_i6,
255
gen_op_movl_T1_i7,
256
},
257
{
258
gen_op_movl_T2_g0,
259
gen_op_movl_T2_g1,
260
gen_op_movl_T2_g2,
261
gen_op_movl_T2_g3,
262
gen_op_movl_T2_g4,
263
gen_op_movl_T2_g5,
264
gen_op_movl_T2_g6,
265
gen_op_movl_T2_g7,
266
gen_op_movl_T2_o0,
267
gen_op_movl_T2_o1,
268
gen_op_movl_T2_o2,
269
gen_op_movl_T2_o3,
270
gen_op_movl_T2_o4,
271
gen_op_movl_T2_o5,
272
gen_op_movl_T2_o6,
273
gen_op_movl_T2_o7,
274
gen_op_movl_T2_l0,
275
gen_op_movl_T2_l1,
276
gen_op_movl_T2_l2,
277
gen_op_movl_T2_l3,
278
gen_op_movl_T2_l4,
279
gen_op_movl_T2_l5,
280
gen_op_movl_T2_l6,
281
gen_op_movl_T2_l7,
282
gen_op_movl_T2_i0,
283
gen_op_movl_T2_i1,
284
gen_op_movl_T2_i2,
285
gen_op_movl_T2_i3,
286
gen_op_movl_T2_i4,
287
gen_op_movl_T2_i5,
288
gen_op_movl_T2_i6,
289
gen_op_movl_T2_i7,
290
}
291
};
292
293
static GenOpFunc1 * const gen_op_movl_TN_im[3] = {
294
gen_op_movl_T0_im,
295
gen_op_movl_T1_im,
296
gen_op_movl_T2_im
297
};
298
299
// Sign extending version
300
static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
301
gen_op_movl_T0_sim,
302
gen_op_movl_T1_sim,
303
gen_op_movl_T2_sim
304
};
305
306
#ifdef TARGET_SPARC64
307
#define GEN32(func, NAME) \
308
static GenOpFunc * const NAME ## _table [64] = { \
309
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
310
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
311
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
312
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
313
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
314
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
315
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
316
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
317
NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0, \
318
NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0, \
319
NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0, \
320
NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0, \
321
}; \
322
static inline void func(int n) \
323
{ \
324
NAME ## _table[n](); \
325
}
326
#else
327
#define GEN32(func, NAME) \
328
static GenOpFunc *const NAME ## _table [32] = { \
329
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
330
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
331
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
332
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
333
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
334
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
335
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
336
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
337
}; \
338
static inline void func(int n) \
339
{ \
340
NAME ## _table[n](); \
341
}
342
#endif
343
344
115
/* floating point registers moves */
345
GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
346
GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
347
GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
348
GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
349
350
GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
351
GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
352
GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
353
GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
354
355
#if defined(CONFIG_USER_ONLY)
356
GEN32(gen_op_load_fpr_QT0, gen_op_load_fpr_QT0_fprf);
357
GEN32(gen_op_load_fpr_QT1, gen_op_load_fpr_QT1_fprf);
358
GEN32(gen_op_store_QT0_fpr, gen_op_store_QT0_fpr_fprf);
359
GEN32(gen_op_store_QT1_fpr, gen_op_store_QT1_fpr_fprf);
360
#endif
116
static void gen_op_load_fpr_DT0(unsigned int src)
117
{
118
tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) +
119
offsetof(CPU_DoubleU, l.upper));
120
tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
121
offsetof(CPU_DoubleU, l.lower));
122
}
123
124
static void gen_op_load_fpr_DT1(unsigned int src)
125
{
126
tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) +
127
offsetof(CPU_DoubleU, l.upper));
128
tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) +
129
offsetof(CPU_DoubleU, l.lower));
130
}
131
132
static void gen_op_store_DT0_fpr(unsigned int dst)
133
{
134
tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) +
135
offsetof(CPU_DoubleU, l.upper));
136
tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) +
137
offsetof(CPU_DoubleU, l.lower));
138
}
139
140
static void gen_op_load_fpr_QT0(unsigned int src)
141
{
142
tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) +
143
offsetof(CPU_QuadU, l.upmost));
144
tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
145
offsetof(CPU_QuadU, l.upper));
146
tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
147
offsetof(CPU_QuadU, l.lower));
148
tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
149
offsetof(CPU_QuadU, l.lowest));
150
}
151
152
static void gen_op_load_fpr_QT1(unsigned int src)
153
{
154
tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) +
155
offsetof(CPU_QuadU, l.upmost));
156
tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +
157
offsetof(CPU_QuadU, l.upper));
158
tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +
159
offsetof(CPU_QuadU, l.lower));
160
tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +
161
offsetof(CPU_QuadU, l.lowest));
162
}
163
164
static void gen_op_store_QT0_fpr(unsigned int dst)
165
{
166
tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) +
167
offsetof(CPU_QuadU, l.upmost));
168
tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +
169
offsetof(CPU_QuadU, l.upper));
170
tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +
171
offsetof(CPU_QuadU, l.lower));
172
tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +
173
offsetof(CPU_QuadU, l.lowest));
174
}
361
175
362
176
/* moves */
363
177
#ifdef CONFIG_USER_ONLY
365
179
#ifdef TARGET_SPARC64
366
180
#define hypervisor(dc) 0
367
181
#endif
368
#define gen_op_ldst(name) gen_op_##name##_raw()
369
182
#else
370
183
#define supervisor(dc) (dc->mem_idx >= 1)
371
184
#ifdef TARGET_SPARC64
372
185
#define hypervisor(dc) (dc->mem_idx == 2)
373
#define OP_LD_TABLE(width) \
374
static GenOpFunc * const gen_op_##width[] = { \
375
&gen_op_##width##_user, \
376
&gen_op_##width##_kernel, \
377
&gen_op_##width##_hypv, \
378
};
379
#else
380
#define OP_LD_TABLE(width) \
381
static GenOpFunc * const gen_op_##width[] = { \
382
&gen_op_##width##_user, \
383
&gen_op_##width##_kernel, \
384
};
385
#endif
386
#define gen_op_ldst(name) (*gen_op_##name[dc->mem_idx])()
387
#endif
388
389
#ifndef CONFIG_USER_ONLY
390
OP_LD_TABLE(ld);
391
OP_LD_TABLE(st);
392
OP_LD_TABLE(ldub);
393
OP_LD_TABLE(lduh);
394
OP_LD_TABLE(ldsb);
395
OP_LD_TABLE(ldsh);
396
OP_LD_TABLE(stb);
397
OP_LD_TABLE(sth);
398
OP_LD_TABLE(std);
399
OP_LD_TABLE(ldstub);
400
OP_LD_TABLE(swap);
401
OP_LD_TABLE(ldd);
402
OP_LD_TABLE(stf);
403
OP_LD_TABLE(stdf);
404
OP_LD_TABLE(ldf);
405
OP_LD_TABLE(lddf);
406
407
#ifdef TARGET_SPARC64
408
OP_LD_TABLE(lduw);
409
OP_LD_TABLE(ldsw);
410
OP_LD_TABLE(ldx);
411
OP_LD_TABLE(stx);
412
#endif
413
#endif
414
415
/* asi moves */
416
#ifdef TARGET_SPARC64
417
static inline void gen_ld_asi(int insn, int size, int sign)
418
{
419
int asi, offset;
420
421
if (IS_IMM) {
422
offset = GET_FIELD(insn, 25, 31);
423
gen_op_ld_asi_reg(offset, size, sign);
424
} else {
425
asi = GET_FIELD(insn, 19, 26);
426
gen_op_ld_asi(asi, size, sign);
427
}
428
}
429
430
static inline void gen_st_asi(int insn, int size)
431
{
432
int asi, offset;
433
434
if (IS_IMM) {
435
offset = GET_FIELD(insn, 25, 31);
436
gen_op_st_asi_reg(offset, size);
437
} else {
438
asi = GET_FIELD(insn, 19, 26);
439
gen_op_st_asi(asi, size);
440
}
441
}
442
443
static inline void gen_ldf_asi(int insn, int size, int rd)
444
{
445
int asi, offset;
446
447
if (IS_IMM) {
448
offset = GET_FIELD(insn, 25, 31);
449
gen_op_ldf_asi_reg(offset, size, rd);
450
} else {
451
asi = GET_FIELD(insn, 19, 26);
452
gen_op_ldf_asi(asi, size, rd);
453
}
454
}
455
456
static inline void gen_stf_asi(int insn, int size, int rd)
457
{
458
int asi, offset;
459
460
if (IS_IMM) {
461
offset = GET_FIELD(insn, 25, 31);
462
gen_op_stf_asi_reg(offset, size, rd);
463
} else {
464
asi = GET_FIELD(insn, 19, 26);
465
gen_op_stf_asi(asi, size, rd);
466
}
467
}
468
469
static inline void gen_swap_asi(int insn)
470
{
471
int asi, offset;
472
473
if (IS_IMM) {
474
offset = GET_FIELD(insn, 25, 31);
475
gen_op_swap_asi_reg(offset);
476
} else {
477
asi = GET_FIELD(insn, 19, 26);
478
gen_op_swap_asi(asi);
479
}
480
}
481
482
static inline void gen_ldstub_asi(int insn)
483
{
484
int asi, offset;
485
486
if (IS_IMM) {
487
offset = GET_FIELD(insn, 25, 31);
488
gen_op_ldstub_asi_reg(offset);
489
} else {
490
asi = GET_FIELD(insn, 19, 26);
491
gen_op_ldstub_asi(asi);
492
}
493
}
494
495
static inline void gen_ldda_asi(int insn)
496
{
497
int asi, offset;
498
499
if (IS_IMM) {
500
offset = GET_FIELD(insn, 25, 31);
501
gen_op_ldda_asi_reg(offset);
502
} else {
503
asi = GET_FIELD(insn, 19, 26);
504
gen_op_ldda_asi(asi);
505
}
506
}
507
508
static inline void gen_stda_asi(int insn)
509
{
510
int asi, offset;
511
512
if (IS_IMM) {
513
offset = GET_FIELD(insn, 25, 31);
514
gen_op_stda_asi_reg(offset);
515
} else {
516
asi = GET_FIELD(insn, 19, 26);
517
gen_op_stda_asi(asi);
518
}
519
}
520
521
static inline void gen_cas_asi(int insn)
522
{
523
int asi, offset;
524
525
if (IS_IMM) {
526
offset = GET_FIELD(insn, 25, 31);
527
gen_op_cas_asi_reg(offset);
528
} else {
529
asi = GET_FIELD(insn, 19, 26);
530
gen_op_cas_asi(asi);
531
}
532
}
533
534
static inline void gen_casx_asi(int insn)
535
{
536
int asi, offset;
537
538
if (IS_IMM) {
539
offset = GET_FIELD(insn, 25, 31);
540
gen_op_casx_asi_reg(offset);
541
} else {
542
asi = GET_FIELD(insn, 19, 26);
543
gen_op_casx_asi(asi);
544
}
545
}
546
547
#elif !defined(CONFIG_USER_ONLY)
548
549
static inline void gen_ld_asi(int insn, int size, int sign)
550
{
551
int asi;
552
553
asi = GET_FIELD(insn, 19, 26);
554
gen_op_ld_asi(asi, size, sign);
555
}
556
557
static inline void gen_st_asi(int insn, int size)
558
{
559
int asi;
560
561
asi = GET_FIELD(insn, 19, 26);
562
gen_op_st_asi(asi, size);
563
}
564
565
static inline void gen_ldstub_asi(int insn)
566
{
567
int asi;
568
569
asi = GET_FIELD(insn, 19, 26);
570
gen_op_ldstub_asi(asi);
571
}
572
573
static inline void gen_swap_asi(int insn)
574
{
575
int asi;
576
577
asi = GET_FIELD(insn, 19, 26);
578
gen_op_swap_asi(asi);
579
}
580
581
static inline void gen_ldda_asi(int insn)
582
{
583
int asi;
584
585
asi = GET_FIELD(insn, 19, 26);
586
gen_op_ld_asi(asi, 8, 0);
587
}
588
589
static inline void gen_stda_asi(int insn)
590
{
591
int asi;
592
593
asi = GET_FIELD(insn, 19, 26);
594
gen_op_st_asi(asi, 8);
595
}
596
#endif
597
598
static inline void gen_movl_imm_TN(int reg, uint32_t imm)
599
{
600
gen_op_movl_TN_im[reg](imm);
601
}
602
603
static inline void gen_movl_imm_T1(uint32_t val)
604
{
605
gen_movl_imm_TN(1, val);
606
}
607
608
static inline void gen_movl_imm_T0(uint32_t val)
609
{
610
gen_movl_imm_TN(0, val);
611
}
612
613
static inline void gen_movl_simm_TN(int reg, int32_t imm)
614
{
615
gen_op_movl_TN_sim[reg](imm);
616
}
617
618
static inline void gen_movl_simm_T1(int32_t val)
619
{
620
gen_movl_simm_TN(1, val);
621
}
622
623
static inline void gen_movl_simm_T0(int32_t val)
624
{
625
gen_movl_simm_TN(0, val);
626
}
627
628
static inline void gen_movl_reg_TN(int reg, int t)
629
{
630
if (reg)
631
gen_op_movl_reg_TN[t][reg] ();
632
else
633
gen_movl_imm_TN(t, 0);
634
}
635
636
static inline void gen_movl_reg_T0(int reg)
637
{
638
gen_movl_reg_TN(reg, 0);
639
}
640
641
static inline void gen_movl_reg_T1(int reg)
642
{
643
gen_movl_reg_TN(reg, 1);
644
}
645
646
static inline void gen_movl_reg_T2(int reg)
647
{
648
gen_movl_reg_TN(reg, 2);
649
}
650
651
static inline void gen_movl_TN_reg(int reg, int t)
652
{
653
if (reg)
654
gen_op_movl_TN_reg[t][reg] ();
655
}
656
657
static inline void gen_movl_T0_reg(int reg)
658
{
659
gen_movl_TN_reg(reg, 0);
660
}
661
662
static inline void gen_movl_T1_reg(int reg)
663
{
664
gen_movl_TN_reg(reg, 1);
665
}
666
667
static inline void gen_jmp_im(target_ulong pc)
668
{
669
#ifdef TARGET_SPARC64
670
if (pc == (uint32_t)pc) {
671
gen_op_jmp_im(pc);
672
} else {
673
gen_op_jmp_im64(pc >> 32, pc);
674
}
675
#else
676
gen_op_jmp_im(pc);
677
#endif
678
}
679
680
static inline void gen_movl_npc_im(target_ulong npc)
681
{
682
#ifdef TARGET_SPARC64
683
if (npc == (uint32_t)npc) {
684
gen_op_movl_npc_im(npc);
685
} else {
686
gen_op_movq_npc_im64(npc >> 32, npc);
687
}
688
#else
689
gen_op_movl_npc_im(npc);
690
#endif
186
#else
187
#endif
188
#endif
189
190
#ifdef TARGET_SPARC64
191
#ifndef TARGET_ABI32
192
#define AM_CHECK(dc) ((dc)->address_mask_32bit)
193
#else
194
#define AM_CHECK(dc) (1)
195
#endif
196
#endif
197
198
static inline void gen_address_mask(DisasContext *dc, TCGv addr)
199
{
200
#ifdef TARGET_SPARC64
201
if (AM_CHECK(dc))
202
tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
203
#endif
204
}
205
206
static inline void gen_movl_reg_TN(int reg, TCGv tn)
207
{
208
if (reg == 0)
209
tcg_gen_movi_tl(tn, 0);
210
else if (reg < 8)
211
tcg_gen_mov_tl(tn, cpu_gregs[reg]);
212
else {
213
tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
214
}
215
}
216
217
static inline void gen_movl_TN_reg(int reg, TCGv tn)
218
{
219
if (reg == 0)
220
return;
221
else if (reg < 8)
222
tcg_gen_mov_tl(cpu_gregs[reg], tn);
223
else {
224
tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
225
}
691
226
}
692
227
693
228
static inline void gen_goto_tb(DisasContext *s, int tb_num,
699
234
if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
700
235
(npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK)) {
701
236
/* jump to same page: we can use a direct jump */
702
if (tb_num == 0)
703
gen_op_goto_tb0(TBPARAM(tb));
704
else
705
gen_op_goto_tb1(TBPARAM(tb));
706
gen_jmp_im(pc);
707
gen_movl_npc_im(npc);
708
gen_op_movl_T0_im((long)tb + tb_num);
709
gen_op_exit_tb();
237
tcg_gen_goto_tb(tb_num);
238
tcg_gen_movi_tl(cpu_pc, pc);
239
tcg_gen_movi_tl(cpu_npc, npc);
240
tcg_gen_exit_tb((long)tb + tb_num);
710
241
} else {
711
242
/* jump to another page: currently not optimized */
712
gen_jmp_im(pc);
713
gen_movl_npc_im(npc);
714
gen_op_movl_T0_0();
715
gen_op_exit_tb();
243
tcg_gen_movi_tl(cpu_pc, pc);
244
tcg_gen_movi_tl(cpu_npc, npc);
245
tcg_gen_exit_tb(0);
716
246
}
717
247
}
718
248
249
// XXX suboptimal
250
static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)
251
{
252
tcg_gen_extu_i32_tl(reg, src);
253
tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);
254
tcg_gen_andi_tl(reg, reg, 0x1);
255
}
256
257
static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)
258
{
259
tcg_gen_extu_i32_tl(reg, src);
260
tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);
261
tcg_gen_andi_tl(reg, reg, 0x1);
262
}
263
264
static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)
265
{
266
tcg_gen_extu_i32_tl(reg, src);
267
tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);
268
tcg_gen_andi_tl(reg, reg, 0x1);
269
}
270
271
static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
272
{
273
tcg_gen_extu_i32_tl(reg, src);
274
tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);
275
tcg_gen_andi_tl(reg, reg, 0x1);
276
}
277
278
static inline void gen_cc_clear_icc(void)
279
{
280
tcg_gen_movi_i32(cpu_psr, 0);
281
}
282
283
#ifdef TARGET_SPARC64
284
static inline void gen_cc_clear_xcc(void)
285
{
286
tcg_gen_movi_i32(cpu_xcc, 0);
287
}
288
#endif
289
290
/* old op:
291
if (!T0)
292
env->psr |= PSR_ZERO;
293
if ((int32_t) T0 < 0)
294
env->psr |= PSR_NEG;
295
*/
296
static inline void gen_cc_NZ_icc(TCGv dst)
297
{
298
TCGv r_temp;
299
int l1, l2;
300
301
l1 = gen_new_label();
302
l2 = gen_new_label();
303
r_temp = tcg_temp_new();
304
tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
305
tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
306
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
307
gen_set_label(l1);
308
tcg_gen_ext32s_tl(r_temp, dst);
309
tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);
310
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
311
gen_set_label(l2);
312
tcg_temp_free(r_temp);
313
}
314
315
#ifdef TARGET_SPARC64
316
static inline void gen_cc_NZ_xcc(TCGv dst)
317
{
318
int l1, l2;
319
320
l1 = gen_new_label();
321
l2 = gen_new_label();
322
tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);
323
tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
324
gen_set_label(l1);
325
tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);
326
tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
327
gen_set_label(l2);
328
}
329
#endif
330
331
/* old op:
332
if (T0 < src1)
333
env->psr |= PSR_CARRY;
334
*/
335
static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
336
{
337
TCGv r_temp1, r_temp2;
338
int l1;
339
340
l1 = gen_new_label();
341
r_temp1 = tcg_temp_new();
342
r_temp2 = tcg_temp_new();
343
tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL);
344
tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL);
345
tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
346
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
347
gen_set_label(l1);
348
tcg_temp_free(r_temp1);
349
tcg_temp_free(r_temp2);
350
}
351
352
#ifdef TARGET_SPARC64
353
static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
354
{
355
int l1;
356
357
l1 = gen_new_label();
358
tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
359
tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
360
gen_set_label(l1);
361
}
362
#endif
363
364
/* old op:
365
if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
366
env->psr |= PSR_OVF;
367
*/
368
static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
369
{
370
TCGv r_temp;
371
372
r_temp = tcg_temp_new();
373
tcg_gen_xor_tl(r_temp, src1, src2);
374
tcg_gen_not_tl(r_temp, r_temp);
375
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
376
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
377
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
378
tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
379
tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
380
tcg_temp_free(r_temp);
381
tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
382
}
383
384
#ifdef TARGET_SPARC64
385
static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
386
{
387
TCGv r_temp;
388
389
r_temp = tcg_temp_new();
390
tcg_gen_xor_tl(r_temp, src1, src2);
391
tcg_gen_not_tl(r_temp, r_temp);
392
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
393
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
394
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
395
tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
396
tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
397
tcg_temp_free(r_temp);
398
tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
399
}
400
#endif
401
402
static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
403
{
404
TCGv r_temp;
405
TCGv_i32 r_const;
406
int l1;
407
408
l1 = gen_new_label();
409
410
r_temp = tcg_temp_new();
411
tcg_gen_xor_tl(r_temp, src1, src2);
412
tcg_gen_not_tl(r_temp, r_temp);
413
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
414
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
415
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
416
tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
417
r_const = tcg_const_i32(TT_TOVF);
418
gen_helper_raise_exception(r_const);
419
tcg_temp_free_i32(r_const);
420
gen_set_label(l1);
421
tcg_temp_free(r_temp);
422
}
423
424
static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
425
{
426
int l1;
427
428
l1 = gen_new_label();
429
tcg_gen_or_tl(cpu_tmp0, src1, src2);
430
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
431
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
432
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
433
gen_set_label(l1);
434
}
435
436
static inline void gen_tag_tv(TCGv src1, TCGv src2)
437
{
438
int l1;
439
TCGv_i32 r_const;
440
441
l1 = gen_new_label();
442
tcg_gen_or_tl(cpu_tmp0, src1, src2);
443
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
444
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
445
r_const = tcg_const_i32(TT_TOVF);
446
gen_helper_raise_exception(r_const);
447
tcg_temp_free_i32(r_const);
448
gen_set_label(l1);
449
}
450
451
static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
452
{
453
tcg_gen_mov_tl(cpu_cc_src, src1);
454
tcg_gen_mov_tl(cpu_cc_src2, src2);
455
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
456
gen_cc_clear_icc();
457
gen_cc_NZ_icc(cpu_cc_dst);
458
gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
459
gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
460
#ifdef TARGET_SPARC64
461
gen_cc_clear_xcc();
462
gen_cc_NZ_xcc(cpu_cc_dst);
463
gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
464
gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
465
#endif
466
tcg_gen_mov_tl(dst, cpu_cc_dst);
467
}
468
469
static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
470
{
471
tcg_gen_mov_tl(cpu_cc_src, src1);
472
tcg_gen_mov_tl(cpu_cc_src2, src2);
473
gen_mov_reg_C(cpu_tmp0, cpu_psr);
474
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
475
gen_cc_clear_icc();
476
gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
477
#ifdef TARGET_SPARC64
478
gen_cc_clear_xcc();
479
gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
480
#endif
481
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
482
gen_cc_NZ_icc(cpu_cc_dst);
483
gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
484
gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
485
#ifdef TARGET_SPARC64
486
gen_cc_NZ_xcc(cpu_cc_dst);
487
gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
488
gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
489
#endif
490
tcg_gen_mov_tl(dst, cpu_cc_dst);
491
}
492
493
static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
494
{
495
tcg_gen_mov_tl(cpu_cc_src, src1);
496
tcg_gen_mov_tl(cpu_cc_src2, src2);
497
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
498
gen_cc_clear_icc();
499
gen_cc_NZ_icc(cpu_cc_dst);
500
gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
501
gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
502
gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
503
#ifdef TARGET_SPARC64
504
gen_cc_clear_xcc();
505
gen_cc_NZ_xcc(cpu_cc_dst);
506
gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
507
gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
508
#endif
509
tcg_gen_mov_tl(dst, cpu_cc_dst);
510
}
511
512
static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
513
{
514
tcg_gen_mov_tl(cpu_cc_src, src1);
515
tcg_gen_mov_tl(cpu_cc_src2, src2);
516
gen_tag_tv(cpu_cc_src, cpu_cc_src2);
517
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
518
gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
519
gen_cc_clear_icc();
520
gen_cc_NZ_icc(cpu_cc_dst);
521
gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
522
#ifdef TARGET_SPARC64
523
gen_cc_clear_xcc();
524
gen_cc_NZ_xcc(cpu_cc_dst);
525
gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
526
gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
527
#endif
528
tcg_gen_mov_tl(dst, cpu_cc_dst);
529
}
530
531
/* old op:
532
if (src1 < T1)
533
env->psr |= PSR_CARRY;
534
*/
535
static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
536
{
537
TCGv r_temp1, r_temp2;
538
int l1;
539
540
l1 = gen_new_label();
541
r_temp1 = tcg_temp_new();
542
r_temp2 = tcg_temp_new();
543
tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
544
tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
545
tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
546
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
547
gen_set_label(l1);
548
tcg_temp_free(r_temp1);
549
tcg_temp_free(r_temp2);
550
}
551
552
#ifdef TARGET_SPARC64
553
static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
554
{
555
int l1;
556
557
l1 = gen_new_label();
558
tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
559
tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
560
gen_set_label(l1);
561
}
562
#endif
563
564
/* old op:
565
if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
566
env->psr |= PSR_OVF;
567
*/
568
static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
569
{
570
TCGv r_temp;
571
572
r_temp = tcg_temp_new();
573
tcg_gen_xor_tl(r_temp, src1, src2);
574
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
575
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
576
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
577
tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);
578
tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
579
tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);
580
tcg_temp_free(r_temp);
581
}
582
583
#ifdef TARGET_SPARC64
584
static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
585
{
586
TCGv r_temp;
587
588
r_temp = tcg_temp_new();
589
tcg_gen_xor_tl(r_temp, src1, src2);
590
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
591
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
592
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
593
tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);
594
tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);
595
tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);
596
tcg_temp_free(r_temp);
597
}
598
#endif
599
600
static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
601
{
602
TCGv r_temp;
603
TCGv_i32 r_const;
604
int l1;
605
606
l1 = gen_new_label();
607
608
r_temp = tcg_temp_new();
609
tcg_gen_xor_tl(r_temp, src1, src2);
610
tcg_gen_xor_tl(cpu_tmp0, src1, dst);
611
tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
612
tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));
613
tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);
614
r_const = tcg_const_i32(TT_TOVF);
615
gen_helper_raise_exception(r_const);
616
tcg_temp_free_i32(r_const);
617
gen_set_label(l1);
618
tcg_temp_free(r_temp);
619
}
620
621
static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
622
{
623
tcg_gen_mov_tl(cpu_cc_src, src1);
624
tcg_gen_mov_tl(cpu_cc_src2, src2);
625
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
626
gen_cc_clear_icc();
627
gen_cc_NZ_icc(cpu_cc_dst);
628
gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
629
gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
630
#ifdef TARGET_SPARC64
631
gen_cc_clear_xcc();
632
gen_cc_NZ_xcc(cpu_cc_dst);
633
gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
634
gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
635
#endif
636
tcg_gen_mov_tl(dst, cpu_cc_dst);
637
}
638
639
static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
640
{
641
tcg_gen_mov_tl(cpu_cc_src, src1);
642
tcg_gen_mov_tl(cpu_cc_src2, src2);
643
gen_mov_reg_C(cpu_tmp0, cpu_psr);
644
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
645
gen_cc_clear_icc();
646
gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
647
#ifdef TARGET_SPARC64
648
gen_cc_clear_xcc();
649
gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
650
#endif
651
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
652
gen_cc_NZ_icc(cpu_cc_dst);
653
gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);
654
gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
655
#ifdef TARGET_SPARC64
656
gen_cc_NZ_xcc(cpu_cc_dst);
657
gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);
658
gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
659
#endif
660
tcg_gen_mov_tl(dst, cpu_cc_dst);
661
}
662
663
static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
664
{
665
tcg_gen_mov_tl(cpu_cc_src, src1);
666
tcg_gen_mov_tl(cpu_cc_src2, src2);
667
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
668
gen_cc_clear_icc();
669
gen_cc_NZ_icc(cpu_cc_dst);
670
gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
671
gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
672
gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);
673
#ifdef TARGET_SPARC64
674
gen_cc_clear_xcc();
675
gen_cc_NZ_xcc(cpu_cc_dst);
676
gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
677
gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
678
#endif
679
tcg_gen_mov_tl(dst, cpu_cc_dst);
680
}
681
682
static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
683
{
684
tcg_gen_mov_tl(cpu_cc_src, src1);
685
tcg_gen_mov_tl(cpu_cc_src2, src2);
686
gen_tag_tv(cpu_cc_src, cpu_cc_src2);
687
tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
688
gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
689
gen_cc_clear_icc();
690
gen_cc_NZ_icc(cpu_cc_dst);
691
gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
692
#ifdef TARGET_SPARC64
693
gen_cc_clear_xcc();
694
gen_cc_NZ_xcc(cpu_cc_dst);
695
gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
696
gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
697
#endif
698
tcg_gen_mov_tl(dst, cpu_cc_dst);
699
}
700
701
static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
702
{
703
TCGv r_temp;
704
int l1;
705
706
l1 = gen_new_label();
707
r_temp = tcg_temp_new();
708
709
/* old op:
710
if (!(env->y & 1))
711
T1 = 0;
712
*/
713
tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);
714
tcg_gen_andi_tl(r_temp, cpu_y, 0x1);
715
tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);
716
tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);
717
tcg_gen_movi_tl(cpu_cc_src2, 0);
718
gen_set_label(l1);
719
720
// b2 = T0 & 1;
721
// env->y = (b2 << 31) | (env->y >> 1);
722
tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
723
tcg_gen_shli_tl(r_temp, r_temp, 31);
724
tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
725
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);
726
tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);
727
tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
728
729
// b1 = N ^ V;
730
gen_mov_reg_N(cpu_tmp0, cpu_psr);
731
gen_mov_reg_V(r_temp, cpu_psr);
732
tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
733
tcg_temp_free(r_temp);
734
735
// T0 = (b1 << 31) | (T0 >> 1);
736
// src1 = T0;
737
tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
738
tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);
739
tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
740
741
/* do addition and update flags */
742
tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
743
744
gen_cc_clear_icc();
745
gen_cc_NZ_icc(cpu_cc_dst);
746
gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
747
gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
748
tcg_gen_mov_tl(dst, cpu_cc_dst);
749
}
750
751
static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
752
{
753
TCGv_i64 r_temp, r_temp2;
754
755
r_temp = tcg_temp_new_i64();
756
r_temp2 = tcg_temp_new_i64();
757
758
tcg_gen_extu_tl_i64(r_temp, src2);
759
tcg_gen_extu_tl_i64(r_temp2, src1);
760
tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
761
762
tcg_gen_shri_i64(r_temp, r_temp2, 32);
763
tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
764
tcg_temp_free_i64(r_temp);
765
tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
766
#ifdef TARGET_SPARC64
767
tcg_gen_mov_i64(dst, r_temp2);
768
#else
769
tcg_gen_trunc_i64_tl(dst, r_temp2);
770
#endif
771
tcg_temp_free_i64(r_temp2);
772
}
773
774
static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
775
{
776
TCGv_i64 r_temp, r_temp2;
777
778
r_temp = tcg_temp_new_i64();
779
r_temp2 = tcg_temp_new_i64();
780
781
tcg_gen_ext_tl_i64(r_temp, src2);
782
tcg_gen_ext_tl_i64(r_temp2, src1);
783
tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
784
785
tcg_gen_shri_i64(r_temp, r_temp2, 32);
786
tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
787
tcg_temp_free_i64(r_temp);
788
tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
789
#ifdef TARGET_SPARC64
790
tcg_gen_mov_i64(dst, r_temp2);
791
#else
792
tcg_gen_trunc_i64_tl(dst, r_temp2);
793
#endif
794
tcg_temp_free_i64(r_temp2);
795
}
796
797
#ifdef TARGET_SPARC64
798
static inline void gen_trap_ifdivzero_tl(TCGv divisor)
799
{
800
TCGv_i32 r_const;
801
int l1;
802
803
l1 = gen_new_label();
804
tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);
805
r_const = tcg_const_i32(TT_DIV_ZERO);
806
gen_helper_raise_exception(r_const);
807
tcg_temp_free_i32(r_const);
808
gen_set_label(l1);
809
}
810
811
static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
812
{
813
int l1, l2;
814
815
l1 = gen_new_label();
816
l2 = gen_new_label();
817
tcg_gen_mov_tl(cpu_cc_src, src1);
818
tcg_gen_mov_tl(cpu_cc_src2, src2);
819
gen_trap_ifdivzero_tl(cpu_cc_src2);
820
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);
821
tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);
822
tcg_gen_movi_i64(dst, INT64_MIN);
823
tcg_gen_br(l2);
824
gen_set_label(l1);
825
tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);
826
gen_set_label(l2);
827
}
828
#endif
829
830
static inline void gen_op_div_cc(TCGv dst)
831
{
832
int l1;
833
834
tcg_gen_mov_tl(cpu_cc_dst, dst);
835
gen_cc_clear_icc();
836
gen_cc_NZ_icc(cpu_cc_dst);
837
l1 = gen_new_label();
838
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);
839
tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
840
gen_set_label(l1);
841
}
842
843
static inline void gen_op_logic_cc(TCGv dst)
844
{
845
tcg_gen_mov_tl(cpu_cc_dst, dst);
846
847
gen_cc_clear_icc();
848
gen_cc_NZ_icc(cpu_cc_dst);
849
#ifdef TARGET_SPARC64
850
gen_cc_clear_xcc();
851
gen_cc_NZ_xcc(cpu_cc_dst);
852
#endif
853
}
854
855
// 1
856
static inline void gen_op_eval_ba(TCGv dst)
857
{
858
tcg_gen_movi_tl(dst, 1);
859
}
860
861
// Z
862
static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)
863
{
864
gen_mov_reg_Z(dst, src);
865
}
866
867
// Z | (N ^ V)
868
static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)
869
{
870
gen_mov_reg_N(cpu_tmp0, src);
871
gen_mov_reg_V(dst, src);
872
tcg_gen_xor_tl(dst, dst, cpu_tmp0);
873
gen_mov_reg_Z(cpu_tmp0, src);
874
tcg_gen_or_tl(dst, dst, cpu_tmp0);
875
}
876
877
// N ^ V
878
static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)
879
{
880
gen_mov_reg_V(cpu_tmp0, src);
881
gen_mov_reg_N(dst, src);
882
tcg_gen_xor_tl(dst, dst, cpu_tmp0);
883
}
884
885
// C | Z
886
static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)
887
{
888
gen_mov_reg_Z(cpu_tmp0, src);
889
gen_mov_reg_C(dst, src);
890
tcg_gen_or_tl(dst, dst, cpu_tmp0);
891
}
892
893
// C
894
static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)
895
{
896
gen_mov_reg_C(dst, src);
897
}
898
899
// V
900
static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)
901
{
902
gen_mov_reg_V(dst, src);
903
}
904
905
// 0
906
static inline void gen_op_eval_bn(TCGv dst)
907
{
908
tcg_gen_movi_tl(dst, 0);
909
}
910
911
// N
912
static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)
913
{
914
gen_mov_reg_N(dst, src);
915
}
916
917
// !Z
918
static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)
919
{
920
gen_mov_reg_Z(dst, src);
921
tcg_gen_xori_tl(dst, dst, 0x1);
922
}
923
924
// !(Z | (N ^ V))
925
static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)
926
{
927
gen_mov_reg_N(cpu_tmp0, src);
928
gen_mov_reg_V(dst, src);
929
tcg_gen_xor_tl(dst, dst, cpu_tmp0);
930
gen_mov_reg_Z(cpu_tmp0, src);
931
tcg_gen_or_tl(dst, dst, cpu_tmp0);
932
tcg_gen_xori_tl(dst, dst, 0x1);
933
}
934
935
// !(N ^ V)
936
static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)
937
{
938
gen_mov_reg_V(cpu_tmp0, src);
939
gen_mov_reg_N(dst, src);
940
tcg_gen_xor_tl(dst, dst, cpu_tmp0);
941
tcg_gen_xori_tl(dst, dst, 0x1);
942
}
943
944
// !(C | Z)
945
static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)
946
{
947
gen_mov_reg_Z(cpu_tmp0, src);
948
gen_mov_reg_C(dst, src);
949
tcg_gen_or_tl(dst, dst, cpu_tmp0);
950
tcg_gen_xori_tl(dst, dst, 0x1);
951
}
952
953
// !C
954
static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)
955
{
956
gen_mov_reg_C(dst, src);
957
tcg_gen_xori_tl(dst, dst, 0x1);
958
}
959
960
// !N
961
static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)
962
{
963
gen_mov_reg_N(dst, src);
964
tcg_gen_xori_tl(dst, dst, 0x1);
965
}
966
967
// !V
968
static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)
969
{
970
gen_mov_reg_V(dst, src);
971
tcg_gen_xori_tl(dst, dst, 0x1);
972
}
973
974
/*
975
FPSR bit field FCC1 | FCC0:
976
0 =
977
1 <
978
2 >
979
3 unordered
980
*/
981
static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
982
unsigned int fcc_offset)
983
{
984
tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);
985
tcg_gen_andi_tl(reg, reg, 0x1);
986
}
987
988
static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
989
unsigned int fcc_offset)
990
{
991
tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);
992
tcg_gen_andi_tl(reg, reg, 0x1);
993
}
994
995
// !0: FCC0 | FCC1
996
static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
997
unsigned int fcc_offset)
998
{
999
gen_mov_reg_FCC0(dst, src, fcc_offset);
1000
gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1001
tcg_gen_or_tl(dst, dst, cpu_tmp0);
1002
}
1003
1004
// 1 or 2: FCC0 ^ FCC1
1005
static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
1006
unsigned int fcc_offset)
1007
{
1008
gen_mov_reg_FCC0(dst, src, fcc_offset);
1009
gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1010
tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1011
}
1012
1013
// 1 or 3: FCC0
1014
static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1015
unsigned int fcc_offset)
1016
{
1017
gen_mov_reg_FCC0(dst, src, fcc_offset);
1018
}
1019
1020
// 1: FCC0 & !FCC1
1021
static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1022
unsigned int fcc_offset)
1023
{
1024
gen_mov_reg_FCC0(dst, src, fcc_offset);
1025
gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1026
tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1027
tcg_gen_and_tl(dst, dst, cpu_tmp0);
1028
}
1029
1030
// 2 or 3: FCC1
1031
static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1032
unsigned int fcc_offset)
1033
{
1034
gen_mov_reg_FCC1(dst, src, fcc_offset);
1035
}
1036
1037
// 2: !FCC0 & FCC1
1038
static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1039
unsigned int fcc_offset)
1040
{
1041
gen_mov_reg_FCC0(dst, src, fcc_offset);
1042
tcg_gen_xori_tl(dst, dst, 0x1);
1043
gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1044
tcg_gen_and_tl(dst, dst, cpu_tmp0);
1045
}
1046
1047
// 3: FCC0 & FCC1
1048
static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1049
unsigned int fcc_offset)
1050
{
1051
gen_mov_reg_FCC0(dst, src, fcc_offset);
1052
gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1053
tcg_gen_and_tl(dst, dst, cpu_tmp0);
1054
}
1055
1056
// 0: !(FCC0 | FCC1)
1057
static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1058
unsigned int fcc_offset)
1059
{
1060
gen_mov_reg_FCC0(dst, src, fcc_offset);
1061
gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1062
tcg_gen_or_tl(dst, dst, cpu_tmp0);
1063
tcg_gen_xori_tl(dst, dst, 0x1);
1064
}
1065
1066
// 0 or 3: !(FCC0 ^ FCC1)
1067
static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1068
unsigned int fcc_offset)
1069
{
1070
gen_mov_reg_FCC0(dst, src, fcc_offset);
1071
gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1072
tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1073
tcg_gen_xori_tl(dst, dst, 0x1);
1074
}
1075
1076
// 0 or 2: !FCC0
1077
static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1078
unsigned int fcc_offset)
1079
{
1080
gen_mov_reg_FCC0(dst, src, fcc_offset);
1081
tcg_gen_xori_tl(dst, dst, 0x1);
1082
}
1083
1084
// !1: !(FCC0 & !FCC1)
1085
static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1086
unsigned int fcc_offset)
1087
{
1088
gen_mov_reg_FCC0(dst, src, fcc_offset);
1089
gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1090
tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1091
tcg_gen_and_tl(dst, dst, cpu_tmp0);
1092
tcg_gen_xori_tl(dst, dst, 0x1);
1093
}
1094
1095
// 0 or 1: !FCC1
1096
static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1097
unsigned int fcc_offset)
1098
{
1099
gen_mov_reg_FCC1(dst, src, fcc_offset);
1100
tcg_gen_xori_tl(dst, dst, 0x1);
1101
}
1102
1103
// !2: !(!FCC0 & FCC1)
1104
static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1105
unsigned int fcc_offset)
1106
{
1107
gen_mov_reg_FCC0(dst, src, fcc_offset);
1108
tcg_gen_xori_tl(dst, dst, 0x1);
1109
gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1110
tcg_gen_and_tl(dst, dst, cpu_tmp0);
1111
tcg_gen_xori_tl(dst, dst, 0x1);
1112
}
1113
1114
// !3: !(FCC0 & FCC1)
1115
static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1116
unsigned int fcc_offset)
1117
{
1118
gen_mov_reg_FCC0(dst, src, fcc_offset);
1119
gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1120
tcg_gen_and_tl(dst, dst, cpu_tmp0);
1121
tcg_gen_xori_tl(dst, dst, 0x1);
1122
}
1123
719
1124
static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
720
target_ulong pc2)
1125
target_ulong pc2, TCGv r_cond)
721
1126
{
722
1127
int l1;
723
1128
724
1129
l1 = gen_new_label();
725
1130
726
gen_op_jz_T2_label(l1);
1131
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
727
1132
728
1133
gen_goto_tb(dc, 0, pc1, pc1 + 4);
729
1134
732
1137
}
733
1138
734
1139
static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
735
target_ulong pc2)
1140
target_ulong pc2, TCGv r_cond)
736
1141
{
737
1142
int l1;
738
1143
739
1144
l1 = gen_new_label();
740
1145
741
gen_op_jz_T2_label(l1);
1146
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
742
1147
743
1148
gen_goto_tb(dc, 0, pc2, pc1);
744
1149
746
1151
gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
747
1152
}
748
1153
749
static inline void gen_branch(DisasContext *dc, target_ulong pc,
750
target_ulong npc)
751
{
752
gen_goto_tb(dc, 0, pc, npc);
753
}
754
755
static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2)
1154
static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1155
TCGv r_cond)
756
1156
{
757
1157
int l1, l2;
758
1158
759
1159
l1 = gen_new_label();
760
1160
l2 = gen_new_label();
761
gen_op_jz_T2_label(l1);
762
763
gen_movl_npc_im(npc1);
764
gen_op_jmp_label(l2);
1161
1162
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
1163
1164
tcg_gen_movi_tl(cpu_npc, npc1);
1165
tcg_gen_br(l2);
765
1166
766
1167
gen_set_label(l1);
767
gen_movl_npc_im(npc2);
1168
tcg_gen_movi_tl(cpu_npc, npc2);
768
1169
gen_set_label(l2);
769
1170
}
770
1171
771
/* call this function before using T2 as it may have been set for a jump */
772
static inline void flush_T2(DisasContext * dc)
1172
/* call this function before using the condition register as it may
1173
have been set for a jump */
1174
static inline void flush_cond(DisasContext *dc, TCGv cond)
773
1175
{
774
1176
if (dc->npc == JUMP_PC) {
775
gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
1177
gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
776
1178
dc->npc = DYNAMIC_PC;
777
1179
}
778
1180
}
779
1181
780
static inline void save_npc(DisasContext * dc)
1182
static inline void save_npc(DisasContext *dc, TCGv cond)
781
1183
{
782
1184
if (dc->npc == JUMP_PC) {
783
gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
1185
gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
784
1186
dc->npc = DYNAMIC_PC;
785
1187
} else if (dc->npc != DYNAMIC_PC) {
786
gen_movl_npc_im(dc->npc);
1188
tcg_gen_movi_tl(cpu_npc, dc->npc);
787
1189
}
788
1190
}
789
1191
790
static inline void save_state(DisasContext * dc)
1192
static inline void save_state(DisasContext *dc, TCGv cond)
791
1193
{
792
gen_jmp_im(dc->pc);
793
save_npc(dc);
1194
tcg_gen_movi_tl(cpu_pc, dc->pc);
1195
save_npc(dc, cond);
794
1196
}
795
1197
796
static inline void gen_mov_pc_npc(DisasContext * dc)
1198
static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
797
1199
{
798
1200
if (dc->npc == JUMP_PC) {
799
gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
800
gen_op_mov_pc_npc();
1201
gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1202
tcg_gen_mov_tl(cpu_pc, cpu_npc);
801
1203
dc->pc = DYNAMIC_PC;
802
1204
} else if (dc->npc == DYNAMIC_PC) {
803
gen_op_mov_pc_npc();
1205
tcg_gen_mov_tl(cpu_pc, cpu_npc);
804
1206
dc->pc = DYNAMIC_PC;
805
1207
} else {
806
1208
dc->pc = dc->npc;
807
1209
}
808
1210
}
809
1211
810
static GenOpFunc * const gen_cond[2][16] = {
811
{
812
gen_op_eval_bn,
813
gen_op_eval_be,
814
gen_op_eval_ble,
815
gen_op_eval_bl,
816
gen_op_eval_bleu,
817
gen_op_eval_bcs,
818
gen_op_eval_bneg,
819
gen_op_eval_bvs,
820
gen_op_eval_ba,
821
gen_op_eval_bne,
822
gen_op_eval_bg,
823
gen_op_eval_bge,
824
gen_op_eval_bgu,
825
gen_op_eval_bcc,
826
gen_op_eval_bpos,
827
gen_op_eval_bvc,
828
},
829
{
830
#ifdef TARGET_SPARC64
831
gen_op_eval_bn,
832
gen_op_eval_xbe,
833
gen_op_eval_xble,
834
gen_op_eval_xbl,
835
gen_op_eval_xbleu,
836
gen_op_eval_xbcs,
837
gen_op_eval_xbneg,
838
gen_op_eval_xbvs,
839
gen_op_eval_ba,
840
gen_op_eval_xbne,
841
gen_op_eval_xbg,
842
gen_op_eval_xbge,
843
gen_op_eval_xbgu,
844
gen_op_eval_xbcc,
845
gen_op_eval_xbpos,
846
gen_op_eval_xbvc,
847
#endif
848
},
849
};
850
851
static GenOpFunc * const gen_fcond[4][16] = {
852
{
853
gen_op_eval_bn,
854
gen_op_eval_fbne,
855
gen_op_eval_fblg,
856
gen_op_eval_fbul,
857
gen_op_eval_fbl,
858
gen_op_eval_fbug,
859
gen_op_eval_fbg,
860
gen_op_eval_fbu,
861
gen_op_eval_ba,
862
gen_op_eval_fbe,
863
gen_op_eval_fbue,
864
gen_op_eval_fbge,
865
gen_op_eval_fbuge,
866
gen_op_eval_fble,
867
gen_op_eval_fbule,
868
gen_op_eval_fbo,
869
},
870
#ifdef TARGET_SPARC64
871
{
872
gen_op_eval_bn,
873
gen_op_eval_fbne_fcc1,
874
gen_op_eval_fblg_fcc1,
875
gen_op_eval_fbul_fcc1,
876
gen_op_eval_fbl_fcc1,
877
gen_op_eval_fbug_fcc1,
878
gen_op_eval_fbg_fcc1,
879
gen_op_eval_fbu_fcc1,
880
gen_op_eval_ba,
881
gen_op_eval_fbe_fcc1,
882
gen_op_eval_fbue_fcc1,
883
gen_op_eval_fbge_fcc1,
884
gen_op_eval_fbuge_fcc1,
885
gen_op_eval_fble_fcc1,
886
gen_op_eval_fbule_fcc1,
887
gen_op_eval_fbo_fcc1,
888
},
889
{
890
gen_op_eval_bn,
891
gen_op_eval_fbne_fcc2,
892
gen_op_eval_fblg_fcc2,
893
gen_op_eval_fbul_fcc2,
894
gen_op_eval_fbl_fcc2,
895
gen_op_eval_fbug_fcc2,
896
gen_op_eval_fbg_fcc2,
897
gen_op_eval_fbu_fcc2,
898
gen_op_eval_ba,
899
gen_op_eval_fbe_fcc2,
900
gen_op_eval_fbue_fcc2,
901
gen_op_eval_fbge_fcc2,
902
gen_op_eval_fbuge_fcc2,
903
gen_op_eval_fble_fcc2,
904
gen_op_eval_fbule_fcc2,
905
gen_op_eval_fbo_fcc2,
906
},
907
{
908
gen_op_eval_bn,
909
gen_op_eval_fbne_fcc3,
910
gen_op_eval_fblg_fcc3,
911
gen_op_eval_fbul_fcc3,
912
gen_op_eval_fbl_fcc3,
913
gen_op_eval_fbug_fcc3,
914
gen_op_eval_fbg_fcc3,
915
gen_op_eval_fbu_fcc3,
916
gen_op_eval_ba,
917
gen_op_eval_fbe_fcc3,
918
gen_op_eval_fbue_fcc3,
919
gen_op_eval_fbge_fcc3,
920
gen_op_eval_fbuge_fcc3,
921
gen_op_eval_fble_fcc3,
922
gen_op_eval_fbule_fcc3,
923
gen_op_eval_fbo_fcc3,
924
},
1212
static inline void gen_op_next_insn(void)
1213
{
1214
tcg_gen_mov_tl(cpu_pc, cpu_npc);
1215
tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1216
}
1217
1218
static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1219
{
1220
TCGv_i32 r_src;
1221
1222
#ifdef TARGET_SPARC64
1223
if (cc)
1224
r_src = cpu_xcc;
1225
else
1226
r_src = cpu_psr;
925
1227
#else
926
{}, {}, {},
1228
r_src = cpu_psr;
927
1229
#endif
1230
switch (cond) {
1231
case 0x0:
1232
gen_op_eval_bn(r_dst);
1233
break;
1234
case 0x1:
1235
gen_op_eval_be(r_dst, r_src);
1236
break;
1237
case 0x2:
1238
gen_op_eval_ble(r_dst, r_src);
1239
break;
1240
case 0x3:
1241
gen_op_eval_bl(r_dst, r_src);
1242
break;
1243
case 0x4:
1244
gen_op_eval_bleu(r_dst, r_src);
1245
break;
1246
case 0x5:
1247
gen_op_eval_bcs(r_dst, r_src);
1248
break;
1249
case 0x6:
1250
gen_op_eval_bneg(r_dst, r_src);
1251
break;
1252
case 0x7:
1253
gen_op_eval_bvs(r_dst, r_src);
1254
break;
1255
case 0x8:
1256
gen_op_eval_ba(r_dst);
1257
break;
1258
case 0x9:
1259
gen_op_eval_bne(r_dst, r_src);
1260
break;
1261
case 0xa:
1262
gen_op_eval_bg(r_dst, r_src);
1263
break;
1264
case 0xb:
1265
gen_op_eval_bge(r_dst, r_src);
1266
break;
1267
case 0xc:
1268
gen_op_eval_bgu(r_dst, r_src);
1269
break;
1270
case 0xd:
1271
gen_op_eval_bcc(r_dst, r_src);
1272
break;
1273
case 0xe:
1274
gen_op_eval_bpos(r_dst, r_src);
1275
break;
1276
case 0xf:
1277
gen_op_eval_bvc(r_dst, r_src);
1278
break;
1279
}
1280
}
1281
1282
static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1283
{
1284
unsigned int offset;
1285
1286
switch (cc) {
1287
default:
1288
case 0x0:
1289
offset = 0;
1290
break;
1291
case 0x1:
1292
offset = 32 - 10;
1293
break;
1294
case 0x2:
1295
offset = 34 - 10;
1296
break;
1297
case 0x3:
1298
offset = 36 - 10;
1299
break;
1300
}
1301
1302
switch (cond) {
1303
case 0x0:
1304
gen_op_eval_bn(r_dst);
1305
break;
1306
case 0x1:
1307
gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1308
break;
1309
case 0x2:
1310
gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1311
break;
1312
case 0x3:
1313
gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1314
break;
1315
case 0x4:
1316
gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1317
break;
1318
case 0x5:
1319
gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1320
break;
1321
case 0x6:
1322
gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1323
break;
1324
case 0x7:
1325
gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1326
break;
1327
case 0x8:
1328
gen_op_eval_ba(r_dst);
1329
break;
1330
case 0x9:
1331
gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1332
break;
1333
case 0xa:
1334
gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1335
break;
1336
case 0xb:
1337
gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1338
break;
1339
case 0xc:
1340
gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1341
break;
1342
case 0xd:
1343
gen_op_eval_fble(r_dst, cpu_fsr, offset);
1344
break;
1345
case 0xe:
1346
gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1347
break;
1348
case 0xf:
1349
gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1350
break;
1351
}
1352
}
1353
1354
#ifdef TARGET_SPARC64
1355
// Inverted logic
1356
static const int gen_tcg_cond_reg[8] = {
1357
-1,
1358
TCG_COND_NE,
1359
TCG_COND_GT,
1360
TCG_COND_GE,
1361
-1,
1362
TCG_COND_EQ,
1363
TCG_COND_LE,
1364
TCG_COND_LT,
928
1365
};
929
1366
930
#ifdef TARGET_SPARC64
931
static void gen_cond_reg(int cond)
1367
static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
932
1368
{
933
switch (cond) {
934
case 0x1:
935
gen_op_eval_brz();
936
break;
937
case 0x2:
938
gen_op_eval_brlez();
939
break;
940
case 0x3:
941
gen_op_eval_brlz();
942
break;
943
case 0x5:
944
gen_op_eval_brnz();
945
break;
946
case 0x6:
947
gen_op_eval_brgz();
948
break;
949
default:
950
case 0x7:
951
gen_op_eval_brgez();
952
break;
953
}
1369
int l1;
1370
1371
l1 = gen_new_label();
1372
tcg_gen_movi_tl(r_dst, 0);
1373
tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], r_src, 0, l1);
1374
tcg_gen_movi_tl(r_dst, 1);
1375
gen_set_label(l1);
954
1376
}
955
1377
#endif
956
1378
957
1379
/* XXX: potentially incorrect if dynamic npc */
958
static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1380
static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1381
TCGv r_cond)
959
1382
{
960
1383
unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
961
1384
target_ulong target = dc->pc + offset;
979
1402
dc->npc = target;
980
1403
}
981
1404
} else {
982
flush_T2(dc);
983
gen_cond[cc][cond]();
1405
flush_cond(dc, r_cond);
1406
gen_cond(r_cond, cc, cond);
984
1407
if (a) {
985
gen_branch_a(dc, target, dc->npc);
1408
gen_branch_a(dc, target, dc->npc, r_cond);
986
1409
dc->is_br = 1;
987
1410
} else {
988
1411
dc->pc = dc->npc;
994
1417
}
995
1418
996
1419
/* XXX: potentially incorrect if dynamic npc */
997
static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1420
static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1421
TCGv r_cond)
998
1422
{
999
1423
unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1000
1424
target_ulong target = dc->pc + offset;
1018
1442
dc->npc = target;
1019
1443
}
1020
1444
} else {
1021
flush_T2(dc);
1022
gen_fcond[cc][cond]();
1445
flush_cond(dc, r_cond);
1446
gen_fcond(r_cond, cc, cond);
1023
1447
if (a) {
1024
gen_branch_a(dc, target, dc->npc);
1448
gen_branch_a(dc, target, dc->npc, r_cond);
1025
1449
dc->is_br = 1;
1026
1450
} else {
1027
1451
dc->pc = dc->npc;
1034
1458
1035
1459
#ifdef TARGET_SPARC64
1036
1460
/* XXX: potentially incorrect if dynamic npc */
1037
static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
1461
static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1462
TCGv r_cond, TCGv r_reg)
1038
1463
{
1039
1464
unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1040
1465
target_ulong target = dc->pc + offset;
1041
1466
1042
flush_T2(dc);
1043
gen_cond_reg(cond);
1467
flush_cond(dc, r_cond);
1468
gen_cond_reg(r_cond, cond, r_reg);
1044
1469
if (a) {
1045
gen_branch_a(dc, target, dc->npc);
1470
gen_branch_a(dc, target, dc->npc, r_cond);
1046
1471
dc->is_br = 1;
1047
1472
} else {
1048
1473
dc->pc = dc->npc;
1052
1477
}
1053
1478
}
1054
1479
1055
static GenOpFunc * const gen_fcmps[4] = {
1056
gen_op_fcmps,
1057
gen_op_fcmps_fcc1,
1058
gen_op_fcmps_fcc2,
1059
gen_op_fcmps_fcc3,
1060
};
1061
1062
static GenOpFunc * const gen_fcmpd[4] = {
1063
gen_op_fcmpd,
1064
gen_op_fcmpd_fcc1,
1065
gen_op_fcmpd_fcc2,
1066
gen_op_fcmpd_fcc3,
1067
};
1068
1069
#if defined(CONFIG_USER_ONLY)
1070
static GenOpFunc * const gen_fcmpq[4] = {
1071
gen_op_fcmpq,
1072
gen_op_fcmpq_fcc1,
1073
gen_op_fcmpq_fcc2,
1074
gen_op_fcmpq_fcc3,
1075
};
1076
#endif
1077
1078
static GenOpFunc * const gen_fcmpes[4] = {
1079
gen_op_fcmpes,
1080
gen_op_fcmpes_fcc1,
1081
gen_op_fcmpes_fcc2,
1082
gen_op_fcmpes_fcc3,
1083
};
1084
1085
static GenOpFunc * const gen_fcmped[4] = {
1086
gen_op_fcmped,
1087
gen_op_fcmped_fcc1,
1088
gen_op_fcmped_fcc2,
1089
gen_op_fcmped_fcc3,
1090
};
1091
1092
#if defined(CONFIG_USER_ONLY)
1093
static GenOpFunc * const gen_fcmpeq[4] = {
1094
gen_op_fcmpeq,
1095
gen_op_fcmpeq_fcc1,
1096
gen_op_fcmpeq_fcc2,
1097
gen_op_fcmpeq_fcc3,
1098
};
1099
#endif
1100
#endif
1101
1102
static int gen_trap_ifnofpu(DisasContext * dc)
1480
static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
1481
{
1482
switch (fccno) {
1483
case 0:
1484
gen_helper_fcmps(r_rs1, r_rs2);
1485
break;
1486
case 1:
1487
gen_helper_fcmps_fcc1(r_rs1, r_rs2);
1488
break;
1489
case 2:
1490
gen_helper_fcmps_fcc2(r_rs1, r_rs2);
1491
break;
1492
case 3:
1493
gen_helper_fcmps_fcc3(r_rs1, r_rs2);
1494
break;
1495
}
1496
}
1497
1498
static inline void gen_op_fcmpd(int fccno)
1499
{
1500
switch (fccno) {
1501
case 0:
1502
gen_helper_fcmpd();
1503
break;
1504
case 1:
1505
gen_helper_fcmpd_fcc1();
1506
break;
1507
case 2:
1508
gen_helper_fcmpd_fcc2();
1509
break;
1510
case 3:
1511
gen_helper_fcmpd_fcc3();
1512
break;
1513
}
1514
}
1515
1516
static inline void gen_op_fcmpq(int fccno)
1517
{
1518
switch (fccno) {
1519
case 0:
1520
gen_helper_fcmpq();
1521
break;
1522
case 1:
1523
gen_helper_fcmpq_fcc1();
1524
break;
1525
case 2:
1526
gen_helper_fcmpq_fcc2();
1527
break;
1528
case 3:
1529
gen_helper_fcmpq_fcc3();
1530
break;
1531
}
1532
}
1533
1534
static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
1535
{
1536
switch (fccno) {
1537
case 0:
1538
gen_helper_fcmpes(r_rs1, r_rs2);
1539
break;
1540
case 1:
1541
gen_helper_fcmpes_fcc1(r_rs1, r_rs2);
1542
break;
1543
case 2:
1544
gen_helper_fcmpes_fcc2(r_rs1, r_rs2);
1545
break;
1546
case 3:
1547
gen_helper_fcmpes_fcc3(r_rs1, r_rs2);
1548
break;
1549
}
1550
}
1551
1552
static inline void gen_op_fcmped(int fccno)
1553
{
1554
switch (fccno) {
1555
case 0:
1556
gen_helper_fcmped();
1557
break;
1558
case 1:
1559
gen_helper_fcmped_fcc1();
1560
break;
1561
case 2:
1562
gen_helper_fcmped_fcc2();
1563
break;
1564
case 3:
1565
gen_helper_fcmped_fcc3();
1566
break;
1567
}
1568
}
1569
1570
static inline void gen_op_fcmpeq(int fccno)
1571
{
1572
switch (fccno) {
1573
case 0:
1574
gen_helper_fcmpeq();
1575
break;
1576
case 1:
1577
gen_helper_fcmpeq_fcc1();
1578
break;
1579
case 2:
1580
gen_helper_fcmpeq_fcc2();
1581
break;
1582
case 3:
1583
gen_helper_fcmpeq_fcc3();
1584
break;
1585
}
1586
}
1587
1588
#else
1589
1590
static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2)
1591
{
1592
gen_helper_fcmps(r_rs1, r_rs2);
1593
}
1594
1595
static inline void gen_op_fcmpd(int fccno)
1596
{
1597
gen_helper_fcmpd();
1598
}
1599
1600
static inline void gen_op_fcmpq(int fccno)
1601
{
1602
gen_helper_fcmpq();
1603
}
1604
1605
static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2)
1606
{
1607
gen_helper_fcmpes(r_rs1, r_rs2);
1608
}
1609
1610
static inline void gen_op_fcmped(int fccno)
1611
{
1612
gen_helper_fcmped();
1613
}
1614
1615
static inline void gen_op_fcmpeq(int fccno)
1616
{
1617
gen_helper_fcmpeq();
1618
}
1619
#endif
1620
1621
static inline void gen_op_fpexception_im(int fsr_flags)
1622
{
1623
TCGv_i32 r_const;
1624
1625
tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK);
1626
tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1627
r_const = tcg_const_i32(TT_FP_EXCP);
1628
gen_helper_raise_exception(r_const);
1629
tcg_temp_free_i32(r_const);
1630
}
1631
1632
static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1103
1633
{
1104
1634
#if !defined(CONFIG_USER_ONLY)
1105
1635
if (!dc->fpu_enabled) {
1106
save_state(dc);
1107
gen_op_exception(TT_NFPU_INSN);
1636
TCGv_i32 r_const;
1637
1638
save_state(dc, r_cond);
1639
r_const = tcg_const_i32(TT_NFPU_INSN);
1640
gen_helper_raise_exception(r_const);
1641
tcg_temp_free_i32(r_const);
1108
1642
dc->is_br = 1;
1109
1643
return 1;
1110
1644
}
1112
1646
return 0;
1113
1647
}
1114
1648
1649
static inline void gen_op_clear_ieee_excp_and_FTT(void)
1650
{
1651
tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK);
1652
}
1653
1654
static inline void gen_clear_float_exceptions(void)
1655
{
1656
gen_helper_clear_float_exceptions();
1657
}
1658
1659
/* asi moves */
1660
#ifdef TARGET_SPARC64
1661
static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr)
1662
{
1663
int asi;
1664
TCGv_i32 r_asi;
1665
1666
if (IS_IMM) {
1667
r_asi = tcg_temp_new_i32();
1668
tcg_gen_mov_i32(r_asi, cpu_asi);
1669
} else {
1670
asi = GET_FIELD(insn, 19, 26);
1671
r_asi = tcg_const_i32(asi);
1672
}
1673
return r_asi;
1674
}
1675
1676
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1677
int sign)
1678
{
1679
TCGv_i32 r_asi, r_size, r_sign;
1680
1681
r_asi = gen_get_asi(insn, addr);
1682
r_size = tcg_const_i32(size);
1683
r_sign = tcg_const_i32(sign);
1684
gen_helper_ld_asi(dst, addr, r_asi, r_size, r_sign);
1685
tcg_temp_free_i32(r_sign);
1686
tcg_temp_free_i32(r_size);
1687
tcg_temp_free_i32(r_asi);
1688
}
1689
1690
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1691
{
1692
TCGv_i32 r_asi, r_size;
1693
1694
r_asi = gen_get_asi(insn, addr);
1695
r_size = tcg_const_i32(size);
1696
gen_helper_st_asi(addr, src, r_asi, r_size);
1697
tcg_temp_free_i32(r_size);
1698
tcg_temp_free_i32(r_asi);
1699
}
1700
1701
static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1702
{
1703
TCGv_i32 r_asi, r_size, r_rd;
1704
1705
r_asi = gen_get_asi(insn, addr);
1706
r_size = tcg_const_i32(size);
1707
r_rd = tcg_const_i32(rd);
1708
gen_helper_ldf_asi(addr, r_asi, r_size, r_rd);
1709
tcg_temp_free_i32(r_rd);
1710
tcg_temp_free_i32(r_size);
1711
tcg_temp_free_i32(r_asi);
1712
}
1713
1714
static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1715
{
1716
TCGv_i32 r_asi, r_size, r_rd;
1717
1718
r_asi = gen_get_asi(insn, addr);
1719
r_size = tcg_const_i32(size);
1720
r_rd = tcg_const_i32(rd);
1721
gen_helper_stf_asi(addr, r_asi, r_size, r_rd);
1722
tcg_temp_free_i32(r_rd);
1723
tcg_temp_free_i32(r_size);
1724
tcg_temp_free_i32(r_asi);
1725
}
1726
1727
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1728
{
1729
TCGv_i32 r_asi, r_size, r_sign;
1730
1731
r_asi = gen_get_asi(insn, addr);
1732
r_size = tcg_const_i32(4);
1733
r_sign = tcg_const_i32(0);
1734
gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
1735
tcg_temp_free_i32(r_sign);
1736
gen_helper_st_asi(addr, dst, r_asi, r_size);
1737
tcg_temp_free_i32(r_size);
1738
tcg_temp_free_i32(r_asi);
1739
tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1740
}
1741
1742
static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1743
{
1744
TCGv_i32 r_asi, r_rd;
1745
1746
r_asi = gen_get_asi(insn, addr);
1747
r_rd = tcg_const_i32(rd);
1748
gen_helper_ldda_asi(addr, r_asi, r_rd);
1749
tcg_temp_free_i32(r_rd);
1750
tcg_temp_free_i32(r_asi);
1751
}
1752
1753
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1754
{
1755
TCGv_i32 r_asi, r_size;
1756
1757
gen_movl_reg_TN(rd + 1, cpu_tmp0);
1758
tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi);
1759
r_asi = gen_get_asi(insn, addr);
1760
r_size = tcg_const_i32(8);
1761
gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size);
1762
tcg_temp_free_i32(r_size);
1763
tcg_temp_free_i32(r_asi);
1764
}
1765
1766
static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1767
int rd)
1768
{
1769
TCGv r_val1;
1770
TCGv_i32 r_asi;
1771
1772
r_val1 = tcg_temp_new();
1773
gen_movl_reg_TN(rd, r_val1);
1774
r_asi = gen_get_asi(insn, addr);
1775
gen_helper_cas_asi(dst, addr, r_val1, val2, r_asi);
1776
tcg_temp_free_i32(r_asi);
1777
tcg_temp_free(r_val1);
1778
}
1779
1780
static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn,
1781
int rd)
1782
{
1783
TCGv_i32 r_asi;
1784
1785
gen_movl_reg_TN(rd, cpu_tmp64);
1786
r_asi = gen_get_asi(insn, addr);
1787
gen_helper_casx_asi(dst, addr, cpu_tmp64, val2, r_asi);
1788
tcg_temp_free_i32(r_asi);
1789
}
1790
1791
#elif !defined(CONFIG_USER_ONLY)
1792
1793
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size,
1794
int sign)
1795
{
1796
TCGv_i32 r_asi, r_size, r_sign;
1797
1798
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1799
r_size = tcg_const_i32(size);
1800
r_sign = tcg_const_i32(sign);
1801
gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
1802
tcg_temp_free(r_sign);
1803
tcg_temp_free(r_size);
1804
tcg_temp_free(r_asi);
1805
tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1806
}
1807
1808
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1809
{
1810
TCGv_i32 r_asi, r_size;
1811
1812
tcg_gen_extu_tl_i64(cpu_tmp64, src);
1813
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1814
r_size = tcg_const_i32(size);
1815
gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size);
1816
tcg_temp_free(r_size);
1817
tcg_temp_free(r_asi);
1818
}
1819
1820
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1821
{
1822
TCGv_i32 r_asi, r_size, r_sign;
1823
TCGv_i64 r_val;
1824
1825
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1826
r_size = tcg_const_i32(4);
1827
r_sign = tcg_const_i32(0);
1828
gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
1829
tcg_temp_free(r_sign);
1830
r_val = tcg_temp_new_i64();
1831
tcg_gen_extu_tl_i64(r_val, dst);
1832
gen_helper_st_asi(addr, r_val, r_asi, r_size);
1833
tcg_temp_free_i64(r_val);
1834
tcg_temp_free(r_size);
1835
tcg_temp_free(r_asi);
1836
tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1837
}
1838
1839
static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd)
1840
{
1841
TCGv_i32 r_asi, r_size, r_sign;
1842
1843
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1844
r_size = tcg_const_i32(8);
1845
r_sign = tcg_const_i32(0);
1846
gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign);
1847
tcg_temp_free(r_sign);
1848
tcg_temp_free(r_size);
1849
tcg_temp_free(r_asi);
1850
tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
1851
gen_movl_TN_reg(rd + 1, cpu_tmp0);
1852
tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1853
tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1854
gen_movl_TN_reg(rd, hi);
1855
}
1856
1857
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1858
{
1859
TCGv_i32 r_asi, r_size;
1860
1861
gen_movl_reg_TN(rd + 1, cpu_tmp0);
1862
tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi);
1863
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1864
r_size = tcg_const_i32(8);
1865
gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size);
1866
tcg_temp_free(r_size);
1867
tcg_temp_free(r_asi);
1868
}
1869
#endif
1870
1871
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1872
static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1873
{
1874
TCGv_i64 r_val;
1875
TCGv_i32 r_asi, r_size;
1876
1877
gen_ld_asi(dst, addr, insn, 1, 0);
1878
1879
r_val = tcg_const_i64(0xffULL);
1880
r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));
1881
r_size = tcg_const_i32(1);
1882
gen_helper_st_asi(addr, r_val, r_asi, r_size);
1883
tcg_temp_free_i32(r_size);
1884
tcg_temp_free_i32(r_asi);
1885
tcg_temp_free_i64(r_val);
1886
}
1887
#endif
1888
1889
static inline TCGv get_src1(unsigned int insn, TCGv def)
1890
{
1891
TCGv r_rs1 = def;
1892
unsigned int rs1;
1893
1894
rs1 = GET_FIELD(insn, 13, 17);
1895
if (rs1 == 0)
1896
r_rs1 = tcg_const_tl(0); // XXX how to free?
1897
else if (rs1 < 8)
1898
r_rs1 = cpu_gregs[rs1];
1899
else
1900
tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1901
return r_rs1;
1902
}
1903
1904
static inline TCGv get_src2(unsigned int insn, TCGv def)
1905
{
1906
TCGv r_rs2 = def;
1907
unsigned int rs2;
1908
1909
if (IS_IMM) { /* immediate */
1910
rs2 = GET_FIELDs(insn, 19, 31);
1911
r_rs2 = tcg_const_tl((int)rs2); // XXX how to free?
1912
} else { /* register */
1913
rs2 = GET_FIELD(insn, 27, 31);
1914
if (rs2 == 0)
1915
r_rs2 = tcg_const_tl(0); // XXX how to free?
1916
else if (rs2 < 8)
1917
r_rs2 = cpu_gregs[rs2];
1918
else
1919
tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
1920
}
1921
return r_rs2;
1922
}
1923
1924
#define CHECK_IU_FEATURE(dc, FEATURE) \
1925
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
1926
goto illegal_insn;
1927
#define CHECK_FPU_FEATURE(dc, FEATURE) \
1928
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
1929
goto nfpu_insn;
1930
1115
1931
/* before an instruction, dc->pc must be static */
1116
1932
static void disas_sparc_insn(DisasContext * dc)
1117
1933
{
1118
1934
unsigned int insn, opc, rs1, rs2, rd;
1119
1935
1936
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
1937
tcg_gen_debug_insn_start(dc->pc);
1120
1938
insn = ldl_code(dc->pc);
1121
1939
opc = GET_FIELD(insn, 0, 1);
1122
1940
1123
1941
rd = GET_FIELD(insn, 2, 6);
1942
1943
cpu_src1 = tcg_temp_new(); // const
1944
cpu_src2 = tcg_temp_new(); // const
1945
1124
1946
switch (opc) {
1125
1947
case 0: /* branches/sethi */
1126
1948
{
1137
1959
target <<= 2;
1138
1960
cc = GET_FIELD_SP(insn, 20, 21);
1139
1961
if (cc == 0)
1140
do_branch(dc, target, insn, 0);
1962
do_branch(dc, target, insn, 0, cpu_cond);
1141
1963
else if (cc == 2)
1142
do_branch(dc, target, insn, 1);
1964
do_branch(dc, target, insn, 1, cpu_cond);
1143
1965
else
1144
1966
goto illegal_insn;
1145
1967
goto jmp_insn;
1150
1972
(GET_FIELD_SP(insn, 20, 21) << 14);
1151
1973
target = sign_extend(target, 16);
1152
1974
target <<= 2;
1153
rs1 = GET_FIELD(insn, 13, 17);
1154
gen_movl_reg_T0(rs1);
1155
do_branch_reg(dc, target, insn);
1975
cpu_src1 = get_src1(insn, cpu_src1);
1976
do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1156
1977
goto jmp_insn;
1157
1978
}
1158
1979
case 0x5: /* V9 FBPcc */
1159
1980
{
1160
1981
int cc = GET_FIELD_SP(insn, 20, 21);
1161
if (gen_trap_ifnofpu(dc))
1982
if (gen_trap_ifnofpu(dc, cpu_cond))
1162
1983
goto jmp_insn;
1163
1984
target = GET_FIELD_SP(insn, 0, 18);
1164
1985
target = sign_extend(target, 19);
1165
1986
target <<= 2;
1166
do_fbranch(dc, target, insn, cc);
1987
do_fbranch(dc, target, insn, cc, cpu_cond);
1167
1988
goto jmp_insn;
1168
1989
}
1169
1990
#else
1177
1998
target = GET_FIELD(insn, 10, 31);
1178
1999
target = sign_extend(target, 22);
1179
2000
target <<= 2;
1180
do_branch(dc, target, insn, 0);
2001
do_branch(dc, target, insn, 0, cpu_cond);
1181
2002
goto jmp_insn;
1182
2003
}
1183
2004
case 0x6: /* FBN+x */
1184
2005
{
1185
if (gen_trap_ifnofpu(dc))
2006
if (gen_trap_ifnofpu(dc, cpu_cond))
1186
2007
goto jmp_insn;
1187
2008
target = GET_FIELD(insn, 10, 31);
1188
2009
target = sign_extend(target, 22);
1189
2010
target <<= 2;
1190
do_fbranch(dc, target, insn, 0);
2011
do_fbranch(dc, target, insn, 0, cpu_cond);
1191
2012
goto jmp_insn;
1192
2013
}
1193
2014
case 0x4: /* SETHI */
1194
#define OPTIM
1195
#if defined(OPTIM)
1196
2015
if (rd) { // nop
1197
#endif
1198
2016
uint32_t value = GET_FIELD(insn, 10, 31);
1199
gen_movl_imm_T0(value << 10);
1200
gen_movl_T0_reg(rd);
1201
#if defined(OPTIM)
2017
TCGv r_const;
2018
2019
r_const = tcg_const_tl(value << 10);
2020
gen_movl_TN_reg(rd, r_const);
2021
tcg_temp_free(r_const);
1202
2022
}
1203
#endif
1204
2023
break;
1205
2024
case 0x0: /* UNIMPL */
1206
2025
default:
1212
2031
case 1:
1213
2032
/*CALL*/ {
1214
2033
target_long target = GET_FIELDs(insn, 2, 31) << 2;
2034
TCGv r_const;
1215
2035
1216
#ifdef TARGET_SPARC64
1217
if (dc->pc == (uint32_t)dc->pc) {
1218
gen_op_movl_T0_im(dc->pc);
1219
} else {
1220
gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
1221
}
1222
#else
1223
gen_op_movl_T0_im(dc->pc);
1224
#endif
1225
gen_movl_T0_reg(15);
2036
r_const = tcg_const_tl(dc->pc);
2037
gen_movl_TN_reg(15, r_const);
2038
tcg_temp_free(r_const);
1226
2039
target += dc->pc;
1227
gen_mov_pc_npc(dc);
2040
gen_mov_pc_npc(dc, cpu_cond);
1228
2041
dc->npc = target;
1229
2042
}
1230
2043
goto jmp_insn;
1234
2047
if (xop == 0x3a) { /* generate trap */
1235
2048
int cond;
1236
2049
1237
rs1 = GET_FIELD(insn, 13, 17);
1238
gen_movl_reg_T0(rs1);
2050
cpu_src1 = get_src1(insn, cpu_src1);
1239
2051
if (IS_IMM) {
1240
2052
rs2 = GET_FIELD(insn, 25, 31);
1241
#if defined(OPTIM)
1242
if (rs2 != 0) {
1243
#endif
1244
gen_movl_simm_T1(rs2);
1245
gen_op_add_T1_T0();
1246
#if defined(OPTIM)
1247
}
1248
#endif
2053
tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
1249
2054
} else {
1250
2055
rs2 = GET_FIELD(insn, 27, 31);
1251
#if defined(OPTIM)
1252
2056
if (rs2 != 0) {
1253
#endif
1254
gen_movl_reg_T1(rs2);
1255
gen_op_add_T1_T0();
1256
#if defined(OPTIM)
1257
}
1258
#endif
2057
gen_movl_reg_TN(rs2, cpu_src2);
2058
tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2059
} else
2060
tcg_gen_mov_tl(cpu_dst, cpu_src1);
1259
2061
}
1260
2062
cond = GET_FIELD(insn, 3, 6);
1261
2063
if (cond == 0x8) {
1262
save_state(dc);
1263
gen_op_trap_T0();
2064
save_state(dc, cpu_cond);
2065
if ((dc->def->features & CPU_FEATURE_HYPV) &&
2066
supervisor(dc))
2067
tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK);
2068
else
2069
tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK);
2070
tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP);
2071
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2072
gen_helper_raise_exception(cpu_tmp32);
1264
2073
} else if (cond != 0) {
2074
TCGv r_cond = tcg_temp_new();
2075
int l1;
1265
2076
#ifdef TARGET_SPARC64
1266
2077
/* V9 icc/xcc */
1267
2078
int cc = GET_FIELD_SP(insn, 11, 12);
1268
flush_T2(dc);
1269
save_state(dc);
2079
2080
save_state(dc, cpu_cond);
1270
2081
if (cc == 0)
1271
gen_cond[0][cond]();
2082
gen_cond(r_cond, 0, cond);
1272
2083
else if (cc == 2)
1273
gen_cond[1][cond]();
2084
gen_cond(r_cond, 1, cond);
1274
2085
else
1275
2086
goto illegal_insn;
1276
2087
#else
1277
flush_T2(dc);
1278
save_state(dc);
1279
gen_cond[0][cond]();
2088
save_state(dc, cpu_cond);
2089
gen_cond(r_cond, 0, cond);
1280
2090
#endif
1281
gen_op_trapcc_T0();
2091
l1 = gen_new_label();
2092
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
2093
2094
if ((dc->def->features & CPU_FEATURE_HYPV) &&
2095
supervisor(dc))
2096
tcg_gen_andi_tl(cpu_dst, cpu_dst, UA2005_HTRAP_MASK);
2097
else
2098
tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK);
2099
tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP);
2100
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2101
gen_helper_raise_exception(cpu_tmp32);
2102
2103
gen_set_label(l1);
2104
tcg_temp_free(r_cond);
1282
2105
}
1283
2106
gen_op_next_insn();
1284
gen_op_movl_T0_0();
1285
gen_op_exit_tb();
2107
tcg_gen_exit_tb(0);
1286
2108
dc->is_br = 1;
1287
2109
goto jmp_insn;
1288
2110
} else if (xop == 0x28) {
1299
2121
SPARCv8 manual, rdy on the
1300
2122
microSPARC II */
1301
2123
#endif
1302
gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
1303
gen_movl_T0_reg(rd);
2124
gen_movl_TN_reg(rd, cpu_y);
1304
2125
break;
1305
2126
#ifdef TARGET_SPARC64
1306
2127
case 0x2: /* V9 rdccr */
1307
gen_op_rdccr();
1308
gen_movl_T0_reg(rd);
2128
gen_helper_rdccr(cpu_dst);
2129
gen_movl_TN_reg(rd, cpu_dst);
1309
2130
break;
1310
2131
case 0x3: /* V9 rdasi */
1311
gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1312
gen_movl_T0_reg(rd);
2132
tcg_gen_ext_i32_tl(cpu_dst, cpu_asi);
2133
gen_movl_TN_reg(rd, cpu_dst);
1313
2134
break;
1314
2135
case 0x4: /* V9 rdtick */
1315
gen_op_rdtick();
1316
gen_movl_T0_reg(rd);
2136
{
2137
TCGv_ptr r_tickptr;
2138
2139
r_tickptr = tcg_temp_new_ptr();
2140
tcg_gen_ld_ptr(r_tickptr, cpu_env,
2141
offsetof(CPUState, tick));
2142
gen_helper_tick_get_count(cpu_dst, r_tickptr);
2143
tcg_temp_free_ptr(r_tickptr);
2144
gen_movl_TN_reg(rd, cpu_dst);
2145
}
1317
2146
break;
1318
2147
case 0x5: /* V9 rdpc */
1319
if (dc->pc == (uint32_t)dc->pc) {
1320
gen_op_movl_T0_im(dc->pc);
1321
} else {
1322
gen_op_movq_T0_im64(dc->pc >> 32, dc->pc);
2148
{
2149
TCGv r_const;
2150
2151
r_const = tcg_const_tl(dc->pc);
2152
gen_movl_TN_reg(rd, r_const);
2153
tcg_temp_free(r_const);
1323
2154
}
1324
gen_movl_T0_reg(rd);
1325
2155
break;
1326
2156
case 0x6: /* V9 rdfprs */
1327
gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1328
gen_movl_T0_reg(rd);
2157
tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs);
2158
gen_movl_TN_reg(rd, cpu_dst);
1329
2159
break;
1330
2160
case 0xf: /* V9 membar */
1331
2161
break; /* no effect */
1332
2162
case 0x13: /* Graphics Status */
1333
if (gen_trap_ifnofpu(dc))
2163
if (gen_trap_ifnofpu(dc, cpu_cond))
1334
2164
goto jmp_insn;
1335
gen_op_movtl_T0_env(offsetof(CPUSPARCState, gsr));
1336
gen_movl_T0_reg(rd);
2165
gen_movl_TN_reg(rd, cpu_gsr);
2166
break;
2167
case 0x16: /* Softint */
2168
tcg_gen_ext_i32_tl(cpu_dst, cpu_softint);
2169
gen_movl_TN_reg(rd, cpu_dst);
1337
2170
break;
1338
2171
case 0x17: /* Tick compare */
1339
gen_op_movtl_T0_env(offsetof(CPUSPARCState, tick_cmpr));
1340
gen_movl_T0_reg(rd);
2172
gen_movl_TN_reg(rd, cpu_tick_cmpr);
1341
2173
break;
1342
2174
case 0x18: /* System tick */
1343
gen_op_rdstick();
1344
gen_movl_T0_reg(rd);
2175
{
2176
TCGv_ptr r_tickptr;
2177
2178
r_tickptr = tcg_temp_new_ptr();
2179
tcg_gen_ld_ptr(r_tickptr, cpu_env,
2180
offsetof(CPUState, stick));
2181
gen_helper_tick_get_count(cpu_dst, r_tickptr);
2182
tcg_temp_free_ptr(r_tickptr);
2183
gen_movl_TN_reg(rd, cpu_dst);
2184
}
1345
2185
break;
1346
2186
case 0x19: /* System tick compare */
1347
gen_op_movtl_T0_env(offsetof(CPUSPARCState, stick_cmpr));
1348
gen_movl_T0_reg(rd);
2187
gen_movl_TN_reg(rd, cpu_stick_cmpr);
1349
2188
break;
1350
2189
case 0x10: /* Performance Control */
1351
2190
case 0x11: /* Performance Instrumentation Counter */
1352
2191
case 0x12: /* Dispatch Control */
1353
2192
case 0x14: /* Softint set, WO */
1354
2193
case 0x15: /* Softint clear, WO */
1355
case 0x16: /* Softint write */
1356
2194
#endif
1357
2195
default:
1358
2196
goto illegal_insn;
1362
2200
#ifndef TARGET_SPARC64
1363
2201
if (!supervisor(dc))
1364
2202
goto priv_insn;
1365
gen_op_rdpsr();
2203
gen_helper_rdpsr(cpu_dst);
1366
2204
#else
2205
CHECK_IU_FEATURE(dc, HYPV);
1367
2206
if (!hypervisor(dc))
1368
2207
goto priv_insn;
1369
2208
rs1 = GET_FIELD(insn, 13, 17);
1375
2214
// gen_op_rdhtstate();
1376
2215
break;
1377
2216
case 3: // hintp
1378
gen_op_movl_T0_env(offsetof(CPUSPARCState, hintp));
2217
tcg_gen_mov_tl(cpu_dst, cpu_hintp);
1379
2218
break;
1380
2219
case 5: // htba
1381
gen_op_movl_T0_env(offsetof(CPUSPARCState, htba));
2220
tcg_gen_mov_tl(cpu_dst, cpu_htba);
1382
2221
break;
1383
2222
case 6: // hver
1384
gen_op_movl_T0_env(offsetof(CPUSPARCState, hver));
2223
tcg_gen_mov_tl(cpu_dst, cpu_hver);
1385
2224
break;
1386
2225
case 31: // hstick_cmpr
1387
gen_op_movl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2226
tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr);
1388
2227
break;
1389
2228
default:
1390
2229
goto illegal_insn;
1391
2230
}
1392
2231
#endif
1393
gen_movl_T0_reg(rd);
2232
gen_movl_TN_reg(rd, cpu_dst);
1394
2233
break;
1395
2234
} else if (xop == 0x2a) { /* rdwim / V9 rdpr */
1396
2235
if (!supervisor(dc))
1399
2238
rs1 = GET_FIELD(insn, 13, 17);
1400
2239
switch (rs1) {
1401
2240
case 0: // tpc
1402
gen_op_rdtpc();
2241
{
2242
TCGv_ptr r_tsptr;
2243
2244
r_tsptr = tcg_temp_new_ptr();
2245
tcg_gen_ld_ptr(r_tsptr, cpu_env,
2246
offsetof(CPUState, tsptr));
2247
tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2248
offsetof(trap_state, tpc));
2249
tcg_temp_free_ptr(r_tsptr);
2250
}
1403
2251
break;
1404
2252
case 1: // tnpc
1405
gen_op_rdtnpc();
2253
{
2254
TCGv_ptr r_tsptr;
2255
2256
r_tsptr = tcg_temp_new_ptr();
2257
tcg_gen_ld_ptr(r_tsptr, cpu_env,
2258
offsetof(CPUState, tsptr));
2259
tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2260
offsetof(trap_state, tnpc));
2261
tcg_temp_free_ptr(r_tsptr);
2262
}
1406
2263
break;
1407
2264
case 2: // tstate
1408
gen_op_rdtstate();
2265
{
2266
TCGv_ptr r_tsptr;
2267
2268
r_tsptr = tcg_temp_new_ptr();
2269
tcg_gen_ld_ptr(r_tsptr, cpu_env,
2270
offsetof(CPUState, tsptr));
2271
tcg_gen_ld_tl(cpu_tmp0, r_tsptr,
2272
offsetof(trap_state, tstate));
2273
tcg_temp_free_ptr(r_tsptr);
2274
}
1409
2275
break;
1410
2276
case 3: // tt
1411
gen_op_rdtt();
2277
{
2278
TCGv_ptr r_tsptr;
2279
2280
r_tsptr = tcg_temp_new_ptr();
2281
tcg_gen_ld_ptr(r_tsptr, cpu_env,
2282
offsetof(CPUState, tsptr));
2283
tcg_gen_ld_i32(cpu_tmp32, r_tsptr,
2284
offsetof(trap_state, tt));
2285
tcg_temp_free_ptr(r_tsptr);
2286
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
2287
}
1412
2288
break;
1413
2289
case 4: // tick
1414
gen_op_rdtick();
2290
{
2291
TCGv_ptr r_tickptr;
2292
2293
r_tickptr = tcg_temp_new_ptr();
2294
tcg_gen_ld_ptr(r_tickptr, cpu_env,
2295
offsetof(CPUState, tick));
2296
gen_helper_tick_get_count(cpu_tmp0, r_tickptr);
2297
gen_movl_TN_reg(rd, cpu_tmp0);
2298
tcg_temp_free_ptr(r_tickptr);
2299
}
1415
2300
break;
1416
2301
case 5: // tba
1417
gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
2302
tcg_gen_mov_tl(cpu_tmp0, cpu_tbr);
1418
2303
break;
1419
2304
case 6: // pstate
1420
gen_op_rdpstate();
2305
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2306
offsetof(CPUSPARCState, pstate));
2307
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
1421
2308
break;
1422
2309
case 7: // tl
1423
gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
2310
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2311
offsetof(CPUSPARCState, tl));
2312
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
1424
2313
break;
1425
2314
case 8: // pil
1426
gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
2315
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2316
offsetof(CPUSPARCState, psrpil));
2317
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
1427
2318
break;
1428
2319
case 9: // cwp
1429
gen_op_rdcwp();
2320
gen_helper_rdcwp(cpu_tmp0);
1430
2321
break;
1431
2322
case 10: // cansave
1432
gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
2323
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2324
offsetof(CPUSPARCState, cansave));
2325
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
1433
2326
break;
1434
2327
case 11: // canrestore
1435
gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
2328
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2329
offsetof(CPUSPARCState, canrestore));
2330
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
1436
2331
break;
1437
2332
case 12: // cleanwin
1438
gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
2333
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2334
offsetof(CPUSPARCState, cleanwin));
2335
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
1439
2336
break;
1440
2337
case 13: // otherwin
1441
gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
2338
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2339
offsetof(CPUSPARCState, otherwin));
2340
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
1442
2341
break;
1443
2342
case 14: // wstate
1444
gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
2343
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2344
offsetof(CPUSPARCState, wstate));
2345
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
1445
2346
break;
1446
2347
case 16: // UA2005 gl
1447
gen_op_movl_T0_env(offsetof(CPUSPARCState, gl));
2348
CHECK_IU_FEATURE(dc, GL);
2349
tcg_gen_ld_i32(cpu_tmp32, cpu_env,
2350
offsetof(CPUSPARCState, gl));
2351
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32);
1448
2352
break;
1449
2353
case 26: // UA2005 strand status
2354
CHECK_IU_FEATURE(dc, HYPV);
1450
2355
if (!hypervisor(dc))
1451
2356
goto priv_insn;
1452
gen_op_movl_T0_env(offsetof(CPUSPARCState, ssr));
2357
tcg_gen_mov_tl(cpu_tmp0, cpu_ssr);
1453
2358
break;
1454
2359
case 31: // ver
1455
gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
2360
tcg_gen_mov_tl(cpu_tmp0, cpu_ver);
1456
2361
break;
1457
2362
case 15: // fq
1458
2363
default:
1459
2364
goto illegal_insn;
1460
2365
}
1461
2366
#else
1462
gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
2367
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim);
1463
2368
#endif
1464
gen_movl_T0_reg(rd);
2369
gen_movl_TN_reg(rd, cpu_tmp0);
1465
2370
break;
1466
2371
} else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1467
2372
#ifdef TARGET_SPARC64
1468
gen_op_flushw();
2373
save_state(dc, cpu_cond);
2374
gen_helper_flushw();
1469
2375
#else
1470
2376
if (!supervisor(dc))
1471
2377
goto priv_insn;
1472
gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1473
gen_movl_T0_reg(rd);
2378
gen_movl_TN_reg(rd, cpu_tbr);
1474
2379
#endif
1475
2380
break;
1476
2381
#endif
1477
2382
} else if (xop == 0x34) { /* FPU Operations */
1478
if (gen_trap_ifnofpu(dc))
2383
if (gen_trap_ifnofpu(dc, cpu_cond))
1479
2384
goto jmp_insn;
1480
2385
gen_op_clear_ieee_excp_and_FTT();
1481
2386
rs1 = GET_FIELD(insn, 13, 17);
1483
2388
xop = GET_FIELD(insn, 18, 26);
1484
2389
switch (xop) {
1485
2390
case 0x1: /* fmovs */
1486
gen_op_load_fpr_FT0(rs2);
1487
gen_op_store_FT0_fpr(rd);
2391
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
1488
2392
break;
1489
2393
case 0x5: /* fnegs */
1490
gen_op_load_fpr_FT1(rs2);
1491
gen_op_fnegs();
1492
gen_op_store_FT0_fpr(rd);
2394
gen_helper_fnegs(cpu_fpr[rd], cpu_fpr[rs2]);
1493
2395
break;
1494
2396
case 0x9: /* fabss */
1495
gen_op_load_fpr_FT1(rs2);
1496
gen_op_fabss();
1497
gen_op_store_FT0_fpr(rd);
2397
gen_helper_fabss(cpu_fpr[rd], cpu_fpr[rs2]);
1498
2398
break;
1499
2399
case 0x29: /* fsqrts */
1500
gen_op_load_fpr_FT1(rs2);
1501
gen_op_fsqrts();
1502
gen_op_store_FT0_fpr(rd);
2400
CHECK_FPU_FEATURE(dc, FSQRT);
2401
gen_clear_float_exceptions();
2402
gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]);
2403
gen_helper_check_ieee_exceptions();
2404
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
1503
2405
break;
1504
2406
case 0x2a: /* fsqrtd */
2407
CHECK_FPU_FEATURE(dc, FSQRT);
1505
2408
gen_op_load_fpr_DT1(DFPREG(rs2));
1506
gen_op_fsqrtd();
2409
gen_clear_float_exceptions();
2410
gen_helper_fsqrtd();
2411
gen_helper_check_ieee_exceptions();
1507
2412
gen_op_store_DT0_fpr(DFPREG(rd));
1508
2413
break;
1509
2414
case 0x2b: /* fsqrtq */
1510
#if defined(CONFIG_USER_ONLY)
2415
CHECK_FPU_FEATURE(dc, FLOAT128);
1511
2416
gen_op_load_fpr_QT1(QFPREG(rs2));
1512
gen_op_fsqrtq();
2417
gen_clear_float_exceptions();
2418
gen_helper_fsqrtq();
2419
gen_helper_check_ieee_exceptions();
1513
2420
gen_op_store_QT0_fpr(QFPREG(rd));
1514
2421
break;
1515
#else
1516
goto nfpu_insn;
1517
#endif
1518
case 0x41:
1519
gen_op_load_fpr_FT0(rs1);
1520
gen_op_load_fpr_FT1(rs2);
1521
gen_op_fadds();
1522
gen_op_store_FT0_fpr(rd);
2422
case 0x41: /* fadds */
2423
gen_clear_float_exceptions();
2424
gen_helper_fadds(cpu_tmp32,
2425
cpu_fpr[rs1], cpu_fpr[rs2]);
2426
gen_helper_check_ieee_exceptions();
2427
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
1523
2428
break;
1524
2429
case 0x42:
1525
2430
gen_op_load_fpr_DT0(DFPREG(rs1));
1526
2431
gen_op_load_fpr_DT1(DFPREG(rs2));
1527
gen_op_faddd();
2432
gen_clear_float_exceptions();
2433
gen_helper_faddd();
2434
gen_helper_check_ieee_exceptions();
1528
2435
gen_op_store_DT0_fpr(DFPREG(rd));
1529
2436
break;
1530
2437
case 0x43: /* faddq */
1531
#if defined(CONFIG_USER_ONLY)
2438
CHECK_FPU_FEATURE(dc, FLOAT128);
1532
2439
gen_op_load_fpr_QT0(QFPREG(rs1));
1533
2440
gen_op_load_fpr_QT1(QFPREG(rs2));
1534
gen_op_faddq();
2441
gen_clear_float_exceptions();
2442
gen_helper_faddq();
2443
gen_helper_check_ieee_exceptions();
1535
2444
gen_op_store_QT0_fpr(QFPREG(rd));
1536
2445
break;
1537
#else
1538
goto nfpu_insn;
1539
#endif
1540
case 0x45:
1541
gen_op_load_fpr_FT0(rs1);
1542
gen_op_load_fpr_FT1(rs2);
1543
gen_op_fsubs();
1544
gen_op_store_FT0_fpr(rd);
2446
case 0x45: /* fsubs */
2447
gen_clear_float_exceptions();
2448
gen_helper_fsubs(cpu_tmp32,
2449
cpu_fpr[rs1], cpu_fpr[rs2]);
2450
gen_helper_check_ieee_exceptions();
2451
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
1545
2452
break;
1546
2453
case 0x46:
1547
2454
gen_op_load_fpr_DT0(DFPREG(rs1));
1548
2455
gen_op_load_fpr_DT1(DFPREG(rs2));
1549
gen_op_fsubd();
2456
gen_clear_float_exceptions();
2457
gen_helper_fsubd();
2458
gen_helper_check_ieee_exceptions();
1550
2459
gen_op_store_DT0_fpr(DFPREG(rd));
1551
2460
break;
1552
2461
case 0x47: /* fsubq */
1553
#if defined(CONFIG_USER_ONLY)
2462
CHECK_FPU_FEATURE(dc, FLOAT128);
1554
2463
gen_op_load_fpr_QT0(QFPREG(rs1));
1555
2464
gen_op_load_fpr_QT1(QFPREG(rs2));
1556
gen_op_fsubq();
2465
gen_clear_float_exceptions();
2466
gen_helper_fsubq();
2467
gen_helper_check_ieee_exceptions();
1557
2468
gen_op_store_QT0_fpr(QFPREG(rd));
1558
2469
break;
1559
#else
1560
goto nfpu_insn;
1561
#endif
1562
case 0x49:
1563
gen_op_load_fpr_FT0(rs1);
1564
gen_op_load_fpr_FT1(rs2);
1565
gen_op_fmuls();
1566
gen_op_store_FT0_fpr(rd);
2470
case 0x49: /* fmuls */
2471
CHECK_FPU_FEATURE(dc, FMUL);
2472
gen_clear_float_exceptions();
2473
gen_helper_fmuls(cpu_tmp32,
2474
cpu_fpr[rs1], cpu_fpr[rs2]);
2475
gen_helper_check_ieee_exceptions();
2476
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
1567
2477
break;
1568
case 0x4a:
2478
case 0x4a: /* fmuld */
2479
CHECK_FPU_FEATURE(dc, FMUL);
1569
2480
gen_op_load_fpr_DT0(DFPREG(rs1));
1570
2481
gen_op_load_fpr_DT1(DFPREG(rs2));
1571
gen_op_fmuld();
2482
gen_clear_float_exceptions();
2483
gen_helper_fmuld();
2484
gen_helper_check_ieee_exceptions();
1572
2485
gen_op_store_DT0_fpr(DFPREG(rd));
1573
2486
break;
1574
2487
case 0x4b: /* fmulq */
1575
#if defined(CONFIG_USER_ONLY)
2488
CHECK_FPU_FEATURE(dc, FLOAT128);
2489
CHECK_FPU_FEATURE(dc, FMUL);
1576
2490
gen_op_load_fpr_QT0(QFPREG(rs1));
1577
2491
gen_op_load_fpr_QT1(QFPREG(rs2));
1578
gen_op_fmulq();
2492
gen_clear_float_exceptions();
2493
gen_helper_fmulq();
2494
gen_helper_check_ieee_exceptions();
1579
2495
gen_op_store_QT0_fpr(QFPREG(rd));
1580
2496
break;
1581
#else
1582
goto nfpu_insn;
1583
#endif
1584
case 0x4d:
1585
gen_op_load_fpr_FT0(rs1);
1586
gen_op_load_fpr_FT1(rs2);
1587
gen_op_fdivs();
1588
gen_op_store_FT0_fpr(rd);
2497
case 0x4d: /* fdivs */
2498
gen_clear_float_exceptions();
2499
gen_helper_fdivs(cpu_tmp32,
2500
cpu_fpr[rs1], cpu_fpr[rs2]);
2501
gen_helper_check_ieee_exceptions();
2502
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
1589
2503
break;
1590
2504
case 0x4e:
1591
2505
gen_op_load_fpr_DT0(DFPREG(rs1));
1592
2506
gen_op_load_fpr_DT1(DFPREG(rs2));
1593
gen_op_fdivd();
2507
gen_clear_float_exceptions();
2508
gen_helper_fdivd();
2509
gen_helper_check_ieee_exceptions();
1594
2510
gen_op_store_DT0_fpr(DFPREG(rd));
1595
2511
break;
1596
2512
case 0x4f: /* fdivq */
1597
#if defined(CONFIG_USER_ONLY)
2513
CHECK_FPU_FEATURE(dc, FLOAT128);
1598
2514
gen_op_load_fpr_QT0(QFPREG(rs1));
1599
2515
gen_op_load_fpr_QT1(QFPREG(rs2));
1600
gen_op_fdivq();
2516
gen_clear_float_exceptions();
2517
gen_helper_fdivq();
2518
gen_helper_check_ieee_exceptions();
1601
2519
gen_op_store_QT0_fpr(QFPREG(rd));
1602
2520
break;
1603
#else
1604
goto nfpu_insn;
1605
#endif
1606
case 0x69:
1607
gen_op_load_fpr_FT0(rs1);
1608
gen_op_load_fpr_FT1(rs2);
1609
gen_op_fsmuld();
2521
case 0x69: /* fsmuld */
2522
CHECK_FPU_FEATURE(dc, FSMULD);
2523
gen_clear_float_exceptions();
2524
gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]);
2525
gen_helper_check_ieee_exceptions();
1610
2526
gen_op_store_DT0_fpr(DFPREG(rd));
1611
2527
break;
1612
2528
case 0x6e: /* fdmulq */
1613
#if defined(CONFIG_USER_ONLY)
2529
CHECK_FPU_FEATURE(dc, FLOAT128);
1614
2530
gen_op_load_fpr_DT0(DFPREG(rs1));
1615
2531
gen_op_load_fpr_DT1(DFPREG(rs2));
1616
gen_op_fdmulq();
2532
gen_clear_float_exceptions();
2533
gen_helper_fdmulq();
2534
gen_helper_check_ieee_exceptions();
1617
2535
gen_op_store_QT0_fpr(QFPREG(rd));
1618
2536
break;
1619
#else
1620
goto nfpu_insn;
1621
#endif
1622
case 0xc4:
1623
gen_op_load_fpr_FT1(rs2);
1624
gen_op_fitos();
1625
gen_op_store_FT0_fpr(rd);
2537
case 0xc4: /* fitos */
2538
gen_clear_float_exceptions();
2539
gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]);
2540
gen_helper_check_ieee_exceptions();
2541
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
1626
2542
break;
1627
case 0xc6:
2543
case 0xc6: /* fdtos */
1628
2544
gen_op_load_fpr_DT1(DFPREG(rs2));
1629
gen_op_fdtos();
1630
gen_op_store_FT0_fpr(rd);
2545
gen_clear_float_exceptions();
2546
gen_helper_fdtos(cpu_tmp32);
2547
gen_helper_check_ieee_exceptions();
2548
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
1631
2549
break;
1632
2550
case 0xc7: /* fqtos */
1633
#if defined(CONFIG_USER_ONLY)
2551
CHECK_FPU_FEATURE(dc, FLOAT128);
1634
2552
gen_op_load_fpr_QT1(QFPREG(rs2));
1635
gen_op_fqtos();
1636
gen_op_store_FT0_fpr(rd);
2553
gen_clear_float_exceptions();
2554
gen_helper_fqtos(cpu_tmp32);
2555
gen_helper_check_ieee_exceptions();
2556
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
1637
2557
break;
1638
#else
1639
goto nfpu_insn;
1640
#endif
1641
case 0xc8:
1642
gen_op_load_fpr_FT1(rs2);
1643
gen_op_fitod();
2558
case 0xc8: /* fitod */
2559
gen_helper_fitod(cpu_fpr[rs2]);
1644
2560
gen_op_store_DT0_fpr(DFPREG(rd));
1645
2561
break;
1646
case 0xc9:
1647
gen_op_load_fpr_FT1(rs2);
1648
gen_op_fstod();
2562
case 0xc9: /* fstod */
2563
gen_helper_fstod(cpu_fpr[rs2]);
1649
2564
gen_op_store_DT0_fpr(DFPREG(rd));
1650
2565
break;
1651
2566
case 0xcb: /* fqtod */
1652
#if defined(CONFIG_USER_ONLY)
2567
CHECK_FPU_FEATURE(dc, FLOAT128);
1653
2568
gen_op_load_fpr_QT1(QFPREG(rs2));
1654
gen_op_fqtod();
2569
gen_clear_float_exceptions();
2570
gen_helper_fqtod();
2571
gen_helper_check_ieee_exceptions();
1655
2572
gen_op_store_DT0_fpr(DFPREG(rd));
1656
2573
break;
1657
#else
1658
goto nfpu_insn;
1659
#endif
1660
2574
case 0xcc: /* fitoq */
1661
#if defined(CONFIG_USER_ONLY)
1662
gen_op_load_fpr_FT1(rs2);
1663
gen_op_fitoq();
2575
CHECK_FPU_FEATURE(dc, FLOAT128);
2576
gen_helper_fitoq(cpu_fpr[rs2]);
1664
2577
gen_op_store_QT0_fpr(QFPREG(rd));
1665
2578
break;
1666
#else
1667
goto nfpu_insn;
1668
#endif
1669
2579
case 0xcd: /* fstoq */
1670
#if defined(CONFIG_USER_ONLY)
1671
gen_op_load_fpr_FT1(rs2);
1672
gen_op_fstoq();
2580
CHECK_FPU_FEATURE(dc, FLOAT128);
2581
gen_helper_fstoq(cpu_fpr[rs2]);
1673
2582
gen_op_store_QT0_fpr(QFPREG(rd));
1674
2583
break;
1675
#else
1676
goto nfpu_insn;
1677
#endif
1678
2584
case 0xce: /* fdtoq */
1679
#if defined(CONFIG_USER_ONLY)
2585
CHECK_FPU_FEATURE(dc, FLOAT128);
1680
2586
gen_op_load_fpr_DT1(DFPREG(rs2));
1681
gen_op_fdtoq();
2587
gen_helper_fdtoq();
1682
2588
gen_op_store_QT0_fpr(QFPREG(rd));
1683
2589
break;
1684
#else
1685
goto nfpu_insn;
1686
#endif
1687
case 0xd1:
1688
gen_op_load_fpr_FT1(rs2);
1689
gen_op_fstoi();
1690
gen_op_store_FT0_fpr(rd);
2590
case 0xd1: /* fstoi */
2591
gen_clear_float_exceptions();
2592
gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]);
2593
gen_helper_check_ieee_exceptions();
2594
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
1691
2595
break;
1692
case 0xd2:
2596
case 0xd2: /* fdtoi */
1693
2597
gen_op_load_fpr_DT1(DFPREG(rs2));
1694
gen_op_fdtoi();
1695
gen_op_store_FT0_fpr(rd);
2598
gen_clear_float_exceptions();
2599
gen_helper_fdtoi(cpu_tmp32);
2600
gen_helper_check_ieee_exceptions();
2601
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
1696
2602
break;
1697
2603
case 0xd3: /* fqtoi */
1698
#if defined(CONFIG_USER_ONLY)
2604
CHECK_FPU_FEATURE(dc, FLOAT128);
1699
2605
gen_op_load_fpr_QT1(QFPREG(rs2));
1700
gen_op_fqtoi();
1701
gen_op_store_FT0_fpr(rd);
2606
gen_clear_float_exceptions();
2607
gen_helper_fqtoi(cpu_tmp32);
2608
gen_helper_check_ieee_exceptions();
2609
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
1702
2610
break;
1703
#else
1704
goto nfpu_insn;
1705
#endif
1706
2611
#ifdef TARGET_SPARC64
1707
2612
case 0x2: /* V9 fmovd */
1708
gen_op_load_fpr_DT0(DFPREG(rs2));
1709
gen_op_store_DT0_fpr(DFPREG(rd));
2613
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)],
2614
cpu_fpr[DFPREG(rs2)]);
2615
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
2616
cpu_fpr[DFPREG(rs2) + 1]);
1710
2617
break;
1711
2618
case 0x3: /* V9 fmovq */
1712
#if defined(CONFIG_USER_ONLY)
1713
gen_op_load_fpr_QT0(QFPREG(rs2));
1714
gen_op_store_QT0_fpr(QFPREG(rd));
2619
CHECK_FPU_FEATURE(dc, FLOAT128);
2620
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)],
2621
cpu_fpr[QFPREG(rs2)]);
2622
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1],
2623
cpu_fpr[QFPREG(rs2) + 1]);
2624
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2],
2625
cpu_fpr[QFPREG(rs2) + 2]);
2626
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3],
2627
cpu_fpr[QFPREG(rs2) + 3]);
1715
2628
break;
1716
#else
1717
goto nfpu_insn;
1718
#endif
1719
2629
case 0x6: /* V9 fnegd */
1720
2630
gen_op_load_fpr_DT1(DFPREG(rs2));
1721
gen_op_fnegd();
2631
gen_helper_fnegd();
1722
2632
gen_op_store_DT0_fpr(DFPREG(rd));
1723
2633
break;
1724
2634
case 0x7: /* V9 fnegq */
1725
#if defined(CONFIG_USER_ONLY)
2635
CHECK_FPU_FEATURE(dc, FLOAT128);
1726
2636
gen_op_load_fpr_QT1(QFPREG(rs2));
1727
gen_op_fnegq();
2637
gen_helper_fnegq();
1728
2638
gen_op_store_QT0_fpr(QFPREG(rd));
1729
2639
break;
1730
#else
1731
goto nfpu_insn;
1732
#endif
1733
2640
case 0xa: /* V9 fabsd */
1734
2641
gen_op_load_fpr_DT1(DFPREG(rs2));
1735
gen_op_fabsd();
2642
gen_helper_fabsd();
1736
2643
gen_op_store_DT0_fpr(DFPREG(rd));
1737
2644
break;
1738
2645
case 0xb: /* V9 fabsq */
1739
#if defined(CONFIG_USER_ONLY)
2646
CHECK_FPU_FEATURE(dc, FLOAT128);
1740
2647
gen_op_load_fpr_QT1(QFPREG(rs2));
1741
gen_op_fabsq();
2648
gen_helper_fabsq();
1742
2649
gen_op_store_QT0_fpr(QFPREG(rd));
1743
2650
break;
1744
#else
1745
goto nfpu_insn;
1746
#endif
1747
2651
case 0x81: /* V9 fstox */
1748
gen_op_load_fpr_FT1(rs2);
1749
gen_op_fstox();
2652
gen_clear_float_exceptions();
2653
gen_helper_fstox(cpu_fpr[rs2]);
2654
gen_helper_check_ieee_exceptions();
1750
2655
gen_op_store_DT0_fpr(DFPREG(rd));
1751
2656
break;
1752
2657
case 0x82: /* V9 fdtox */
1753
2658
gen_op_load_fpr_DT1(DFPREG(rs2));
1754
gen_op_fdtox();
2659
gen_clear_float_exceptions();
2660
gen_helper_fdtox();
2661
gen_helper_check_ieee_exceptions();
1755
2662
gen_op_store_DT0_fpr(DFPREG(rd));
1756
2663
break;
1757
2664
case 0x83: /* V9 fqtox */
1758
#if defined(CONFIG_USER_ONLY)
2665
CHECK_FPU_FEATURE(dc, FLOAT128);
1759
2666
gen_op_load_fpr_QT1(QFPREG(rs2));
1760
gen_op_fqtox();
2667
gen_clear_float_exceptions();
2668
gen_helper_fqtox();
2669
gen_helper_check_ieee_exceptions();
1761
2670
gen_op_store_DT0_fpr(DFPREG(rd));
1762
2671
break;
1763
#else
1764
goto nfpu_insn;
1765
#endif
1766
2672
case 0x84: /* V9 fxtos */
1767
2673
gen_op_load_fpr_DT1(DFPREG(rs2));
1768
gen_op_fxtos();
1769
gen_op_store_FT0_fpr(rd);
2674
gen_clear_float_exceptions();
2675
gen_helper_fxtos(cpu_tmp32);
2676
gen_helper_check_ieee_exceptions();
2677
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
1770
2678
break;
1771
2679
case 0x88: /* V9 fxtod */
1772
2680
gen_op_load_fpr_DT1(DFPREG(rs2));
1773
gen_op_fxtod();
2681
gen_clear_float_exceptions();
2682
gen_helper_fxtod();
2683
gen_helper_check_ieee_exceptions();
1774
2684
gen_op_store_DT0_fpr(DFPREG(rd));
1775
2685
break;
1776
2686
case 0x8c: /* V9 fxtoq */
1777
#if defined(CONFIG_USER_ONLY)
2687
CHECK_FPU_FEATURE(dc, FLOAT128);
1778
2688
gen_op_load_fpr_DT1(DFPREG(rs2));
1779
gen_op_fxtoq();
2689
gen_clear_float_exceptions();
2690
gen_helper_fxtoq();
2691
gen_helper_check_ieee_exceptions();
1780
2692
gen_op_store_QT0_fpr(QFPREG(rd));
1781
2693
break;
1782
#else
1783
goto nfpu_insn;
1784
#endif
1785
2694
#endif
1786
2695
default:
1787
2696
goto illegal_insn;
1790
2699
#ifdef TARGET_SPARC64
1791
2700
int cond;
1792
2701
#endif
1793
if (gen_trap_ifnofpu(dc))
2702
if (gen_trap_ifnofpu(dc, cpu_cond))
1794
2703
goto jmp_insn;
1795
2704
gen_op_clear_ieee_excp_and_FTT();
1796
2705
rs1 = GET_FIELD(insn, 13, 17);
1798
2707
xop = GET_FIELD(insn, 18, 26);
1799
2708
#ifdef TARGET_SPARC64
1800
2709
if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2710
int l1;
2711
2712
l1 = gen_new_label();
1801
2713
cond = GET_FIELD_SP(insn, 14, 17);
1802
gen_op_load_fpr_FT0(rd);
1803
gen_op_load_fpr_FT1(rs2);
1804
rs1 = GET_FIELD(insn, 13, 17);
1805
gen_movl_reg_T0(rs1);
1806
flush_T2(dc);
1807
gen_cond_reg(cond);
1808
gen_op_fmovs_cc();
1809
gen_op_store_FT0_fpr(rd);
2714
cpu_src1 = get_src1(insn, cpu_src1);
2715
tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2716
0, l1);
2717
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
2718
gen_set_label(l1);
1810
2719
break;
1811
2720
} else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2721
int l1;
2722
2723
l1 = gen_new_label();
1812
2724
cond = GET_FIELD_SP(insn, 14, 17);
1813
gen_op_load_fpr_DT0(DFPREG(rd));
1814
gen_op_load_fpr_DT1(DFPREG(rs2));
1815
flush_T2(dc);
1816
rs1 = GET_FIELD(insn, 13, 17);
1817
gen_movl_reg_T0(rs1);
1818
gen_cond_reg(cond);
1819
gen_op_fmovs_cc();
1820
gen_op_store_DT0_fpr(DFPREG(rd));
2725
cpu_src1 = get_src1(insn, cpu_src1);
2726
tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2727
0, l1);
2728
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]);
2729
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], cpu_fpr[DFPREG(rs2) + 1]);
2730
gen_set_label(l1);
1821
2731
break;
1822
2732
} else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1823
#if defined(CONFIG_USER_ONLY)
2733
int l1;
2734
2735
CHECK_FPU_FEATURE(dc, FLOAT128);
2736
l1 = gen_new_label();
1824
2737
cond = GET_FIELD_SP(insn, 14, 17);
1825
gen_op_load_fpr_QT0(QFPREG(rd));
1826
gen_op_load_fpr_QT1(QFPREG(rs2));
1827
flush_T2(dc);
1828
rs1 = GET_FIELD(insn, 13, 17);
1829
gen_movl_reg_T0(rs1);
1830
gen_cond_reg(cond);
1831
gen_op_fmovq_cc();
1832
gen_op_store_QT0_fpr(QFPREG(rd));
2738
cpu_src1 = get_src1(insn, cpu_src1);
2739
tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond], cpu_src1,
2740
0, l1);
2741
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], cpu_fpr[QFPREG(rs2)]);
2742
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], cpu_fpr[QFPREG(rs2) + 1]);
2743
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], cpu_fpr[QFPREG(rs2) + 2]);
2744
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], cpu_fpr[QFPREG(rs2) + 3]);
2745
gen_set_label(l1);
1833
2746
break;
1834
#else
1835
goto nfpu_insn;
1836
#endif
1837
2747
}
1838
2748
#endif
1839
2749
switch (xop) {
1840
2750
#ifdef TARGET_SPARC64
2751
#define FMOVSCC(fcc) \
2752
{ \
2753
TCGv r_cond; \
2754
int l1; \
2755
\
2756
l1 = gen_new_label(); \
2757
r_cond = tcg_temp_new(); \
2758
cond = GET_FIELD_SP(insn, 14, 17); \
2759
gen_fcond(r_cond, fcc, cond); \
2760
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2761
0, l1); \
2762
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \
2763
gen_set_label(l1); \
2764
tcg_temp_free(r_cond); \
2765
}
2766
#define FMOVDCC(fcc) \
2767
{ \
2768
TCGv r_cond; \
2769
int l1; \
2770
\
2771
l1 = gen_new_label(); \
2772
r_cond = tcg_temp_new(); \
2773
cond = GET_FIELD_SP(insn, 14, 17); \
2774
gen_fcond(r_cond, fcc, cond); \
2775
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2776
0, l1); \
2777
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \
2778
cpu_fpr[DFPREG(rs2)]); \
2779
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
2780
cpu_fpr[DFPREG(rs2) + 1]); \
2781
gen_set_label(l1); \
2782
tcg_temp_free(r_cond); \
2783
}
2784
#define FMOVQCC(fcc) \
2785
{ \
2786
TCGv r_cond; \
2787
int l1; \
2788
\
2789
l1 = gen_new_label(); \
2790
r_cond = tcg_temp_new(); \
2791
cond = GET_FIELD_SP(insn, 14, 17); \
2792
gen_fcond(r_cond, fcc, cond); \
2793
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2794
0, l1); \
2795
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \
2796
cpu_fpr[QFPREG(rs2)]); \
2797
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
2798
cpu_fpr[QFPREG(rs2) + 1]); \
2799
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
2800
cpu_fpr[QFPREG(rs2) + 2]); \
2801
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
2802
cpu_fpr[QFPREG(rs2) + 3]); \
2803
gen_set_label(l1); \
2804
tcg_temp_free(r_cond); \
2805
}
1841
2806
case 0x001: /* V9 fmovscc %fcc0 */
1842
cond = GET_FIELD_SP(insn, 14, 17);
1843
gen_op_load_fpr_FT0(rd);
1844
gen_op_load_fpr_FT1(rs2);
1845
flush_T2(dc);
1846
gen_fcond[0][cond]();
1847
gen_op_fmovs_cc();
1848
gen_op_store_FT0_fpr(rd);
2807
FMOVSCC(0);
1849
2808
break;
1850
2809
case 0x002: /* V9 fmovdcc %fcc0 */
1851
cond = GET_FIELD_SP(insn, 14, 17);
1852
gen_op_load_fpr_DT0(DFPREG(rd));
1853
gen_op_load_fpr_DT1(DFPREG(rs2));
1854
flush_T2(dc);
1855
gen_fcond[0][cond]();
1856
gen_op_fmovd_cc();
1857
gen_op_store_DT0_fpr(DFPREG(rd));
2810
FMOVDCC(0);
1858
2811
break;
1859
2812
case 0x003: /* V9 fmovqcc %fcc0 */
1860
#if defined(CONFIG_USER_ONLY)
1861
cond = GET_FIELD_SP(insn, 14, 17);
1862
gen_op_load_fpr_QT0(QFPREG(rd));
1863
gen_op_load_fpr_QT1(QFPREG(rs2));
1864
flush_T2(dc);
1865
gen_fcond[0][cond]();
1866
gen_op_fmovq_cc();
1867
gen_op_store_QT0_fpr(QFPREG(rd));
2813
CHECK_FPU_FEATURE(dc, FLOAT128);
2814
FMOVQCC(0);
1868
2815
break;
1869
#else
1870
goto nfpu_insn;
1871
#endif
1872
2816
case 0x041: /* V9 fmovscc %fcc1 */
1873
cond = GET_FIELD_SP(insn, 14, 17);
1874
gen_op_load_fpr_FT0(rd);
1875
gen_op_load_fpr_FT1(rs2);
1876
flush_T2(dc);
1877
gen_fcond[1][cond]();
1878
gen_op_fmovs_cc();
1879
gen_op_store_FT0_fpr(rd);
2817
FMOVSCC(1);
1880
2818
break;
1881
2819
case 0x042: /* V9 fmovdcc %fcc1 */
1882
cond = GET_FIELD_SP(insn, 14, 17);
1883
gen_op_load_fpr_DT0(DFPREG(rd));
1884
gen_op_load_fpr_DT1(DFPREG(rs2));
1885
flush_T2(dc);
1886
gen_fcond[1][cond]();
1887
gen_op_fmovd_cc();
1888
gen_op_store_DT0_fpr(DFPREG(rd));
2820
FMOVDCC(1);
1889
2821
break;
1890
2822
case 0x043: /* V9 fmovqcc %fcc1 */
1891
#if defined(CONFIG_USER_ONLY)
1892
cond = GET_FIELD_SP(insn, 14, 17);
1893
gen_op_load_fpr_QT0(QFPREG(rd));
1894
gen_op_load_fpr_QT1(QFPREG(rs2));
1895
flush_T2(dc);
1896
gen_fcond[1][cond]();
1897
gen_op_fmovq_cc();
1898
gen_op_store_QT0_fpr(QFPREG(rd));
2823
CHECK_FPU_FEATURE(dc, FLOAT128);
2824
FMOVQCC(1);
1899
2825
break;
1900
#else
1901
goto nfpu_insn;
1902
#endif
1903
2826
case 0x081: /* V9 fmovscc %fcc2 */
1904
cond = GET_FIELD_SP(insn, 14, 17);
1905
gen_op_load_fpr_FT0(rd);
1906
gen_op_load_fpr_FT1(rs2);
1907
flush_T2(dc);
1908
gen_fcond[2][cond]();
1909
gen_op_fmovs_cc();
1910
gen_op_store_FT0_fpr(rd);
2827
FMOVSCC(2);
1911
2828
break;
1912
2829
case 0x082: /* V9 fmovdcc %fcc2 */
1913
cond = GET_FIELD_SP(insn, 14, 17);
1914
gen_op_load_fpr_DT0(DFPREG(rd));
1915
gen_op_load_fpr_DT1(DFPREG(rs2));
1916
flush_T2(dc);
1917
gen_fcond[2][cond]();
1918
gen_op_fmovd_cc();
1919
gen_op_store_DT0_fpr(DFPREG(rd));
2830
FMOVDCC(2);
1920
2831
break;
1921
2832
case 0x083: /* V9 fmovqcc %fcc2 */
1922
#if defined(CONFIG_USER_ONLY)
1923
cond = GET_FIELD_SP(insn, 14, 17);
1924
gen_op_load_fpr_QT0(rd);
1925
gen_op_load_fpr_QT1(rs2);
1926
flush_T2(dc);
1927
gen_fcond[2][cond]();
1928
gen_op_fmovq_cc();
1929
gen_op_store_QT0_fpr(rd);
2833
CHECK_FPU_FEATURE(dc, FLOAT128);
2834
FMOVQCC(2);
1930
2835
break;
1931
#else
1932
goto nfpu_insn;
1933
#endif
1934
2836
case 0x0c1: /* V9 fmovscc %fcc3 */
1935
cond = GET_FIELD_SP(insn, 14, 17);
1936
gen_op_load_fpr_FT0(rd);
1937
gen_op_load_fpr_FT1(rs2);
1938
flush_T2(dc);
1939
gen_fcond[3][cond]();
1940
gen_op_fmovs_cc();
1941
gen_op_store_FT0_fpr(rd);
2837
FMOVSCC(3);
1942
2838
break;
1943
2839
case 0x0c2: /* V9 fmovdcc %fcc3 */
1944
cond = GET_FIELD_SP(insn, 14, 17);
1945
gen_op_load_fpr_DT0(DFPREG(rd));
1946
gen_op_load_fpr_DT1(DFPREG(rs2));
1947
flush_T2(dc);
1948
gen_fcond[3][cond]();
1949
gen_op_fmovd_cc();
1950
gen_op_store_DT0_fpr(DFPREG(rd));
2840
FMOVDCC(3);
1951
2841
break;
1952
2842
case 0x0c3: /* V9 fmovqcc %fcc3 */
1953
#if defined(CONFIG_USER_ONLY)
1954
cond = GET_FIELD_SP(insn, 14, 17);
1955
gen_op_load_fpr_QT0(QFPREG(rd));
1956
gen_op_load_fpr_QT1(QFPREG(rs2));
1957
flush_T2(dc);
1958
gen_fcond[3][cond]();
1959
gen_op_fmovq_cc();
1960
gen_op_store_QT0_fpr(QFPREG(rd));
2843
CHECK_FPU_FEATURE(dc, FLOAT128);
2844
FMOVQCC(3);
1961
2845
break;
1962
#else
1963
goto nfpu_insn;
1964
#endif
2846
#undef FMOVSCC
2847
#undef FMOVDCC
2848
#undef FMOVQCC
2849
#define FMOVCC(size_FDQ, icc) \
2850
{ \
2851
TCGv r_cond; \
2852
int l1; \
2853
\
2854
l1 = gen_new_label(); \
2855
r_cond = tcg_temp_new(); \
2856
cond = GET_FIELD_SP(insn, 14, 17); \
2857
gen_cond(r_cond, icc, cond); \
2858
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2859
0, l1); \
2860
glue(glue(gen_op_load_fpr_, size_FDQ), T0) \
2861
(glue(size_FDQ, FPREG(rs2))); \
2862
glue(glue(gen_op_store_, size_FDQ), T0_fpr) \
2863
(glue(size_FDQ, FPREG(rd))); \
2864
gen_set_label(l1); \
2865
tcg_temp_free(r_cond); \
2866
}
2867
#define FMOVSCC(icc) \
2868
{ \
2869
TCGv r_cond; \
2870
int l1; \
2871
\
2872
l1 = gen_new_label(); \
2873
r_cond = tcg_temp_new(); \
2874
cond = GET_FIELD_SP(insn, 14, 17); \
2875
gen_cond(r_cond, icc, cond); \
2876
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2877
0, l1); \
2878
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); \
2879
gen_set_label(l1); \
2880
tcg_temp_free(r_cond); \
2881
}
2882
#define FMOVDCC(icc) \
2883
{ \
2884
TCGv r_cond; \
2885
int l1; \
2886
\
2887
l1 = gen_new_label(); \
2888
r_cond = tcg_temp_new(); \
2889
cond = GET_FIELD_SP(insn, 14, 17); \
2890
gen_cond(r_cond, icc, cond); \
2891
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2892
0, l1); \
2893
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], \
2894
cpu_fpr[DFPREG(rs2)]); \
2895
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1], \
2896
cpu_fpr[DFPREG(rs2) + 1]); \
2897
gen_set_label(l1); \
2898
tcg_temp_free(r_cond); \
2899
}
2900
#define FMOVQCC(icc) \
2901
{ \
2902
TCGv r_cond; \
2903
int l1; \
2904
\
2905
l1 = gen_new_label(); \
2906
r_cond = tcg_temp_new(); \
2907
cond = GET_FIELD_SP(insn, 14, 17); \
2908
gen_cond(r_cond, icc, cond); \
2909
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \
2910
0, l1); \
2911
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd)], \
2912
cpu_fpr[QFPREG(rs2)]); \
2913
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 1], \
2914
cpu_fpr[QFPREG(rs2) + 1]); \
2915
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 2], \
2916
cpu_fpr[QFPREG(rs2) + 2]); \
2917
tcg_gen_mov_i32(cpu_fpr[QFPREG(rd) + 3], \
2918
cpu_fpr[QFPREG(rs2) + 3]); \
2919
gen_set_label(l1); \
2920
tcg_temp_free(r_cond); \
2921
}
2922
1965
2923
case 0x101: /* V9 fmovscc %icc */
1966
cond = GET_FIELD_SP(insn, 14, 17);
1967
gen_op_load_fpr_FT0(rd);
1968
gen_op_load_fpr_FT1(rs2);
1969
flush_T2(dc);
1970
gen_cond[0][cond]();
1971
gen_op_fmovs_cc();
1972
gen_op_store_FT0_fpr(rd);
2924
FMOVSCC(0);
1973
2925
break;
1974
2926
case 0x102: /* V9 fmovdcc %icc */
1975
cond = GET_FIELD_SP(insn, 14, 17);
1976
gen_op_load_fpr_DT0(DFPREG(rd));
1977
gen_op_load_fpr_DT1(DFPREG(rs2));
1978
flush_T2(dc);
1979
gen_cond[0][cond]();
1980
gen_op_fmovd_cc();
1981
gen_op_store_DT0_fpr(DFPREG(rd));
1982
break;
2927
FMOVDCC(0);
1983
2928
case 0x103: /* V9 fmovqcc %icc */
1984
#if defined(CONFIG_USER_ONLY)
1985
cond = GET_FIELD_SP(insn, 14, 17);
1986
gen_op_load_fpr_QT0(rd);
1987
gen_op_load_fpr_QT1(rs2);
1988
flush_T2(dc);
1989
gen_cond[0][cond]();
1990
gen_op_fmovq_cc();
1991
gen_op_store_QT0_fpr(rd);
2929
CHECK_FPU_FEATURE(dc, FLOAT128);
2930
FMOVQCC(0);
1992
2931
break;
1993
#else
1994
goto nfpu_insn;
1995
#endif
1996
2932
case 0x181: /* V9 fmovscc %xcc */
1997
cond = GET_FIELD_SP(insn, 14, 17);
1998
gen_op_load_fpr_FT0(rd);
1999
gen_op_load_fpr_FT1(rs2);
2000
flush_T2(dc);
2001
gen_cond[1][cond]();
2002
gen_op_fmovs_cc();
2003
gen_op_store_FT0_fpr(rd);
2933
FMOVSCC(1);
2004
2934
break;
2005
2935
case 0x182: /* V9 fmovdcc %xcc */
2006
cond = GET_FIELD_SP(insn, 14, 17);
2007
gen_op_load_fpr_DT0(DFPREG(rd));
2008
gen_op_load_fpr_DT1(DFPREG(rs2));
2009
flush_T2(dc);
2010
gen_cond[1][cond]();
2011
gen_op_fmovd_cc();
2012
gen_op_store_DT0_fpr(DFPREG(rd));
2936
FMOVDCC(1);
2013
2937
break;
2014
2938
case 0x183: /* V9 fmovqcc %xcc */
2015
#if defined(CONFIG_USER_ONLY)
2016
cond = GET_FIELD_SP(insn, 14, 17);
2017
gen_op_load_fpr_QT0(rd);
2018
gen_op_load_fpr_QT1(rs2);
2019
flush_T2(dc);
2020
gen_cond[1][cond]();
2021
gen_op_fmovq_cc();
2022
gen_op_store_QT0_fpr(rd);
2939
CHECK_FPU_FEATURE(dc, FLOAT128);
2940
FMOVQCC(1);
2023
2941
break;
2024
#else
2025
goto nfpu_insn;
2026
#endif
2942
#undef FMOVSCC
2943
#undef FMOVDCC
2944
#undef FMOVQCC
2027
2945
#endif
2028
2946
case 0x51: /* fcmps, V9 %fcc */
2029
gen_op_load_fpr_FT0(rs1);
2030
gen_op_load_fpr_FT1(rs2);
2031
#ifdef TARGET_SPARC64
2032
gen_fcmps[rd & 3]();
2033
#else
2034
gen_op_fcmps();
2035
#endif
2947
gen_op_fcmps(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
2036
2948
break;
2037
2949
case 0x52: /* fcmpd, V9 %fcc */
2038
2950
gen_op_load_fpr_DT0(DFPREG(rs1));
2039
2951
gen_op_load_fpr_DT1(DFPREG(rs2));
2040
#ifdef TARGET_SPARC64
2041
gen_fcmpd[rd & 3]();
2042
#else
2043
gen_op_fcmpd();
2044
#endif
2952
gen_op_fcmpd(rd & 3);
2045
2953
break;
2046
2954
case 0x53: /* fcmpq, V9 %fcc */
2047
#if defined(CONFIG_USER_ONLY)
2955
CHECK_FPU_FEATURE(dc, FLOAT128);
2048
2956
gen_op_load_fpr_QT0(QFPREG(rs1));
2049
2957
gen_op_load_fpr_QT1(QFPREG(rs2));
2050
#ifdef TARGET_SPARC64
2051
gen_fcmpq[rd & 3]();
2052
#else
2053
gen_op_fcmpq();
2054
#endif
2958
gen_op_fcmpq(rd & 3);
2055
2959
break;
2056
#else /* !defined(CONFIG_USER_ONLY) */
2057
goto nfpu_insn;
2058
#endif
2059
2960
case 0x55: /* fcmpes, V9 %fcc */
2060
gen_op_load_fpr_FT0(rs1);
2061
gen_op_load_fpr_FT1(rs2);
2062
#ifdef TARGET_SPARC64
2063
gen_fcmpes[rd & 3]();
2064
#else
2065
gen_op_fcmpes();
2066
#endif
2961
gen_op_fcmpes(rd & 3, cpu_fpr[rs1], cpu_fpr[rs2]);
2067
2962
break;
2068
2963
case 0x56: /* fcmped, V9 %fcc */
2069
2964
gen_op_load_fpr_DT0(DFPREG(rs1));
2070
2965
gen_op_load_fpr_DT1(DFPREG(rs2));
2071
#ifdef TARGET_SPARC64
2072
gen_fcmped[rd & 3]();
2073
#else
2074
gen_op_fcmped();
2075
#endif
2966
gen_op_fcmped(rd & 3);
2076
2967
break;
2077
2968
case 0x57: /* fcmpeq, V9 %fcc */
2078
#if defined(CONFIG_USER_ONLY)
2969
CHECK_FPU_FEATURE(dc, FLOAT128);
2079
2970
gen_op_load_fpr_QT0(QFPREG(rs1));
2080
2971
gen_op_load_fpr_QT1(QFPREG(rs2));
2081
#ifdef TARGET_SPARC64
2082
gen_fcmpeq[rd & 3]();
2083
#else
2084
gen_op_fcmpeq();
2085
#endif
2972
gen_op_fcmpeq(rd & 3);
2086
2973
break;
2087
#else/* !defined(CONFIG_USER_ONLY) */
2088
goto nfpu_insn;
2089
#endif
2090
2974
default:
2091
2975
goto illegal_insn;
2092
2976
}
2093
#if defined(OPTIM)
2094
2977
} else if (xop == 0x2) {
2095
2978
// clr/mov shortcut
2096
2979
2097
2980
rs1 = GET_FIELD(insn, 13, 17);
2098
2981
if (rs1 == 0) {
2099
// or %g0, x, y -> mov T1, x; mov y, T1
2982
// or %g0, x, y -> mov T0, x; mov y, T0
2100
2983
if (IS_IMM) { /* immediate */
2984
TCGv r_const;
2985
2101
2986
rs2 = GET_FIELDs(insn, 19, 31);
2102
gen_movl_simm_T1(rs2);
2987
r_const = tcg_const_tl((int)rs2);
2988
gen_movl_TN_reg(rd, r_const);
2989
tcg_temp_free(r_const);
2103
2990
} else { /* register */
2104
2991
rs2 = GET_FIELD(insn, 27, 31);
2105
gen_movl_reg_T1(rs2);
2992
gen_movl_reg_TN(rs2, cpu_dst);
2993
gen_movl_TN_reg(rd, cpu_dst);
2106
2994
}
2107
gen_movl_T1_reg(rd);
2108
2995
} else {
2109
gen_movl_reg_T0(rs1);
2996
cpu_src1 = get_src1(insn, cpu_src1);
2110
2997
if (IS_IMM) { /* immediate */
2111
// or x, #0, y -> mov T1, x; mov y, T1
2112
2998
rs2 = GET_FIELDs(insn, 19, 31);
2113
if (rs2 != 0) {
2114
gen_movl_simm_T1(rs2);
2115
gen_op_or_T1_T0();
2116
}
2999
tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
3000
gen_movl_TN_reg(rd, cpu_dst);
2117
3001
} else { /* register */
2118
3002
// or x, %g0, y -> mov T1, x; mov y, T1
2119
3003
rs2 = GET_FIELD(insn, 27, 31);
2120
3004
if (rs2 != 0) {
2121
gen_movl_reg_T1(rs2);
2122
gen_op_or_T1_T0();
2123
}
3005
gen_movl_reg_TN(rs2, cpu_src2);
3006
tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
3007
gen_movl_TN_reg(rd, cpu_dst);
3008
} else
3009
gen_movl_TN_reg(rd, cpu_src1);
2124
3010
}
2125
gen_movl_T0_reg(rd);
2126
3011
}
2127
#endif
2128
3012
#ifdef TARGET_SPARC64
2129
3013
} else if (xop == 0x25) { /* sll, V9 sllx */
2130
rs1 = GET_FIELD(insn, 13, 17);
2131
gen_movl_reg_T0(rs1);
3014
cpu_src1 = get_src1(insn, cpu_src1);
2132
3015
if (IS_IMM) { /* immediate */
2133
3016
rs2 = GET_FIELDs(insn, 20, 31);
2134
gen_movl_simm_T1(rs2);
3017
if (insn & (1 << 12)) {
3018
tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
3019
} else {
3020
tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x1f);
3021
}
2135
3022
} else { /* register */
2136
3023
rs2 = GET_FIELD(insn, 27, 31);
2137
gen_movl_reg_T1(rs2);
3024
gen_movl_reg_TN(rs2, cpu_src2);
3025
if (insn & (1 << 12)) {
3026
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3027
} else {
3028
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3029
}
3030
tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2138
3031
}
2139
if (insn & (1 << 12))
2140
gen_op_sllx();
2141
else
2142
gen_op_sll();
2143
gen_movl_T0_reg(rd);
3032
gen_movl_TN_reg(rd, cpu_dst);
2144
3033
} else if (xop == 0x26) { /* srl, V9 srlx */
2145
rs1 = GET_FIELD(insn, 13, 17);
2146
gen_movl_reg_T0(rs1);
3034
cpu_src1 = get_src1(insn, cpu_src1);
2147
3035
if (IS_IMM) { /* immediate */
2148
3036
rs2 = GET_FIELDs(insn, 20, 31);
2149
gen_movl_simm_T1(rs2);
3037
if (insn & (1 << 12)) {
3038
tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
3039
} else {
3040
tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3041
tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
3042
}
2150
3043
} else { /* register */
2151
3044
rs2 = GET_FIELD(insn, 27, 31);
2152
gen_movl_reg_T1(rs2);
3045
gen_movl_reg_TN(rs2, cpu_src2);
3046
if (insn & (1 << 12)) {
3047
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3048
tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
3049
} else {
3050
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3051
tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3052
tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
3053
}
2153
3054
}
2154
if (insn & (1 << 12))
2155
gen_op_srlx();
2156
else
2157
gen_op_srl();
2158
gen_movl_T0_reg(rd);
3055
gen_movl_TN_reg(rd, cpu_dst);
2159
3056
} else if (xop == 0x27) { /* sra, V9 srax */
2160
rs1 = GET_FIELD(insn, 13, 17);
2161
gen_movl_reg_T0(rs1);
3057
cpu_src1 = get_src1(insn, cpu_src1);
2162
3058
if (IS_IMM) { /* immediate */
2163
3059
rs2 = GET_FIELDs(insn, 20, 31);
2164
gen_movl_simm_T1(rs2);
3060
if (insn & (1 << 12)) {
3061
tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
3062
} else {
3063
tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3064
tcg_gen_ext32s_i64(cpu_dst, cpu_dst);
3065
tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
3066
}
2165
3067
} else { /* register */
2166
3068
rs2 = GET_FIELD(insn, 27, 31);
2167
gen_movl_reg_T1(rs2);
3069
gen_movl_reg_TN(rs2, cpu_src2);
3070
if (insn & (1 << 12)) {
3071
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
3072
tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
3073
} else {
3074
tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
3075
tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
3076
tcg_gen_ext32s_i64(cpu_dst, cpu_dst);
3077
tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
3078
}
2168
3079
}
2169
if (insn & (1 << 12))
2170
gen_op_srax();
2171
else
2172
gen_op_sra();
2173
gen_movl_T0_reg(rd);
3080
gen_movl_TN_reg(rd, cpu_dst);
2174
3081
#endif
2175
3082
} else if (xop < 0x36) {
2176
rs1 = GET_FIELD(insn, 13, 17);
2177
gen_movl_reg_T0(rs1);
2178
if (IS_IMM) { /* immediate */
2179
rs2 = GET_FIELDs(insn, 19, 31);
2180
gen_movl_simm_T1(rs2);
2181
} else { /* register */
2182
rs2 = GET_FIELD(insn, 27, 31);
2183
gen_movl_reg_T1(rs2);
2184
}
3083
cpu_src1 = get_src1(insn, cpu_src1);
3084
cpu_src2 = get_src2(insn, cpu_src2);
2185
3085
if (xop < 0x20) {
2186
3086
switch (xop & ~0x10) {
2187
3087
case 0x0:
2188
3088
if (xop & 0x10)
2189
gen_op_add_T1_T0_cc();
3089
gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2190
3090
else
2191
gen_op_add_T1_T0();
3091
tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2192
3092
break;
2193
3093
case 0x1:
2194
gen_op_and_T1_T0();
3094
tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2195
3095
if (xop & 0x10)
2196
gen_op_logic_T0_cc();
3096
gen_op_logic_cc(cpu_dst);
2197
3097
break;
2198
3098
case 0x2:
2199
gen_op_or_T1_T0();
3099
tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2200
3100
if (xop & 0x10)
2201
gen_op_logic_T0_cc();
3101
gen_op_logic_cc(cpu_dst);
2202
3102
break;
2203
3103
case 0x3:
2204
gen_op_xor_T1_T0();
3104
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
2205
3105
if (xop & 0x10)
2206
gen_op_logic_T0_cc();
3106
gen_op_logic_cc(cpu_dst);
2207
3107
break;
2208
3108
case 0x4:
2209
3109
if (xop & 0x10)
2210
gen_op_sub_T1_T0_cc();
3110
gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
2211
3111
else
2212
gen_op_sub_T1_T0();
3112
tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
2213
3113
break;
2214
3114
case 0x5:
2215
gen_op_andn_T1_T0();
3115
tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2);
2216
3116
if (xop & 0x10)
2217
gen_op_logic_T0_cc();
3117
gen_op_logic_cc(cpu_dst);
2218
3118
break;
2219
3119
case 0x6:
2220
gen_op_orn_T1_T0();
3120
tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2);
2221
3121
if (xop & 0x10)
2222
gen_op_logic_T0_cc();
3122
gen_op_logic_cc(cpu_dst);
2223
3123
break;
2224
3124
case 0x7:
2225
gen_op_xnor_T1_T0();
3125
tcg_gen_not_tl(cpu_tmp0, cpu_src2);
3126
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
2226
3127
if (xop & 0x10)
2227
gen_op_logic_T0_cc();
3128
gen_op_logic_cc(cpu_dst);
2228
3129
break;
2229
3130
case 0x8:
2230
3131
if (xop & 0x10)
2231
gen_op_addx_T1_T0_cc();
2232
else
2233
gen_op_addx_T1_T0();
3132
gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3133
else {
3134
gen_mov_reg_C(cpu_tmp0, cpu_psr);
3135
tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3136
tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3137
}
2234
3138
break;
2235
3139
#ifdef TARGET_SPARC64
2236
3140
case 0x9: /* V9 mulx */
2237
gen_op_mulx_T1_T0();
3141
tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
2238
3142
break;
2239
3143
#endif
2240
3144
case 0xa:
2241
gen_op_umul_T1_T0();
3145
CHECK_IU_FEATURE(dc, MUL);
3146
gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
2242
3147
if (xop & 0x10)
2243
gen_op_logic_T0_cc();
3148
gen_op_logic_cc(cpu_dst);
2244
3149
break;
2245
3150
case 0xb:
2246
gen_op_smul_T1_T0();
3151
CHECK_IU_FEATURE(dc, MUL);
3152
gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
2247
3153
if (xop & 0x10)
2248
gen_op_logic_T0_cc();
3154
gen_op_logic_cc(cpu_dst);
2249
3155
break;
2250
3156
case 0xc:
2251
3157
if (xop & 0x10)
2252
gen_op_subx_T1_T0_cc();
2253
else
2254
gen_op_subx_T1_T0();
3158
gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3159
else {
3160
gen_mov_reg_C(cpu_tmp0, cpu_psr);
3161
tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3162
tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3163
}
2255
3164
break;
2256
3165
#ifdef TARGET_SPARC64
2257
3166
case 0xd: /* V9 udivx */
2258
gen_op_udivx_T1_T0();
3167
tcg_gen_mov_tl(cpu_cc_src, cpu_src1);
3168
tcg_gen_mov_tl(cpu_cc_src2, cpu_src2);
3169
gen_trap_ifdivzero_tl(cpu_cc_src2);
3170
tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
2259
3171
break;
2260
3172
#endif
2261
3173
case 0xe:
2262
gen_op_udiv_T1_T0();
3174
CHECK_IU_FEATURE(dc, DIV);
3175
gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2);
2263
3176
if (xop & 0x10)
2264
gen_op_div_cc();
3177
gen_op_div_cc(cpu_dst);
2265
3178
break;
2266
3179
case 0xf:
2267
gen_op_sdiv_T1_T0();
3180
CHECK_IU_FEATURE(dc, DIV);
3181
gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2);
2268
3182
if (xop & 0x10)
2269
gen_op_div_cc();
3183
gen_op_div_cc(cpu_dst);
2270
3184
break;
2271
3185
default:
2272
3186
goto illegal_insn;
2273
3187
}
2274
gen_movl_T0_reg(rd);
3188
gen_movl_TN_reg(rd, cpu_dst);
2275
3189
} else {
2276
3190
switch (xop) {
2277
3191
case 0x20: /* taddcc */
2278
gen_op_tadd_T1_T0_cc();
2279
gen_movl_T0_reg(rd);
3192
gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3193
gen_movl_TN_reg(rd, cpu_dst);
2280
3194
break;
2281
3195
case 0x21: /* tsubcc */
2282
gen_op_tsub_T1_T0_cc();
2283
gen_movl_T0_reg(rd);
3196
gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3197
gen_movl_TN_reg(rd, cpu_dst);
2284
3198
break;
2285
3199
case 0x22: /* taddcctv */
2286
save_state(dc);
2287
gen_op_tadd_T1_T0_ccTV();
2288
gen_movl_T0_reg(rd);
3200
save_state(dc, cpu_cond);
3201
gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3202
gen_movl_TN_reg(rd, cpu_dst);
2289
3203
break;
2290
3204
case 0x23: /* tsubcctv */
2291
save_state(dc);
2292
gen_op_tsub_T1_T0_ccTV();
2293
gen_movl_T0_reg(rd);
3205
save_state(dc, cpu_cond);
3206
gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3207
gen_movl_TN_reg(rd, cpu_dst);
2294
3208
break;
2295
3209
case 0x24: /* mulscc */
2296
gen_op_mulscc_T1_T0();
2297
gen_movl_T0_reg(rd);
3210
gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3211
gen_movl_TN_reg(rd, cpu_dst);
2298
3212
break;
2299
3213
#ifndef TARGET_SPARC64
2300
3214
case 0x25: /* sll */
2301
gen_op_sll();
2302
gen_movl_T0_reg(rd);
3215
if (IS_IMM) { /* immediate */
3216
rs2 = GET_FIELDs(insn, 20, 31);
3217
tcg_gen_shli_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3218
} else { /* register */
3219
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3220
tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3221
}
3222
gen_movl_TN_reg(rd, cpu_dst);
2303
3223
break;
2304
3224
case 0x26: /* srl */
2305
gen_op_srl();
2306
gen_movl_T0_reg(rd);
3225
if (IS_IMM) { /* immediate */
3226
rs2 = GET_FIELDs(insn, 20, 31);
3227
tcg_gen_shri_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3228
} else { /* register */
3229
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3230
tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3231
}
3232
gen_movl_TN_reg(rd, cpu_dst);
2307
3233
break;
2308
3234
case 0x27: /* sra */
2309
gen_op_sra();
2310
gen_movl_T0_reg(rd);
3235
if (IS_IMM) { /* immediate */
3236
rs2 = GET_FIELDs(insn, 20, 31);
3237
tcg_gen_sari_tl(cpu_dst, cpu_src1, rs2 & 0x1f);
3238
} else { /* register */
3239
tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3240
tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3241
}
3242
gen_movl_TN_reg(rd, cpu_dst);
2311
3243
break;
2312
3244
#endif
2313
3245
case 0x30:
2314
3246
{
2315
3247
switch(rd) {
2316
3248
case 0: /* wry */
2317
gen_op_xor_T1_T0();
2318
gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
3249
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
3250
tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
2319
3251
break;
2320
3252
#ifndef TARGET_SPARC64
2321
3253
case 0x01 ... 0x0f: /* undefined in the
2329
3261
break;
2330
3262
#else
2331
3263
case 0x2: /* V9 wrccr */
2332
gen_op_xor_T1_T0();
2333
gen_op_wrccr();
3264
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3265
gen_helper_wrccr(cpu_dst);
2334
3266
break;
2335
3267
case 0x3: /* V9 wrasi */
2336
gen_op_xor_T1_T0();
2337
gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
3268
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3269
tcg_gen_trunc_tl_i32(cpu_asi, cpu_dst);
2338
3270
break;
2339
3271
case 0x6: /* V9 wrfprs */
2340
gen_op_xor_T1_T0();
2341
gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
2342
save_state(dc);
3272
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3273
tcg_gen_trunc_tl_i32(cpu_fprs, cpu_dst);
3274
save_state(dc, cpu_cond);
2343
3275
gen_op_next_insn();
2344
gen_op_movl_T0_0();
2345
gen_op_exit_tb();
3276
tcg_gen_exit_tb(0);
2346
3277
dc->is_br = 1;
2347
3278
break;
2348
3279
case 0xf: /* V9 sir, nop if user */
2349
3280
#if !defined(CONFIG_USER_ONLY)
2350
3281
if (supervisor(dc))
2351
gen_op_sir();
3282
; // XXX
2352
3283
#endif
2353
3284
break;
2354
3285
case 0x13: /* Graphics Status */
2355
if (gen_trap_ifnofpu(dc))
3286
if (gen_trap_ifnofpu(dc, cpu_cond))
2356
3287
goto jmp_insn;
2357
gen_op_xor_T1_T0();
2358
gen_op_movtl_env_T0(offsetof(CPUSPARCState, gsr));
3288
tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
3289
break;
3290
case 0x14: /* Softint set */
3291
if (!supervisor(dc))
3292
goto illegal_insn;
3293
tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
3294
gen_helper_set_softint(cpu_tmp64);
3295
break;
3296
case 0x15: /* Softint clear */
3297
if (!supervisor(dc))
3298
goto illegal_insn;
3299
tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
3300
gen_helper_clear_softint(cpu_tmp64);
3301
break;
3302
case 0x16: /* Softint write */
3303
if (!supervisor(dc))
3304
goto illegal_insn;
3305
tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
3306
gen_helper_write_softint(cpu_tmp64);
2359
3307
break;
2360
3308
case 0x17: /* Tick compare */
2361
3309
#if !defined(CONFIG_USER_ONLY)
2362
3310
if (!supervisor(dc))
2363
3311
goto illegal_insn;
2364
3312
#endif
2365
gen_op_xor_T1_T0();
2366
gen_op_movtl_env_T0(offsetof(CPUSPARCState, tick_cmpr));
2367
gen_op_wrtick_cmpr();
3313
{
3314
TCGv_ptr r_tickptr;
3315
3316
tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1,
3317
cpu_src2);
3318
r_tickptr = tcg_temp_new_ptr();
3319
tcg_gen_ld_ptr(r_tickptr, cpu_env,
3320
offsetof(CPUState, tick));
3321
gen_helper_tick_set_limit(r_tickptr,
3322
cpu_tick_cmpr);
3323
tcg_temp_free_ptr(r_tickptr);
3324
}
2368
3325
break;
2369
3326
case 0x18: /* System tick */
2370
3327
#if !defined(CONFIG_USER_ONLY)
2371
3328
if (!supervisor(dc))
2372
3329
goto illegal_insn;
2373
3330
#endif
2374
gen_op_xor_T1_T0();
2375
gen_op_wrstick();
3331
{
3332
TCGv_ptr r_tickptr;
3333
3334
tcg_gen_xor_tl(cpu_dst, cpu_src1,
3335
cpu_src2);
3336
r_tickptr = tcg_temp_new_ptr();
3337
tcg_gen_ld_ptr(r_tickptr, cpu_env,
3338
offsetof(CPUState, stick));
3339
gen_helper_tick_set_count(r_tickptr,
3340
cpu_dst);
3341
tcg_temp_free_ptr(r_tickptr);
3342
}
2376
3343
break;
2377
3344
case 0x19: /* System tick compare */
2378
3345
#if !defined(CONFIG_USER_ONLY)
2379
3346
if (!supervisor(dc))
2380
3347
goto illegal_insn;
2381
3348
#endif
2382
gen_op_xor_T1_T0();
2383
gen_op_movtl_env_T0(offsetof(CPUSPARCState, stick_cmpr));
2384
gen_op_wrstick_cmpr();
3349
{
3350
TCGv_ptr r_tickptr;
3351
3352
tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1,
3353
cpu_src2);
3354
r_tickptr = tcg_temp_new_ptr();
3355
tcg_gen_ld_ptr(r_tickptr, cpu_env,
3356
offsetof(CPUState, stick));
3357
gen_helper_tick_set_limit(r_tickptr,
3358
cpu_stick_cmpr);
3359
tcg_temp_free_ptr(r_tickptr);
3360
}
2385
3361
break;
2386
3362
2387
3363
case 0x10: /* Performance Control */
2388
case 0x11: /* Performance Instrumentation Counter */
3364
case 0x11: /* Performance Instrumentation
3365
Counter */
2389
3366
case 0x12: /* Dispatch Control */
2390
case 0x14: /* Softint set */
2391
case 0x15: /* Softint clear */
2392
case 0x16: /* Softint write */
2393
3367
#endif
2394
3368
default:
2395
3369
goto illegal_insn;
2404
3378
#ifdef TARGET_SPARC64
2405
3379
switch (rd) {
2406
3380
case 0:
2407
gen_op_saved();
3381
gen_helper_saved();
2408
3382
break;
2409
3383
case 1:
2410
gen_op_restored();
3384
gen_helper_restored();
2411
3385
break;
2412
3386
case 2: /* UA2005 allclean */
2413
3387
case 3: /* UA2005 otherw */
2418
3392
goto illegal_insn;
2419
3393
}
2420
3394
#else
2421
gen_op_xor_T1_T0();
2422
gen_op_wrpsr();
2423
save_state(dc);
3395
tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3396
gen_helper_wrpsr(cpu_dst);
3397
save_state(dc, cpu_cond);
2424
3398
gen_op_next_insn();
2425
gen_op_movl_T0_0();
2426
gen_op_exit_tb();
3399
tcg_gen_exit_tb(0);
2427
3400
dc->is_br = 1;
2428
3401
#endif
2429
3402
}
2432
3405
{
2433
3406
if (!supervisor(dc))
2434
3407
goto priv_insn;
2435
gen_op_xor_T1_T0();
3408
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
2436
3409
#ifdef TARGET_SPARC64
2437
3410
switch (rd) {
2438
3411
case 0: // tpc
2439
gen_op_wrtpc();
3412
{
3413
TCGv_ptr r_tsptr;
3414
3415
r_tsptr = tcg_temp_new_ptr();
3416
tcg_gen_ld_ptr(r_tsptr, cpu_env,
3417
offsetof(CPUState, tsptr));
3418
tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3419
offsetof(trap_state, tpc));
3420
tcg_temp_free_ptr(r_tsptr);
3421
}
2440
3422
break;
2441
3423
case 1: // tnpc
2442
gen_op_wrtnpc();
3424
{
3425
TCGv_ptr r_tsptr;
3426
3427
r_tsptr = tcg_temp_new_ptr();
3428
tcg_gen_ld_ptr(r_tsptr, cpu_env,
3429
offsetof(CPUState, tsptr));
3430
tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3431
offsetof(trap_state, tnpc));
3432
tcg_temp_free_ptr(r_tsptr);
3433
}
2443
3434
break;
2444
3435
case 2: // tstate
2445
gen_op_wrtstate();
3436
{
3437
TCGv_ptr r_tsptr;
3438
3439
r_tsptr = tcg_temp_new_ptr();
3440
tcg_gen_ld_ptr(r_tsptr, cpu_env,
3441
offsetof(CPUState, tsptr));
3442
tcg_gen_st_tl(cpu_tmp0, r_tsptr,
3443
offsetof(trap_state,
3444
tstate));
3445
tcg_temp_free_ptr(r_tsptr);
3446
}
2446
3447
break;
2447
3448
case 3: // tt
2448
gen_op_wrtt();
3449
{
3450
TCGv_ptr r_tsptr;
3451
3452
r_tsptr = tcg_temp_new_ptr();
3453
tcg_gen_ld_ptr(r_tsptr, cpu_env,
3454
offsetof(CPUState, tsptr));
3455
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3456
tcg_gen_st_i32(cpu_tmp32, r_tsptr,
3457
offsetof(trap_state, tt));
3458
tcg_temp_free_ptr(r_tsptr);
3459
}
2449
3460
break;
2450
3461
case 4: // tick
2451
gen_op_wrtick();
3462
{
3463
TCGv_ptr r_tickptr;
3464
3465
r_tickptr = tcg_temp_new_ptr();
3466
tcg_gen_ld_ptr(r_tickptr, cpu_env,
3467
offsetof(CPUState, tick));
3468
gen_helper_tick_set_count(r_tickptr,
3469
cpu_tmp0);
3470
tcg_temp_free_ptr(r_tickptr);
3471
}
2452
3472
break;
2453
3473
case 5: // tba
2454
gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3474
tcg_gen_mov_tl(cpu_tbr, cpu_tmp0);
2455
3475
break;
2456
3476
case 6: // pstate
2457
gen_op_wrpstate();
2458
save_state(dc);
3477
save_state(dc, cpu_cond);
3478
gen_helper_wrpstate(cpu_tmp0);
2459
3479
gen_op_next_insn();
2460
gen_op_movl_T0_0();
2461
gen_op_exit_tb();
3480
tcg_gen_exit_tb(0);
2462
3481
dc->is_br = 1;
2463
3482
break;
2464
3483
case 7: // tl
2465
gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
3484
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3485
tcg_gen_st_i32(cpu_tmp32, cpu_env,
3486
offsetof(CPUSPARCState, tl));
2466
3487
break;
2467
3488
case 8: // pil
2468
gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
3489
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3490
tcg_gen_st_i32(cpu_tmp32, cpu_env,
3491
offsetof(CPUSPARCState,
3492
psrpil));
2469
3493
break;
2470
3494
case 9: // cwp
2471
gen_op_wrcwp();
3495
gen_helper_wrcwp(cpu_tmp0);
2472
3496
break;
2473
3497
case 10: // cansave
2474
gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
3498
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3499
tcg_gen_st_i32(cpu_tmp32, cpu_env,
3500
offsetof(CPUSPARCState,
3501
cansave));
2475
3502
break;
2476
3503
case 11: // canrestore
2477
gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
3504
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3505
tcg_gen_st_i32(cpu_tmp32, cpu_env,
3506
offsetof(CPUSPARCState,
3507
canrestore));
2478
3508
break;
2479
3509
case 12: // cleanwin
2480
gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
3510
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3511
tcg_gen_st_i32(cpu_tmp32, cpu_env,
3512
offsetof(CPUSPARCState,
3513
cleanwin));
2481
3514
break;
2482
3515
case 13: // otherwin
2483
gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
3516
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3517
tcg_gen_st_i32(cpu_tmp32, cpu_env,
3518
offsetof(CPUSPARCState,
3519
otherwin));
2484
3520
break;
2485
3521
case 14: // wstate
2486
gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
3522
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3523
tcg_gen_st_i32(cpu_tmp32, cpu_env,
3524
offsetof(CPUSPARCState,
3525
wstate));
2487
3526
break;
2488
3527
case 16: // UA2005 gl
2489
gen_op_movl_env_T0(offsetof(CPUSPARCState, gl));
3528
CHECK_IU_FEATURE(dc, GL);
3529
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3530
tcg_gen_st_i32(cpu_tmp32, cpu_env,
3531
offsetof(CPUSPARCState, gl));
2490
3532
break;
2491
3533
case 26: // UA2005 strand status
3534
CHECK_IU_FEATURE(dc, HYPV);
2492
3535
if (!hypervisor(dc))
2493
3536
goto priv_insn;
2494
gen_op_movl_env_T0(offsetof(CPUSPARCState, ssr));
3537
tcg_gen_mov_tl(cpu_ssr, cpu_tmp0);
2495
3538
break;
2496
3539
default:
2497
3540
goto illegal_insn;
2498
3541
}
2499
3542
#else
2500
gen_op_wrwim();
3543
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
3544
if (dc->def->nwindows != 32)
3545
tcg_gen_andi_tl(cpu_tmp32, cpu_tmp32,
3546
(1 << dc->def->nwindows) - 1);
3547
tcg_gen_mov_i32(cpu_wim, cpu_tmp32);
2501
3548
#endif
2502
3549
}
2503
3550
break;
2506
3553
#ifndef TARGET_SPARC64
2507
3554
if (!supervisor(dc))
2508
3555
goto priv_insn;
2509
gen_op_xor_T1_T0();
2510
gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
3556
tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2);
2511
3557
#else
3558
CHECK_IU_FEATURE(dc, HYPV);
2512
3559
if (!hypervisor(dc))
2513
3560
goto priv_insn;
2514
gen_op_xor_T1_T0();
3561
tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
2515
3562
switch (rd) {
2516
3563
case 0: // hpstate
2517
3564
// XXX gen_op_wrhpstate();
2518
save_state(dc);
3565
save_state(dc, cpu_cond);
2519
3566
gen_op_next_insn();
2520
gen_op_movl_T0_0();
2521
gen_op_exit_tb();
3567
tcg_gen_exit_tb(0);
2522
3568
dc->is_br = 1;
2523
3569
break;
2524
3570
case 1: // htstate
2525
3571
// XXX gen_op_wrhtstate();
2526
3572
break;
2527
3573
case 3: // hintp
2528
gen_op_movl_env_T0(offsetof(CPUSPARCState, hintp));
3574
tcg_gen_mov_tl(cpu_hintp, cpu_tmp0);
2529
3575
break;
2530
3576
case 5: // htba
2531
gen_op_movl_env_T0(offsetof(CPUSPARCState, htba));
3577
tcg_gen_mov_tl(cpu_htba, cpu_tmp0);
2532
3578
break;
2533
3579
case 31: // hstick_cmpr
2534
gen_op_movtl_env_T0(offsetof(CPUSPARCState, hstick_cmpr));
2535
gen_op_wrhstick_cmpr();
3580
{
3581
TCGv_ptr r_tickptr;
3582
3583
tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0);
3584
r_tickptr = tcg_temp_new_ptr();
3585
tcg_gen_ld_ptr(r_tickptr, cpu_env,
3586
offsetof(CPUState, hstick));
3587
gen_helper_tick_set_limit(r_tickptr,
3588
cpu_hstick_cmpr);
3589
tcg_temp_free_ptr(r_tickptr);
3590
}
2536
3591
break;
2537
3592
case 6: // hver readonly
2538
3593
default:
2547
3602
{
2548
3603
int cc = GET_FIELD_SP(insn, 11, 12);
2549
3604
int cond = GET_FIELD_SP(insn, 14, 17);
2550
if (IS_IMM) { /* immediate */
2551
rs2 = GET_FIELD_SPs(insn, 0, 10);
2552
gen_movl_simm_T1(rs2);
2553
}
2554
else {
2555
rs2 = GET_FIELD_SP(insn, 0, 4);
2556
gen_movl_reg_T1(rs2);
2557
}
2558
gen_movl_reg_T0(rd);
2559
flush_T2(dc);
3605
TCGv r_cond;
3606
int l1;
3607
3608
r_cond = tcg_temp_new();
2560
3609
if (insn & (1 << 18)) {
2561
3610
if (cc == 0)
2562
gen_cond[0][cond]();
3611
gen_cond(r_cond, 0, cond);
2563
3612
else if (cc == 2)
2564
gen_cond[1][cond]();
3613
gen_cond(r_cond, 1, cond);
2565
3614
else
2566
3615
goto illegal_insn;
2567
3616
} else {
2568
gen_fcond[cc][cond]();
2569
}
2570
gen_op_mov_cc();
2571
gen_movl_T0_reg(rd);
3617
gen_fcond(r_cond, cc, cond);
3618
}
3619
3620
l1 = gen_new_label();
3621
3622
tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);
3623
if (IS_IMM) { /* immediate */
3624
TCGv r_const;
3625
3626
rs2 = GET_FIELD_SPs(insn, 0, 10);
3627
r_const = tcg_const_tl((int)rs2);
3628
gen_movl_TN_reg(rd, r_const);
3629
tcg_temp_free(r_const);
3630
} else {
3631
rs2 = GET_FIELD_SP(insn, 0, 4);
3632
gen_movl_reg_TN(rs2, cpu_tmp0);
3633
gen_movl_TN_reg(rd, cpu_tmp0);
3634
}
3635
gen_set_label(l1);
3636
tcg_temp_free(r_cond);
2572
3637
break;
2573
3638
}
2574
3639
case 0x2d: /* V9 sdivx */
2575
gen_op_sdivx_T1_T0();
2576
gen_movl_T0_reg(rd);
3640
gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3641
gen_movl_TN_reg(rd, cpu_dst);
2577
3642
break;
2578
3643
case 0x2e: /* V9 popc */
2579
3644
{
2580
if (IS_IMM) { /* immediate */
2581
rs2 = GET_FIELD_SPs(insn, 0, 12);
2582
gen_movl_simm_T1(rs2);
2583
// XXX optimize: popc(constant)
2584
}
2585
else {
2586
rs2 = GET_FIELD_SP(insn, 0, 4);
2587
gen_movl_reg_T1(rs2);
2588
}
2589
gen_op_popc();
2590
gen_movl_T0_reg(rd);
3645
cpu_src2 = get_src2(insn, cpu_src2);
3646
gen_helper_popc(cpu_dst, cpu_src2);
3647
gen_movl_TN_reg(rd, cpu_dst);
2591
3648
}
2592
3649
case 0x2f: /* V9 movr */
2593
3650
{
2594
3651
int cond = GET_FIELD_SP(insn, 10, 12);
2595
rs1 = GET_FIELD(insn, 13, 17);
2596
flush_T2(dc);
2597
gen_movl_reg_T0(rs1);
2598
gen_cond_reg(cond);
3652
int l1;
3653
3654
cpu_src1 = get_src1(insn, cpu_src1);
3655
3656
l1 = gen_new_label();
3657
3658
tcg_gen_brcondi_tl(gen_tcg_cond_reg[cond],
3659
cpu_src1, 0, l1);
2599
3660
if (IS_IMM) { /* immediate */
3661
TCGv r_const;
3662
2600
3663
rs2 = GET_FIELD_SPs(insn, 0, 9);
2601
gen_movl_simm_T1(rs2);
2602
}
2603
else {
3664
r_const = tcg_const_tl((int)rs2);
3665
gen_movl_TN_reg(rd, r_const);
3666
tcg_temp_free(r_const);
3667
} else {
2604
3668
rs2 = GET_FIELD_SP(insn, 0, 4);
2605
gen_movl_reg_T1(rs2);
3669
gen_movl_reg_TN(rs2, cpu_tmp0);
3670
gen_movl_TN_reg(rd, cpu_tmp0);
2606
3671
}
2607
gen_movl_reg_T0(rd);
2608
gen_op_mov_cc();
2609
gen_movl_T0_reg(rd);
3672
gen_set_label(l1);
2610
3673
break;
2611
3674
}
2612
3675
#endif
2619
3682
int opf = GET_FIELD_SP(insn, 5, 13);
2620
3683
rs1 = GET_FIELD(insn, 13, 17);
2621
3684
rs2 = GET_FIELD(insn, 27, 31);
2622
if (gen_trap_ifnofpu(dc))
3685
if (gen_trap_ifnofpu(dc, cpu_cond))
2623
3686
goto jmp_insn;
2624
3687
2625
3688
switch (opf) {
2638
3701
// XXX
2639
3702
goto illegal_insn;
2640
3703
case 0x010: /* VIS I array8 */
2641
gen_movl_reg_T0(rs1);
2642
gen_movl_reg_T1(rs2);
2643
gen_op_array8();
2644
gen_movl_T0_reg(rd);
3704
CHECK_FPU_FEATURE(dc, VIS1);
3705
cpu_src1 = get_src1(insn, cpu_src1);
3706
gen_movl_reg_TN(rs2, cpu_src2);
3707
gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
3708
gen_movl_TN_reg(rd, cpu_dst);
2645
3709
break;
2646
3710
case 0x012: /* VIS I array16 */
2647
gen_movl_reg_T0(rs1);
2648
gen_movl_reg_T1(rs2);
2649
gen_op_array16();
2650
gen_movl_T0_reg(rd);
3711
CHECK_FPU_FEATURE(dc, VIS1);
3712
cpu_src1 = get_src1(insn, cpu_src1);
3713
gen_movl_reg_TN(rs2, cpu_src2);
3714
gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
3715
tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3716
gen_movl_TN_reg(rd, cpu_dst);
2651
3717
break;
2652
3718
case 0x014: /* VIS I array32 */
2653
gen_movl_reg_T0(rs1);
2654
gen_movl_reg_T1(rs2);
2655
gen_op_array32();
2656
gen_movl_T0_reg(rd);
3719
CHECK_FPU_FEATURE(dc, VIS1);
3720
cpu_src1 = get_src1(insn, cpu_src1);
3721
gen_movl_reg_TN(rs2, cpu_src2);
3722
gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
3723
tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3724
gen_movl_TN_reg(rd, cpu_dst);
2657
3725
break;
2658
3726
case 0x018: /* VIS I alignaddr */
2659
gen_movl_reg_T0(rs1);
2660
gen_movl_reg_T1(rs2);
2661
gen_op_alignaddr();
2662
gen_movl_T0_reg(rd);
3727
CHECK_FPU_FEATURE(dc, VIS1);
3728
cpu_src1 = get_src1(insn, cpu_src1);
3729
gen_movl_reg_TN(rs2, cpu_src2);
3730
gen_helper_alignaddr(cpu_dst, cpu_src1, cpu_src2);
3731
gen_movl_TN_reg(rd, cpu_dst);
2663
3732
break;
2664
3733
case 0x019: /* VIS II bmask */
2665
3734
case 0x01a: /* VIS I alignaddrl */
2666
3735
// XXX
2667
3736
goto illegal_insn;
2668
3737
case 0x020: /* VIS I fcmple16 */
3738
CHECK_FPU_FEATURE(dc, VIS1);
2669
3739
gen_op_load_fpr_DT0(DFPREG(rs1));
2670
3740
gen_op_load_fpr_DT1(DFPREG(rs2));
2671
gen_op_fcmple16();
3741
gen_helper_fcmple16();
2672
3742
gen_op_store_DT0_fpr(DFPREG(rd));
2673
3743
break;
2674
3744
case 0x022: /* VIS I fcmpne16 */
3745
CHECK_FPU_FEATURE(dc, VIS1);
2675
3746
gen_op_load_fpr_DT0(DFPREG(rs1));
2676
3747
gen_op_load_fpr_DT1(DFPREG(rs2));
2677
gen_op_fcmpne16();
3748
gen_helper_fcmpne16();
2678
3749
gen_op_store_DT0_fpr(DFPREG(rd));
2679
3750
break;
2680
3751
case 0x024: /* VIS I fcmple32 */
3752
CHECK_FPU_FEATURE(dc, VIS1);
2681
3753
gen_op_load_fpr_DT0(DFPREG(rs1));
2682
3754
gen_op_load_fpr_DT1(DFPREG(rs2));
2683
gen_op_fcmple32();
3755
gen_helper_fcmple32();
2684
3756
gen_op_store_DT0_fpr(DFPREG(rd));
2685
3757
break;
2686
3758
case 0x026: /* VIS I fcmpne32 */
3759
CHECK_FPU_FEATURE(dc, VIS1);
2687
3760
gen_op_load_fpr_DT0(DFPREG(rs1));
2688
3761
gen_op_load_fpr_DT1(DFPREG(rs2));
2689
gen_op_fcmpne32();
3762
gen_helper_fcmpne32();
2690
3763
gen_op_store_DT0_fpr(DFPREG(rd));
2691
3764
break;
2692
3765
case 0x028: /* VIS I fcmpgt16 */
3766
CHECK_FPU_FEATURE(dc, VIS1);
2693
3767
gen_op_load_fpr_DT0(DFPREG(rs1));
2694
3768
gen_op_load_fpr_DT1(DFPREG(rs2));
2695
gen_op_fcmpgt16();
3769
gen_helper_fcmpgt16();
2696
3770
gen_op_store_DT0_fpr(DFPREG(rd));
2697
3771
break;
2698
3772
case 0x02a: /* VIS I fcmpeq16 */
3773
CHECK_FPU_FEATURE(dc, VIS1);
2699
3774
gen_op_load_fpr_DT0(DFPREG(rs1));
2700
3775
gen_op_load_fpr_DT1(DFPREG(rs2));
2701
gen_op_fcmpeq16();
3776
gen_helper_fcmpeq16();
2702
3777
gen_op_store_DT0_fpr(DFPREG(rd));
2703
3778
break;
2704
3779
case 0x02c: /* VIS I fcmpgt32 */
3780
CHECK_FPU_FEATURE(dc, VIS1);
2705
3781
gen_op_load_fpr_DT0(DFPREG(rs1));
2706
3782
gen_op_load_fpr_DT1(DFPREG(rs2));
2707
gen_op_fcmpgt32();
3783
gen_helper_fcmpgt32();
2708
3784
gen_op_store_DT0_fpr(DFPREG(rd));
2709
3785
break;
2710
3786
case 0x02e: /* VIS I fcmpeq32 */
3787
CHECK_FPU_FEATURE(dc, VIS1);
2711
3788
gen_op_load_fpr_DT0(DFPREG(rs1));
2712
3789
gen_op_load_fpr_DT1(DFPREG(rs2));
2713
gen_op_fcmpeq32();
3790
gen_helper_fcmpeq32();
2714
3791
gen_op_store_DT0_fpr(DFPREG(rd));
2715
3792
break;
2716
3793
case 0x031: /* VIS I fmul8x16 */
3794
CHECK_FPU_FEATURE(dc, VIS1);
2717
3795
gen_op_load_fpr_DT0(DFPREG(rs1));
2718
3796
gen_op_load_fpr_DT1(DFPREG(rs2));
2719
gen_op_fmul8x16();
3797
gen_helper_fmul8x16();
2720
3798
gen_op_store_DT0_fpr(DFPREG(rd));
2721
3799
break;
2722
3800
case 0x033: /* VIS I fmul8x16au */
3801
CHECK_FPU_FEATURE(dc, VIS1);
2723
3802
gen_op_load_fpr_DT0(DFPREG(rs1));
2724
3803
gen_op_load_fpr_DT1(DFPREG(rs2));
2725
gen_op_fmul8x16au();
3804
gen_helper_fmul8x16au();
2726
3805
gen_op_store_DT0_fpr(DFPREG(rd));
2727
3806
break;
2728
3807
case 0x035: /* VIS I fmul8x16al */
3808
CHECK_FPU_FEATURE(dc, VIS1);
2729
3809
gen_op_load_fpr_DT0(DFPREG(rs1));
2730
3810
gen_op_load_fpr_DT1(DFPREG(rs2));
2731
gen_op_fmul8x16al();
3811
gen_helper_fmul8x16al();
2732
3812
gen_op_store_DT0_fpr(DFPREG(rd));
2733
3813
break;
2734
3814
case 0x036: /* VIS I fmul8sux16 */
3815
CHECK_FPU_FEATURE(dc, VIS1);
2735
3816
gen_op_load_fpr_DT0(DFPREG(rs1));
2736
3817
gen_op_load_fpr_DT1(DFPREG(rs2));
2737
gen_op_fmul8sux16();
3818
gen_helper_fmul8sux16();
2738
3819
gen_op_store_DT0_fpr(DFPREG(rd));
2739
3820
break;
2740
3821
case 0x037: /* VIS I fmul8ulx16 */
3822
CHECK_FPU_FEATURE(dc, VIS1);
2741
3823
gen_op_load_fpr_DT0(DFPREG(rs1));
2742
3824
gen_op_load_fpr_DT1(DFPREG(rs2));
2743
gen_op_fmul8ulx16();
3825
gen_helper_fmul8ulx16();
2744
3826
gen_op_store_DT0_fpr(DFPREG(rd));
2745
3827
break;
2746
3828
case 0x038: /* VIS I fmuld8sux16 */
3829
CHECK_FPU_FEATURE(dc, VIS1);
2747
3830
gen_op_load_fpr_DT0(DFPREG(rs1));
2748
3831
gen_op_load_fpr_DT1(DFPREG(rs2));
2749
gen_op_fmuld8sux16();
3832
gen_helper_fmuld8sux16();
2750
3833
gen_op_store_DT0_fpr(DFPREG(rd));
2751
3834
break;
2752
3835
case 0x039: /* VIS I fmuld8ulx16 */
3836
CHECK_FPU_FEATURE(dc, VIS1);
2753
3837
gen_op_load_fpr_DT0(DFPREG(rs1));
2754
3838
gen_op_load_fpr_DT1(DFPREG(rs2));
2755
gen_op_fmuld8ulx16();
3839
gen_helper_fmuld8ulx16();
2756
3840
gen_op_store_DT0_fpr(DFPREG(rd));
2757
3841
break;
2758
3842
case 0x03a: /* VIS I fpack32 */
2762
3846
// XXX
2763
3847
goto illegal_insn;
2764
3848
case 0x048: /* VIS I faligndata */
3849
CHECK_FPU_FEATURE(dc, VIS1);
2765
3850
gen_op_load_fpr_DT0(DFPREG(rs1));
2766
3851
gen_op_load_fpr_DT1(DFPREG(rs2));
2767
gen_op_faligndata();
3852
gen_helper_faligndata();
2768
3853
gen_op_store_DT0_fpr(DFPREG(rd));
2769
3854
break;
2770
3855
case 0x04b: /* VIS I fpmerge */
3856
CHECK_FPU_FEATURE(dc, VIS1);
2771
3857
gen_op_load_fpr_DT0(DFPREG(rs1));
2772
3858
gen_op_load_fpr_DT1(DFPREG(rs2));
2773
gen_op_fpmerge();
3859
gen_helper_fpmerge();
2774
3860
gen_op_store_DT0_fpr(DFPREG(rd));
2775
3861
break;
2776
3862
case 0x04c: /* VIS II bshuffle */
2777
3863
// XXX
2778
3864
goto illegal_insn;
2779
3865
case 0x04d: /* VIS I fexpand */
3866
CHECK_FPU_FEATURE(dc, VIS1);
2780
3867
gen_op_load_fpr_DT0(DFPREG(rs1));
2781
3868
gen_op_load_fpr_DT1(DFPREG(rs2));
2782
gen_op_fexpand();
3869
gen_helper_fexpand();
2783
3870
gen_op_store_DT0_fpr(DFPREG(rd));
2784
3871
break;
2785
3872
case 0x050: /* VIS I fpadd16 */
3873
CHECK_FPU_FEATURE(dc, VIS1);
2786
3874
gen_op_load_fpr_DT0(DFPREG(rs1));
2787
3875
gen_op_load_fpr_DT1(DFPREG(rs2));
2788
gen_op_fpadd16();
3876
gen_helper_fpadd16();
2789
3877
gen_op_store_DT0_fpr(DFPREG(rd));
2790
3878
break;
2791
3879
case 0x051: /* VIS I fpadd16s */
2792
gen_op_load_fpr_FT0(rs1);
2793
gen_op_load_fpr_FT1(rs2);
2794
gen_op_fpadd16s();
2795
gen_op_store_FT0_fpr(rd);
3880
CHECK_FPU_FEATURE(dc, VIS1);
3881
gen_helper_fpadd16s(cpu_fpr[rd],
3882
cpu_fpr[rs1], cpu_fpr[rs2]);
2796
3883
break;
2797
3884
case 0x052: /* VIS I fpadd32 */
3885
CHECK_FPU_FEATURE(dc, VIS1);
2798
3886
gen_op_load_fpr_DT0(DFPREG(rs1));
2799
3887
gen_op_load_fpr_DT1(DFPREG(rs2));
2800
gen_op_fpadd32();
3888
gen_helper_fpadd32();
2801
3889
gen_op_store_DT0_fpr(DFPREG(rd));
2802
3890
break;
2803
3891
case 0x053: /* VIS I fpadd32s */
2804
gen_op_load_fpr_FT0(rs1);
2805
gen_op_load_fpr_FT1(rs2);
2806
gen_op_fpadd32s();
2807
gen_op_store_FT0_fpr(rd);
3892
CHECK_FPU_FEATURE(dc, VIS1);
3893
gen_helper_fpadd32s(cpu_fpr[rd],
3894
cpu_fpr[rs1], cpu_fpr[rs2]);
2808
3895
break;
2809
3896
case 0x054: /* VIS I fpsub16 */
3897
CHECK_FPU_FEATURE(dc, VIS1);
2810
3898
gen_op_load_fpr_DT0(DFPREG(rs1));
2811
3899
gen_op_load_fpr_DT1(DFPREG(rs2));
2812
gen_op_fpsub16();
3900
gen_helper_fpsub16();
2813
3901
gen_op_store_DT0_fpr(DFPREG(rd));
2814
3902
break;
2815
3903
case 0x055: /* VIS I fpsub16s */
2816
gen_op_load_fpr_FT0(rs1);
2817
gen_op_load_fpr_FT1(rs2);
2818
gen_op_fpsub16s();
2819
gen_op_store_FT0_fpr(rd);
3904
CHECK_FPU_FEATURE(dc, VIS1);
3905
gen_helper_fpsub16s(cpu_fpr[rd],
3906
cpu_fpr[rs1], cpu_fpr[rs2]);
2820
3907
break;
2821
3908
case 0x056: /* VIS I fpsub32 */
3909
CHECK_FPU_FEATURE(dc, VIS1);
2822
3910
gen_op_load_fpr_DT0(DFPREG(rs1));
2823
3911
gen_op_load_fpr_DT1(DFPREG(rs2));
2824
gen_op_fpadd32();
3912
gen_helper_fpsub32();
2825
3913
gen_op_store_DT0_fpr(DFPREG(rd));
2826
3914
break;
2827
3915
case 0x057: /* VIS I fpsub32s */
2828
gen_op_load_fpr_FT0(rs1);
2829
gen_op_load_fpr_FT1(rs2);
2830
gen_op_fpsub32s();
2831
gen_op_store_FT0_fpr(rd);
3916
CHECK_FPU_FEATURE(dc, VIS1);
3917
gen_helper_fpsub32s(cpu_fpr[rd],
3918
cpu_fpr[rs1], cpu_fpr[rs2]);
2832
3919
break;
2833
3920
case 0x060: /* VIS I fzero */
2834
gen_op_movl_DT0_0();
2835
gen_op_store_DT0_fpr(DFPREG(rd));
3921
CHECK_FPU_FEATURE(dc, VIS1);
3922
tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], 0);
3923
tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], 0);
2836
3924
break;
2837
3925
case 0x061: /* VIS I fzeros */
2838
gen_op_movl_FT0_0();
2839
gen_op_store_FT0_fpr(rd);
3926
CHECK_FPU_FEATURE(dc, VIS1);
3927
tcg_gen_movi_i32(cpu_fpr[rd], 0);
2840
3928
break;
2841
3929
case 0x062: /* VIS I fnor */
2842
gen_op_load_fpr_DT0(DFPREG(rs1));
2843
gen_op_load_fpr_DT1(DFPREG(rs2));
2844
gen_op_fnor();
2845
gen_op_store_DT0_fpr(DFPREG(rd));
3930
CHECK_FPU_FEATURE(dc, VIS1);
3931
tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
3932
cpu_fpr[DFPREG(rs2)]);
3933
tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
3934
cpu_fpr[DFPREG(rs2) + 1]);
2846
3935
break;
2847
3936
case 0x063: /* VIS I fnors */
2848
gen_op_load_fpr_FT0(rs1);
2849
gen_op_load_fpr_FT1(rs2);
2850
gen_op_fnors();
2851
gen_op_store_FT0_fpr(rd);
3937
CHECK_FPU_FEATURE(dc, VIS1);
3938
tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
2852
3939
break;
2853
3940
case 0x064: /* VIS I fandnot2 */
2854
gen_op_load_fpr_DT1(DFPREG(rs1));
2855
gen_op_load_fpr_DT0(DFPREG(rs2));
2856
gen_op_fandnot();
2857
gen_op_store_DT0_fpr(DFPREG(rd));
3941
CHECK_FPU_FEATURE(dc, VIS1);
3942
tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
3943
cpu_fpr[DFPREG(rs2)]);
3944
tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
3945
cpu_fpr[DFPREG(rs1) + 1],
3946
cpu_fpr[DFPREG(rs2) + 1]);
2858
3947
break;
2859
3948
case 0x065: /* VIS I fandnot2s */
2860
gen_op_load_fpr_FT1(rs1);
2861
gen_op_load_fpr_FT0(rs2);
2862
gen_op_fandnots();
2863
gen_op_store_FT0_fpr(rd);
3949
CHECK_FPU_FEATURE(dc, VIS1);
3950
tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
2864
3951
break;
2865
3952
case 0x066: /* VIS I fnot2 */
2866
gen_op_load_fpr_DT1(DFPREG(rs2));
2867
gen_op_fnot();
2868
gen_op_store_DT0_fpr(DFPREG(rd));
3953
CHECK_FPU_FEATURE(dc, VIS1);
3954
tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)]);
3955
tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
3956
cpu_fpr[DFPREG(rs2) + 1]);
2869
3957
break;
2870
3958
case 0x067: /* VIS I fnot2s */
2871
gen_op_load_fpr_FT1(rs2);
2872
gen_op_fnot();
2873
gen_op_store_FT0_fpr(rd);
3959
CHECK_FPU_FEATURE(dc, VIS1);
3960
tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs2]);
2874
3961
break;
2875
3962
case 0x068: /* VIS I fandnot1 */
2876
gen_op_load_fpr_DT0(DFPREG(rs1));
2877
gen_op_load_fpr_DT1(DFPREG(rs2));
2878
gen_op_fandnot();
2879
gen_op_store_DT0_fpr(DFPREG(rd));
3963
CHECK_FPU_FEATURE(dc, VIS1);
3964
tcg_gen_andc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)],
3965
cpu_fpr[DFPREG(rs1)]);
3966
tcg_gen_andc_i32(cpu_fpr[DFPREG(rd) + 1],
3967
cpu_fpr[DFPREG(rs2) + 1],
3968
cpu_fpr[DFPREG(rs1) + 1]);
2880
3969
break;
2881
3970
case 0x069: /* VIS I fandnot1s */
2882
gen_op_load_fpr_FT0(rs1);
2883
gen_op_load_fpr_FT1(rs2);
2884
gen_op_fandnots();
2885
gen_op_store_FT0_fpr(rd);
3971
CHECK_FPU_FEATURE(dc, VIS1);
3972
tcg_gen_andc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]);
2886
3973
break;
2887
3974
case 0x06a: /* VIS I fnot1 */
2888
gen_op_load_fpr_DT1(DFPREG(rs1));
2889
gen_op_fnot();
2890
gen_op_store_DT0_fpr(DFPREG(rd));
3975
CHECK_FPU_FEATURE(dc, VIS1);
3976
tcg_gen_not_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]);
3977
tcg_gen_not_i32(cpu_fpr[DFPREG(rd) + 1],
3978
cpu_fpr[DFPREG(rs1) + 1]);
2891
3979
break;
2892
3980
case 0x06b: /* VIS I fnot1s */
2893
gen_op_load_fpr_FT1(rs1);
2894
gen_op_fnot();
2895
gen_op_store_FT0_fpr(rd);
3981
CHECK_FPU_FEATURE(dc, VIS1);
3982
tcg_gen_not_i32(cpu_fpr[rd], cpu_fpr[rs1]);
2896
3983
break;
2897
3984
case 0x06c: /* VIS I fxor */
2898
gen_op_load_fpr_DT0(DFPREG(rs1));
2899
gen_op_load_fpr_DT1(DFPREG(rs2));
2900
gen_op_fxor();
2901
gen_op_store_DT0_fpr(DFPREG(rd));
3985
CHECK_FPU_FEATURE(dc, VIS1);
3986
tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
3987
cpu_fpr[DFPREG(rs2)]);
3988
tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1],
3989
cpu_fpr[DFPREG(rs1) + 1],
3990
cpu_fpr[DFPREG(rs2) + 1]);
2902
3991
break;
2903
3992
case 0x06d: /* VIS I fxors */
2904
gen_op_load_fpr_FT0(rs1);
2905
gen_op_load_fpr_FT1(rs2);
2906
gen_op_fxors();
2907
gen_op_store_FT0_fpr(rd);
3993
CHECK_FPU_FEATURE(dc, VIS1);
3994
tcg_gen_xor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
2908
3995
break;
2909
3996
case 0x06e: /* VIS I fnand */
2910
gen_op_load_fpr_DT0(DFPREG(rs1));
2911
gen_op_load_fpr_DT1(DFPREG(rs2));
2912
gen_op_fnand();
2913
gen_op_store_DT0_fpr(DFPREG(rd));
3997
CHECK_FPU_FEATURE(dc, VIS1);
3998
tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
3999
cpu_fpr[DFPREG(rs2)]);
4000
tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
4001
cpu_fpr[DFPREG(rs2) + 1]);
2914
4002
break;
2915
4003
case 0x06f: /* VIS I fnands */
2916
gen_op_load_fpr_FT0(rs1);
2917
gen_op_load_fpr_FT1(rs2);
2918
gen_op_fnands();
2919
gen_op_store_FT0_fpr(rd);
4004
CHECK_FPU_FEATURE(dc, VIS1);
4005
tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
2920
4006
break;
2921
4007
case 0x070: /* VIS I fand */
2922
gen_op_load_fpr_DT0(DFPREG(rs1));
2923
gen_op_load_fpr_DT1(DFPREG(rs2));
2924
gen_op_fand();
2925
gen_op_store_DT0_fpr(DFPREG(rd));
4008
CHECK_FPU_FEATURE(dc, VIS1);
4009
tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
4010
cpu_fpr[DFPREG(rs2)]);
4011
tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1],
4012
cpu_fpr[DFPREG(rs1) + 1],
4013
cpu_fpr[DFPREG(rs2) + 1]);
2926
4014
break;
2927
4015
case 0x071: /* VIS I fands */
2928
gen_op_load_fpr_FT0(rs1);
2929
gen_op_load_fpr_FT1(rs2);
2930
gen_op_fands();
2931
gen_op_store_FT0_fpr(rd);
4016
CHECK_FPU_FEATURE(dc, VIS1);
4017
tcg_gen_and_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
2932
4018
break;
2933
4019
case 0x072: /* VIS I fxnor */
2934
gen_op_load_fpr_DT0(DFPREG(rs1));
2935
gen_op_load_fpr_DT1(DFPREG(rs2));
2936
gen_op_fxnor();
2937
gen_op_store_DT0_fpr(DFPREG(rd));
4020
CHECK_FPU_FEATURE(dc, VIS1);
4021
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1);
4022
tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32,
4023
cpu_fpr[DFPREG(rs1)]);
4024
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1);
4025
tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32,
4026
cpu_fpr[DFPREG(rs1) + 1]);
2938
4027
break;
2939
4028
case 0x073: /* VIS I fxnors */
2940
gen_op_load_fpr_FT0(rs1);
2941
gen_op_load_fpr_FT1(rs2);
2942
gen_op_fxnors();
2943
gen_op_store_FT0_fpr(rd);
4029
CHECK_FPU_FEATURE(dc, VIS1);
4030
tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
4031
tcg_gen_xor_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]);
2944
4032
break;
2945
4033
case 0x074: /* VIS I fsrc1 */
2946
gen_op_load_fpr_DT0(DFPREG(rs1));
2947
gen_op_store_DT0_fpr(DFPREG(rd));
4034
CHECK_FPU_FEATURE(dc, VIS1);
4035
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]);
4036
tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
4037
cpu_fpr[DFPREG(rs1) + 1]);
2948
4038
break;
2949
4039
case 0x075: /* VIS I fsrc1s */
2950
gen_op_load_fpr_FT0(rs1);
2951
gen_op_store_FT0_fpr(rd);
4040
CHECK_FPU_FEATURE(dc, VIS1);
4041
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs1]);
2952
4042
break;
2953
4043
case 0x076: /* VIS I fornot2 */
2954
gen_op_load_fpr_DT1(DFPREG(rs1));
2955
gen_op_load_fpr_DT0(DFPREG(rs2));
2956
gen_op_fornot();
2957
gen_op_store_DT0_fpr(DFPREG(rd));
4044
CHECK_FPU_FEATURE(dc, VIS1);
4045
tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
4046
cpu_fpr[DFPREG(rs2)]);
4047
tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
4048
cpu_fpr[DFPREG(rs1) + 1],
4049
cpu_fpr[DFPREG(rs2) + 1]);
2958
4050
break;
2959
4051
case 0x077: /* VIS I fornot2s */
2960
gen_op_load_fpr_FT1(rs1);
2961
gen_op_load_fpr_FT0(rs2);
2962
gen_op_fornots();
2963
gen_op_store_FT0_fpr(rd);
4052
CHECK_FPU_FEATURE(dc, VIS1);
4053
tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
2964
4054
break;
2965
4055
case 0x078: /* VIS I fsrc2 */
4056
CHECK_FPU_FEATURE(dc, VIS1);
2966
4057
gen_op_load_fpr_DT0(DFPREG(rs2));
2967
4058
gen_op_store_DT0_fpr(DFPREG(rd));
2968
4059
break;
2969
4060
case 0x079: /* VIS I fsrc2s */
2970
gen_op_load_fpr_FT0(rs2);
2971
gen_op_store_FT0_fpr(rd);
4061
CHECK_FPU_FEATURE(dc, VIS1);
4062
tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
2972
4063
break;
2973
4064
case 0x07a: /* VIS I fornot1 */
2974
gen_op_load_fpr_DT0(DFPREG(rs1));
2975
gen_op_load_fpr_DT1(DFPREG(rs2));
2976
gen_op_fornot();
2977
gen_op_store_DT0_fpr(DFPREG(rd));
4065
CHECK_FPU_FEATURE(dc, VIS1);
4066
tcg_gen_orc_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)],
4067
cpu_fpr[DFPREG(rs1)]);
4068
tcg_gen_orc_i32(cpu_fpr[DFPREG(rd) + 1],
4069
cpu_fpr[DFPREG(rs2) + 1],
4070
cpu_fpr[DFPREG(rs1) + 1]);
2978
4071
break;
2979
4072
case 0x07b: /* VIS I fornot1s */
2980
gen_op_load_fpr_FT0(rs1);
2981
gen_op_load_fpr_FT1(rs2);
2982
gen_op_fornots();
2983
gen_op_store_FT0_fpr(rd);
4073
CHECK_FPU_FEATURE(dc, VIS1);
4074
tcg_gen_orc_i32(cpu_fpr[rd], cpu_fpr[rs2], cpu_fpr[rs1]);
2984
4075
break;
2985
4076
case 0x07c: /* VIS I for */
2986
gen_op_load_fpr_DT0(DFPREG(rs1));
2987
gen_op_load_fpr_DT1(DFPREG(rs2));
2988
gen_op_for();
2989
gen_op_store_DT0_fpr(DFPREG(rd));
4077
CHECK_FPU_FEATURE(dc, VIS1);
4078
tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
4079
cpu_fpr[DFPREG(rs2)]);
4080
tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1],
4081
cpu_fpr[DFPREG(rs1) + 1],
4082
cpu_fpr[DFPREG(rs2) + 1]);
2990
4083
break;
2991
4084
case 0x07d: /* VIS I fors */
2992
gen_op_load_fpr_FT0(rs1);
2993
gen_op_load_fpr_FT1(rs2);
2994
gen_op_fors();
2995
gen_op_store_FT0_fpr(rd);
4085
CHECK_FPU_FEATURE(dc, VIS1);
4086
tcg_gen_or_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
2996
4087
break;
2997
4088
case 0x07e: /* VIS I fone */
2998
gen_op_movl_DT0_1();
2999
gen_op_store_DT0_fpr(DFPREG(rd));
4089
CHECK_FPU_FEATURE(dc, VIS1);
4090
tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], -1);
4091
tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], -1);
3000
4092
break;
3001
4093
case 0x07f: /* VIS I fones */
3002
gen_op_movl_FT0_1();
3003
gen_op_store_FT0_fpr(rd);
4094
CHECK_FPU_FEATURE(dc, VIS1);
4095
tcg_gen_movi_i32(cpu_fpr[rd], -1);
3004
4096
break;
3005
4097
case 0x080: /* VIS I shutdown */
3006
4098
case 0x081: /* VIS II siam */
3020
4112
#endif
3021
4113
#ifdef TARGET_SPARC64
3022
4114
} else if (xop == 0x39) { /* V9 return */
3023
rs1 = GET_FIELD(insn, 13, 17);
3024
save_state(dc);
3025
gen_movl_reg_T0(rs1);
4115
TCGv_i32 r_const;
4116
4117
save_state(dc, cpu_cond);
4118
cpu_src1 = get_src1(insn, cpu_src1);
3026
4119
if (IS_IMM) { /* immediate */
3027
4120
rs2 = GET_FIELDs(insn, 19, 31);
3028
#if defined(OPTIM)
3029
if (rs2) {
3030
#endif
3031
gen_movl_simm_T1(rs2);
3032
gen_op_add_T1_T0();
3033
#if defined(OPTIM)
3034
}
3035
#endif
4121
tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
3036
4122
} else { /* register */
3037
4123
rs2 = GET_FIELD(insn, 27, 31);
3038
#if defined(OPTIM)
3039
4124
if (rs2) {
3040
#endif
3041
gen_movl_reg_T1(rs2);
3042
gen_op_add_T1_T0();
3043
#if defined(OPTIM)
3044
}
3045
#endif
4125
gen_movl_reg_TN(rs2, cpu_src2);
4126
tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4127
} else
4128
tcg_gen_mov_tl(cpu_dst, cpu_src1);
3046
4129
}
3047
gen_op_restore();
3048
gen_mov_pc_npc(dc);
3049
gen_op_check_align_T0_3();
3050
gen_op_movl_npc_T0();
4130
gen_helper_restore();
4131
gen_mov_pc_npc(dc, cpu_cond);
4132
r_const = tcg_const_i32(3);
4133
gen_helper_check_align(cpu_dst, r_const);
4134
tcg_temp_free_i32(r_const);
4135
tcg_gen_mov_tl(cpu_npc, cpu_dst);
3051
4136
dc->npc = DYNAMIC_PC;
3052
4137
goto jmp_insn;
3053
4138
#endif
3054
4139
} else {
3055
rs1 = GET_FIELD(insn, 13, 17);
3056
gen_movl_reg_T0(rs1);
4140
cpu_src1 = get_src1(insn, cpu_src1);
3057
4141
if (IS_IMM) { /* immediate */
3058
4142
rs2 = GET_FIELDs(insn, 19, 31);
3059
#if defined(OPTIM)
3060
if (rs2) {
3061
#endif
3062
gen_movl_simm_T1(rs2);
3063
gen_op_add_T1_T0();
3064
#if defined(OPTIM)
3065
}
3066
#endif
4143
tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
3067
4144
} else { /* register */
3068
4145
rs2 = GET_FIELD(insn, 27, 31);
3069
#if defined(OPTIM)
3070
4146
if (rs2) {
3071
#endif
3072
gen_movl_reg_T1(rs2);
3073
gen_op_add_T1_T0();
3074
#if defined(OPTIM)
3075
}
3076
#endif
4147
gen_movl_reg_TN(rs2, cpu_src2);
4148
tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
4149
} else
4150
tcg_gen_mov_tl(cpu_dst, cpu_src1);
3077
4151
}
3078
4152
switch (xop) {
3079
4153
case 0x38: /* jmpl */
3080
4154
{
3081
if (rd != 0) {
3082
#ifdef TARGET_SPARC64
3083
if (dc->pc == (uint32_t)dc->pc) {
3084
gen_op_movl_T1_im(dc->pc);
3085
} else {
3086
gen_op_movq_T1_im64(dc->pc >> 32, dc->pc);
3087
}
3088
#else
3089
gen_op_movl_T1_im(dc->pc);
3090
#endif
3091
gen_movl_T1_reg(rd);
3092
}
3093
gen_mov_pc_npc(dc);
3094
gen_op_check_align_T0_3();
3095
gen_op_movl_npc_T0();
4155
TCGv r_pc;
4156
TCGv_i32 r_const;
4157
4158
r_pc = tcg_const_tl(dc->pc);
4159
gen_movl_TN_reg(rd, r_pc);
4160
tcg_temp_free(r_pc);
4161
gen_mov_pc_npc(dc, cpu_cond);
4162
r_const = tcg_const_i32(3);
4163
gen_helper_check_align(cpu_dst, r_const);
4164
tcg_temp_free_i32(r_const);
4165
tcg_gen_mov_tl(cpu_npc, cpu_dst);
3096
4166
dc->npc = DYNAMIC_PC;
3097
4167
}
3098
4168
goto jmp_insn;
3099
4169
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
3100
4170
case 0x39: /* rett, V9 return */
3101
4171
{
4172
TCGv_i32 r_const;
4173
3102
4174
if (!supervisor(dc))
3103
4175
goto priv_insn;
3104
gen_mov_pc_npc(dc);
3105
gen_op_check_align_T0_3();
3106
gen_op_movl_npc_T0();
4176
gen_mov_pc_npc(dc, cpu_cond);
4177
r_const = tcg_const_i32(3);
4178
gen_helper_check_align(cpu_dst, r_const);
4179
tcg_temp_free_i32(r_const);
4180
tcg_gen_mov_tl(cpu_npc, cpu_dst);
3107
4181
dc->npc = DYNAMIC_PC;
3108
gen_op_rett();
4182
gen_helper_rett();
3109
4183
}
3110
4184
goto jmp_insn;
3111
4185
#endif
3112
4186
case 0x3b: /* flush */
3113
gen_op_flush_T0();
4187
if (!((dc)->def->features & CPU_FEATURE_FLUSH))
4188
goto unimp_flush;
4189
gen_helper_flush(cpu_dst);
3114
4190
break;
3115
4191
case 0x3c: /* save */
3116
save_state(dc);
3117
gen_op_save();
3118
gen_movl_T0_reg(rd);
4192
save_state(dc, cpu_cond);
4193
gen_helper_save();
4194
gen_movl_TN_reg(rd, cpu_dst);
3119
4195
break;
3120
4196
case 0x3d: /* restore */
3121
save_state(dc);
3122
gen_op_restore();
3123
gen_movl_T0_reg(rd);
4197
save_state(dc, cpu_cond);
4198
gen_helper_restore();
4199
gen_movl_TN_reg(rd, cpu_dst);
3124
4200
break;
3125
4201
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
3126
4202
case 0x3e: /* V9 done/retry */
3131
4207
goto priv_insn;
3132
4208
dc->npc = DYNAMIC_PC;
3133
4209
dc->pc = DYNAMIC_PC;
3134
gen_op_done();
4210
gen_helper_done();
3135
4211
goto jmp_insn;
3136
4212
case 1:
3137
4213
if (!supervisor(dc))
3138
4214
goto priv_insn;
3139
4215
dc->npc = DYNAMIC_PC;
3140
4216
dc->pc = DYNAMIC_PC;
3141
gen_op_retry();
4217
gen_helper_retry();
3142
4218
goto jmp_insn;
3143
4219
default:
3144
4220
goto illegal_insn;
3156
4232
case 3: /* load/store instructions */
3157
4233
{
3158
4234
unsigned int xop = GET_FIELD(insn, 7, 12);
3159
rs1 = GET_FIELD(insn, 13, 17);
3160
save_state(dc);
3161
gen_movl_reg_T0(rs1);
3162
if (xop == 0x3c || xop == 0x3e)
3163
{
4235
4236
cpu_src1 = get_src1(insn, cpu_src1);
4237
if (xop == 0x3c || xop == 0x3e) { // V9 casa/casxa
3164
4238
rs2 = GET_FIELD(insn, 27, 31);
3165
gen_movl_reg_T1(rs2);
3166
}
3167
else if (IS_IMM) { /* immediate */
4239
gen_movl_reg_TN(rs2, cpu_src2);
4240
tcg_gen_mov_tl(cpu_addr, cpu_src1);
4241
} else if (IS_IMM) { /* immediate */
3168
4242
rs2 = GET_FIELDs(insn, 19, 31);
3169
#if defined(OPTIM)
3170
if (rs2 != 0) {
3171
#endif
3172
gen_movl_simm_T1(rs2);
3173
gen_op_add_T1_T0();
3174
#if defined(OPTIM)
3175
}
3176
#endif
4243
tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
3177
4244
} else { /* register */
3178
4245
rs2 = GET_FIELD(insn, 27, 31);
3179
#if defined(OPTIM)
3180
4246
if (rs2 != 0) {
3181
#endif
3182
gen_movl_reg_T1(rs2);
3183
gen_op_add_T1_T0();
3184
#if defined(OPTIM)
3185
}
3186
#endif
4247
gen_movl_reg_TN(rs2, cpu_src2);
4248
tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4249
} else
4250
tcg_gen_mov_tl(cpu_addr, cpu_src1);
3187
4251
}
3188
4252
if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
3189
4253
(xop > 0x17 && xop <= 0x1d ) ||
3190
4254
(xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
3191
4255
switch (xop) {
3192
case 0x0: /* load word */
3193
gen_op_check_align_T0_3();
3194
#ifndef TARGET_SPARC64
3195
gen_op_ldst(ld);
3196
#else
3197
gen_op_ldst(lduw);
3198
#endif
4256
case 0x0: /* load unsigned word */
4257
gen_address_mask(dc, cpu_addr);
4258
tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
3199
4259
break;
3200
4260
case 0x1: /* load unsigned byte */
3201
gen_op_ldst(ldub);
4261
gen_address_mask(dc, cpu_addr);
4262
tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
3202
4263
break;
3203
4264
case 0x2: /* load unsigned halfword */
3204
gen_op_check_align_T0_1();
3205
gen_op_ldst(lduh);
4265
gen_address_mask(dc, cpu_addr);
4266
tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
3206
4267
break;
3207
4268
case 0x3: /* load double word */
3208
4269
if (rd & 1)
3209
4270
goto illegal_insn;
3210
gen_op_check_align_T0_7();
3211
gen_op_ldst(ldd);
3212
gen_movl_T0_reg(rd + 1);
4271
else {
4272
TCGv_i32 r_const;
4273
4274
save_state(dc, cpu_cond);
4275
r_const = tcg_const_i32(7);
4276
gen_helper_check_align(cpu_addr, r_const); // XXX remove
4277
tcg_temp_free_i32(r_const);
4278
gen_address_mask(dc, cpu_addr);
4279
tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4280
tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4281
tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4282
gen_movl_TN_reg(rd + 1, cpu_tmp0);
4283
tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4284
tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4285
tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4286
}
3213
4287
break;
3214
4288
case 0x9: /* load signed byte */
3215
gen_op_ldst(ldsb);
4289
gen_address_mask(dc, cpu_addr);
4290
tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
3216
4291
break;
3217
4292
case 0xa: /* load signed halfword */
3218
gen_op_check_align_T0_1();
3219
gen_op_ldst(ldsh);
4293
gen_address_mask(dc, cpu_addr);
4294
tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
3220
4295
break;
3221
4296
case 0xd: /* ldstub -- XXX: should be atomically */
3222
gen_op_ldst(ldstub);
4297
{
4298
TCGv r_const;
4299
4300
gen_address_mask(dc, cpu_addr);
4301
tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4302
r_const = tcg_const_tl(0xff);
4303
tcg_gen_qemu_st8(r_const, cpu_addr, dc->mem_idx);
4304
tcg_temp_free(r_const);
4305
}
3223
4306
break;
3224
case 0x0f: /* swap register with memory. Also atomically */
3225
gen_op_check_align_T0_3();
3226
gen_movl_reg_T1(rd);
3227
gen_op_ldst(swap);
4307
case 0x0f: /* swap register with memory. Also
4308
atomically */
4309
CHECK_IU_FEATURE(dc, SWAP);
4310
gen_movl_reg_TN(rd, cpu_val);
4311
gen_address_mask(dc, cpu_addr);
4312
tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
4313
tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4314
tcg_gen_mov_tl(cpu_val, cpu_tmp0);
3228
4315
break;
3229
4316
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
3230
4317
case 0x10: /* load word alternate */
3234
4321
if (!supervisor(dc))
3235
4322
goto priv_insn;
3236
4323
#endif
3237
gen_op_check_align_T0_3();
3238
gen_ld_asi(insn, 4, 0);
4324
save_state(dc, cpu_cond);
4325
gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
3239
4326
break;
3240
4327
case 0x11: /* load unsigned byte alternate */
3241
4328
#ifndef TARGET_SPARC64
3244
4331
if (!supervisor(dc))
3245
4332
goto priv_insn;
3246
4333
#endif
3247
gen_ld_asi(insn, 1, 0);
4334
save_state(dc, cpu_cond);
4335
gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
3248
4336
break;
3249
4337
case 0x12: /* load unsigned halfword alternate */
3250
4338
#ifndef TARGET_SPARC64
3253
4341
if (!supervisor(dc))
3254
4342
goto priv_insn;
3255
4343
#endif
3256
gen_op_check_align_T0_1();
3257
gen_ld_asi(insn, 2, 0);
4344
save_state(dc, cpu_cond);
4345
gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
3258
4346
break;
3259
4347
case 0x13: /* load double word alternate */
3260
4348
#ifndef TARGET_SPARC64
3265
4353
#endif
3266
4354
if (rd & 1)
3267
4355
goto illegal_insn;
3268
gen_op_check_align_T0_7();
3269
gen_ldda_asi(insn);
3270
gen_movl_T0_reg(rd + 1);
3271
break;
4356
save_state(dc, cpu_cond);
4357
gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
4358
goto skip_move;
3272
4359
case 0x19: /* load signed byte alternate */
3273
4360
#ifndef TARGET_SPARC64
3274
4361
if (IS_IMM)
3276
4363
if (!supervisor(dc))
3277
4364
goto priv_insn;
3278
4365
#endif
3279
gen_ld_asi(insn, 1, 1);
4366
save_state(dc, cpu_cond);
4367
gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
3280
4368
break;
3281
4369
case 0x1a: /* load signed halfword alternate */
3282
4370
#ifndef TARGET_SPARC64
3285
4373
if (!supervisor(dc))
3286
4374
goto priv_insn;
3287
4375
#endif
3288
gen_op_check_align_T0_1();
3289
gen_ld_asi(insn, 2, 1);
4376
save_state(dc, cpu_cond);
4377
gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
3290
4378
break;
3291
4379
case 0x1d: /* ldstuba -- XXX: should be atomically */
3292
4380
#ifndef TARGET_SPARC64
3295
4383
if (!supervisor(dc))
3296
4384
goto priv_insn;
3297
4385
#endif
3298
gen_ldstub_asi(insn);
4386
save_state(dc, cpu_cond);
4387
gen_ldstub_asi(cpu_val, cpu_addr, insn);
3299
4388
break;
3300
case 0x1f: /* swap reg with alt. memory. Also atomically */
4389
case 0x1f: /* swap reg with alt. memory. Also
4390
atomically */
4391
CHECK_IU_FEATURE(dc, SWAP);
3301
4392
#ifndef TARGET_SPARC64
3302
4393
if (IS_IMM)
3303
4394
goto illegal_insn;
3304
4395
if (!supervisor(dc))
3305
4396
goto priv_insn;
3306
4397
#endif
3307
gen_op_check_align_T0_3();
3308
gen_movl_reg_T1(rd);
3309
gen_swap_asi(insn);
4398
save_state(dc, cpu_cond);
4399
gen_movl_reg_TN(rd, cpu_val);
4400
gen_swap_asi(cpu_val, cpu_addr, insn);
3310
4401
break;
3311
4402
3312
4403
#ifndef TARGET_SPARC64
3318
4409
#endif
3319
4410
#ifdef TARGET_SPARC64
3320
4411
case 0x08: /* V9 ldsw */
3321
gen_op_check_align_T0_3();
3322
gen_op_ldst(ldsw);
4412
gen_address_mask(dc, cpu_addr);
4413
tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
3323
4414
break;
3324
4415
case 0x0b: /* V9 ldx */
3325
gen_op_check_align_T0_7();
3326
gen_op_ldst(ldx);
4416
gen_address_mask(dc, cpu_addr);
4417
tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
3327
4418
break;
3328
4419
case 0x18: /* V9 ldswa */
3329
gen_op_check_align_T0_3();
3330
gen_ld_asi(insn, 4, 1);
4420
save_state(dc, cpu_cond);
4421
gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
3331
4422
break;
3332
4423
case 0x1b: /* V9 ldxa */
3333
gen_op_check_align_T0_7();
3334
gen_ld_asi(insn, 8, 0);
4424
save_state(dc, cpu_cond);
4425
gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
3335
4426
break;
3336
4427
case 0x2d: /* V9 prefetch, no effect */
3337
4428
goto skip_move;
3338
4429
case 0x30: /* V9 ldfa */
3339
gen_op_check_align_T0_3();
3340
gen_ldf_asi(insn, 4, rd);
4430
save_state(dc, cpu_cond);
4431
gen_ldf_asi(cpu_addr, insn, 4, rd);
3341
4432
goto skip_move;
3342
4433
case 0x33: /* V9 lddfa */
3343
gen_op_check_align_T0_3();
3344
gen_ldf_asi(insn, 8, DFPREG(rd));
4434
save_state(dc, cpu_cond);
4435
gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
3345
4436
goto skip_move;
3346
4437
case 0x3d: /* V9 prefetcha, no effect */
3347
4438
goto skip_move;
3348
4439
case 0x32: /* V9 ldqfa */
3349
#if defined(CONFIG_USER_ONLY)
3350
gen_op_check_align_T0_3();
3351
gen_ldf_asi(insn, 16, QFPREG(rd));
4440
CHECK_FPU_FEATURE(dc, FLOAT128);
4441
save_state(dc, cpu_cond);
4442
gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
3352
4443
goto skip_move;
3353
#else
3354
goto nfpu_insn;
3355
#endif
3356
4444
#endif
3357
4445
default:
3358
4446
goto illegal_insn;
3359
4447
}
3360
gen_movl_T1_reg(rd);
3361
#ifdef TARGET_SPARC64
4448
gen_movl_TN_reg(rd, cpu_val);
4449
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
3362
4450
skip_move: ;
3363
4451
#endif
3364
4452
} else if (xop >= 0x20 && xop < 0x24) {
3365
if (gen_trap_ifnofpu(dc))
4453
if (gen_trap_ifnofpu(dc, cpu_cond))
3366
4454
goto jmp_insn;
4455
save_state(dc, cpu_cond);
3367
4456
switch (xop) {
3368
4457
case 0x20: /* load fpreg */
3369
gen_op_check_align_T0_3();
3370
gen_op_ldst(ldf);
3371
gen_op_store_FT0_fpr(rd);
4458
gen_address_mask(dc, cpu_addr);
4459
tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
4460
tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0);
3372
4461
break;
3373
case 0x21: /* load fsr */
3374
gen_op_check_align_T0_3();
3375
gen_op_ldst(ldf);
3376
gen_op_ldfsr();
4462
case 0x21: /* ldfsr, V9 ldxfsr */
4463
#ifdef TARGET_SPARC64
4464
gen_address_mask(dc, cpu_addr);
4465
if (rd == 1) {
4466
tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4467
gen_helper_ldxfsr(cpu_tmp64);
4468
} else
4469
#else
4470
{
4471
tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4472
gen_helper_ldfsr(cpu_tmp32);
4473
}
4474
#endif
3377
4475
break;
3378
4476
case 0x22: /* load quad fpreg */
3379
#if defined(CONFIG_USER_ONLY)
3380
gen_op_check_align_T0_7();
3381
gen_op_ldst(ldqf);
3382
gen_op_store_QT0_fpr(QFPREG(rd));
4477
{
4478
TCGv_i32 r_const;
4479
4480
CHECK_FPU_FEATURE(dc, FLOAT128);
4481
r_const = tcg_const_i32(dc->mem_idx);
4482
gen_helper_ldqf(cpu_addr, r_const);
4483
tcg_temp_free_i32(r_const);
4484
gen_op_store_QT0_fpr(QFPREG(rd));
4485
}
3383
4486
break;
3384
#else
3385
goto nfpu_insn;
3386
#endif
3387
4487
case 0x23: /* load double fpreg */
3388
gen_op_check_align_T0_7();
3389
gen_op_ldst(lddf);
3390
gen_op_store_DT0_fpr(DFPREG(rd));
4488
{
4489
TCGv_i32 r_const;
4490
4491
r_const = tcg_const_i32(dc->mem_idx);
4492
gen_helper_lddf(cpu_addr, r_const);
4493
tcg_temp_free_i32(r_const);
4494
gen_op_store_DT0_fpr(DFPREG(rd));
4495
}
3391
4496
break;
3392
4497
default:
3393
4498
goto illegal_insn;
3394
4499
}
3395
4500
} else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
3396
4501
xop == 0xe || xop == 0x1e) {
3397
gen_movl_reg_T1(rd);
4502
gen_movl_reg_TN(rd, cpu_val);
3398
4503
switch (xop) {
3399
case 0x4:
3400
gen_op_check_align_T0_3();
3401
gen_op_ldst(st);
3402
break;
3403
case 0x5:
3404
gen_op_ldst(stb);
3405
break;
3406
case 0x6:
3407
gen_op_check_align_T0_1();
3408
gen_op_ldst(sth);
3409
break;
3410
case 0x7:
4504
case 0x4: /* store word */
4505
gen_address_mask(dc, cpu_addr);
4506
tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4507
break;
4508
case 0x5: /* store byte */
4509
gen_address_mask(dc, cpu_addr);
4510
tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4511
break;
4512
case 0x6: /* store halfword */
4513
gen_address_mask(dc, cpu_addr);
4514
tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4515
break;
4516
case 0x7: /* store double word */
3411
4517
if (rd & 1)
3412
4518
goto illegal_insn;
3413
gen_op_check_align_T0_7();
3414
flush_T2(dc);
3415
gen_movl_reg_T2(rd + 1);
3416
gen_op_ldst(std);
4519
else {
4520
TCGv_i32 r_const;
4521
4522
save_state(dc, cpu_cond);
4523
gen_address_mask(dc, cpu_addr);
4524
r_const = tcg_const_i32(7);
4525
gen_helper_check_align(cpu_addr, r_const); // XXX remove
4526
tcg_temp_free_i32(r_const);
4527
gen_movl_reg_TN(rd + 1, cpu_tmp0);
4528
tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, cpu_val);
4529
tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4530
}
3417
4531
break;
3418
4532
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
3419
case 0x14:
3420
#ifndef TARGET_SPARC64
3421
if (IS_IMM)
3422
goto illegal_insn;
3423
if (!supervisor(dc))
3424
goto priv_insn;
3425
#endif
3426
gen_op_check_align_T0_3();
3427
gen_st_asi(insn, 4);
3428
break;
3429
case 0x15:
3430
#ifndef TARGET_SPARC64
3431
if (IS_IMM)
3432
goto illegal_insn;
3433
if (!supervisor(dc))
3434
goto priv_insn;
3435
#endif
3436
gen_st_asi(insn, 1);
3437
break;
3438
case 0x16:
3439
#ifndef TARGET_SPARC64
3440
if (IS_IMM)
3441
goto illegal_insn;
3442
if (!supervisor(dc))
3443
goto priv_insn;
3444
#endif
3445
gen_op_check_align_T0_1();
3446
gen_st_asi(insn, 2);
3447
break;
3448
case 0x17:
4533
case 0x14: /* store word alternate */
4534
#ifndef TARGET_SPARC64
4535
if (IS_IMM)
4536
goto illegal_insn;
4537
if (!supervisor(dc))
4538
goto priv_insn;
4539
#endif
4540
save_state(dc, cpu_cond);
4541
gen_st_asi(cpu_val, cpu_addr, insn, 4);
4542
break;
4543
case 0x15: /* store byte alternate */
4544
#ifndef TARGET_SPARC64
4545
if (IS_IMM)
4546
goto illegal_insn;
4547
if (!supervisor(dc))
4548
goto priv_insn;
4549
#endif
4550
save_state(dc, cpu_cond);
4551
gen_st_asi(cpu_val, cpu_addr, insn, 1);
4552
break;
4553
case 0x16: /* store halfword alternate */
4554
#ifndef TARGET_SPARC64
4555
if (IS_IMM)
4556
goto illegal_insn;
4557
if (!supervisor(dc))
4558
goto priv_insn;
4559
#endif
4560
save_state(dc, cpu_cond);
4561
gen_st_asi(cpu_val, cpu_addr, insn, 2);
4562
break;
4563
case 0x17: /* store double word alternate */
3449
4564
#ifndef TARGET_SPARC64
3450
4565
if (IS_IMM)
3451
4566
goto illegal_insn;
3454
4569
#endif
3455
4570
if (rd & 1)
3456
4571
goto illegal_insn;
3457
gen_op_check_align_T0_7();
3458
flush_T2(dc);
3459
gen_movl_reg_T2(rd + 1);
3460
gen_stda_asi(insn);
4572
else {
4573
save_state(dc, cpu_cond);
4574
gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4575
}
3461
4576
break;
3462
4577
#endif
3463
4578
#ifdef TARGET_SPARC64
3464
4579
case 0x0e: /* V9 stx */
3465
gen_op_check_align_T0_7();
3466
gen_op_ldst(stx);
4580
gen_address_mask(dc, cpu_addr);
4581
tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
3467
4582
break;
3468
4583
case 0x1e: /* V9 stxa */
3469
gen_op_check_align_T0_7();
3470
gen_st_asi(insn, 8);
4584
save_state(dc, cpu_cond);
4585
gen_st_asi(cpu_val, cpu_addr, insn, 8);
3471
4586
break;
3472
4587
#endif
3473
4588
default:
3474
4589
goto illegal_insn;
3475
4590
}
3476
4591
} else if (xop > 0x23 && xop < 0x28) {
3477
if (gen_trap_ifnofpu(dc))
4592
if (gen_trap_ifnofpu(dc, cpu_cond))
3478
4593
goto jmp_insn;
4594
save_state(dc, cpu_cond);
3479
4595
switch (xop) {
3480
case 0x24:
3481
gen_op_check_align_T0_3();
3482
gen_op_load_fpr_FT0(rd);
3483
gen_op_ldst(stf);
4596
case 0x24: /* store fpreg */
4597
gen_address_mask(dc, cpu_addr);
4598
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]);
4599
tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx);
3484
4600
break;
3485
4601
case 0x25: /* stfsr, V9 stxfsr */
3486
#ifdef CONFIG_USER_ONLY
3487
gen_op_check_align_T0_3();
4602
#ifdef TARGET_SPARC64
4603
gen_address_mask(dc, cpu_addr);
4604
tcg_gen_ld_i64(cpu_tmp64, cpu_env, offsetof(CPUState, fsr));
4605
if (rd == 1)
4606
tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4607
else
4608
tcg_gen_qemu_st32(cpu_tmp64, cpu_addr, dc->mem_idx);
4609
#else
4610
tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUState, fsr));
4611
tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
3488
4612
#endif
3489
gen_op_stfsr();
3490
gen_op_ldst(stf);
3491
4613
break;
3492
4614
case 0x26:
3493
4615
#ifdef TARGET_SPARC64
3494
#if defined(CONFIG_USER_ONLY)
3495
4616
/* V9 stqf, store quad fpreg */
3496
gen_op_check_align_T0_7();
3497
gen_op_load_fpr_QT0(QFPREG(rd));
3498
gen_op_ldst(stqf);
4617
{
4618
TCGv_i32 r_const;
4619
4620
CHECK_FPU_FEATURE(dc, FLOAT128);
4621
gen_op_load_fpr_QT0(QFPREG(rd));
4622
r_const = tcg_const_i32(dc->mem_idx);
4623
gen_helper_stqf(cpu_addr, r_const);
4624
tcg_temp_free_i32(r_const);
4625
}
3499
4626
break;
3500
#else
3501
goto nfpu_insn;
3502
#endif
3503
4627
#else /* !TARGET_SPARC64 */
3504
4628
/* stdfq, store floating point queue */
3505
4629
#if defined(CONFIG_USER_ONLY)
3507
4631
#else
3508
4632
if (!supervisor(dc))
3509
4633
goto priv_insn;
3510
if (gen_trap_ifnofpu(dc))
4634
if (gen_trap_ifnofpu(dc, cpu_cond))
3511
4635
goto jmp_insn;
3512
4636
goto nfq_insn;
3513
4637
#endif
3514
4638
#endif
3515
case 0x27:
3516
gen_op_check_align_T0_7();
3517
gen_op_load_fpr_DT0(DFPREG(rd));
3518
gen_op_ldst(stdf);
4639
case 0x27: /* store double fpreg */
4640
{
4641
TCGv_i32 r_const;
4642
4643
gen_op_load_fpr_DT0(DFPREG(rd));
4644
r_const = tcg_const_i32(dc->mem_idx);
4645
gen_helper_stdf(cpu_addr, r_const);
4646
tcg_temp_free_i32(r_const);
4647
}
3519
4648
break;
3520
4649
default:
3521
4650
goto illegal_insn;
3522
4651
}
3523
4652
} else if (xop > 0x33 && xop < 0x3f) {
4653
save_state(dc, cpu_cond);
3524
4654
switch (xop) {
3525
4655
#ifdef TARGET_SPARC64
3526
4656
case 0x34: /* V9 stfa */
3527
gen_op_check_align_T0_3();
3528
gen_op_load_fpr_FT0(rd);
3529
gen_stf_asi(insn, 4, rd);
4657
gen_stf_asi(cpu_addr, insn, 4, rd);
3530
4658
break;
3531
4659
case 0x36: /* V9 stqfa */
3532
#if defined(CONFIG_USER_ONLY)
3533
gen_op_check_align_T0_7();
3534
gen_op_load_fpr_QT0(QFPREG(rd));
3535
gen_stf_asi(insn, 16, QFPREG(rd));
4660
{
4661
TCGv_i32 r_const;
4662
4663
CHECK_FPU_FEATURE(dc, FLOAT128);
4664
r_const = tcg_const_i32(7);
4665
gen_helper_check_align(cpu_addr, r_const);
4666
tcg_temp_free_i32(r_const);
4667
gen_op_load_fpr_QT0(QFPREG(rd));
4668
gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4669
}
3536
4670
break;
3537
#else
3538
goto nfpu_insn;
3539
#endif
3540
4671
case 0x37: /* V9 stdfa */
3541
gen_op_check_align_T0_3();
3542
4672
gen_op_load_fpr_DT0(DFPREG(rd));
3543
gen_stf_asi(insn, 8, DFPREG(rd));
4673
gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
3544
4674
break;
3545
4675
case 0x3c: /* V9 casa */
3546
gen_op_check_align_T0_3();
3547
flush_T2(dc);
3548
gen_movl_reg_T2(rd);
3549
gen_cas_asi(insn);
3550
gen_movl_T1_reg(rd);
4676
gen_cas_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4677
gen_movl_TN_reg(rd, cpu_val);
3551
4678
break;
3552
4679
case 0x3e: /* V9 casxa */
3553
gen_op_check_align_T0_7();
3554
flush_T2(dc);
3555
gen_movl_reg_T2(rd);
3556
gen_casx_asi(insn);
3557
gen_movl_T1_reg(rd);
4680
gen_casx_asi(cpu_val, cpu_addr, cpu_src2, insn, rd);
4681
gen_movl_TN_reg(rd, cpu_val);
3558
4682
break;
3559
4683
#else
3560
4684
case 0x34: /* stc */
3578
4702
gen_op_next_insn();
3579
4703
} else if (dc->npc == JUMP_PC) {
3580
4704
/* we can do a static jump */
3581
gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1]);
4705
gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
3582
4706
dc->is_br = 1;
3583
4707
} else {
3584
4708
dc->pc = dc->npc;
3587
4711
jmp_insn:
3588
4712
return;
3589
4713
illegal_insn:
3590
save_state(dc);
3591
gen_op_exception(TT_ILL_INSN);
3592
dc->is_br = 1;
4714
{
4715
TCGv_i32 r_const;
4716
4717
save_state(dc, cpu_cond);
4718
r_const = tcg_const_i32(TT_ILL_INSN);
4719
gen_helper_raise_exception(r_const);
4720
tcg_temp_free_i32(r_const);
4721
dc->is_br = 1;
4722
}
4723
return;
4724
unimp_flush:
4725
{
4726
TCGv_i32 r_const;
4727
4728
save_state(dc, cpu_cond);
4729
r_const = tcg_const_i32(TT_UNIMP_FLUSH);
4730
gen_helper_raise_exception(r_const);
4731
tcg_temp_free_i32(r_const);
4732
dc->is_br = 1;
4733
}
3593
4734
return;
3594
4735
#if !defined(CONFIG_USER_ONLY)
3595
4736
priv_insn:
3596
save_state(dc);
3597
gen_op_exception(TT_PRIV_INSN);
3598
dc->is_br = 1;
4737
{
4738
TCGv_i32 r_const;
4739
4740
save_state(dc, cpu_cond);
4741
r_const = tcg_const_i32(TT_PRIV_INSN);
4742
gen_helper_raise_exception(r_const);
4743
tcg_temp_free_i32(r_const);
4744
dc->is_br = 1;
4745
}
3599
4746
return;
4747
#endif
3600
4748
nfpu_insn:
3601
save_state(dc);
4749
save_state(dc, cpu_cond);
3602
4750
gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
3603
4751
dc->is_br = 1;
3604
4752
return;
3605
#ifndef TARGET_SPARC64
4753
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
3606
4754
nfq_insn:
3607
save_state(dc);
4755
save_state(dc, cpu_cond);
3608
4756
gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
3609
4757
dc->is_br = 1;
3610
4758
return;
3611
4759
#endif
3612
#endif
3613
4760
#ifndef TARGET_SPARC64
3614
4761
ncp_insn:
3615
save_state(dc);
3616
gen_op_exception(TT_NCP_INSN);
3617
dc->is_br = 1;
4762
{
4763
TCGv r_const;
4764
4765
save_state(dc, cpu_cond);
4766
r_const = tcg_const_i32(TT_NCP_INSN);
4767
gen_helper_raise_exception(r_const);
4768
tcg_temp_free(r_const);
4769
dc->is_br = 1;
4770
}
3618
4771
return;
3619
4772
#endif
3620
4773
}
3621
4774
3622
static inline int gen_intermediate_code_internal(TranslationBlock * tb,
3623
int spc, CPUSPARCState *env)
4775
static inline void gen_intermediate_code_internal(TranslationBlock * tb,
4776
int spc, CPUSPARCState *env)
3624
4777
{
3625
4778
target_ulong pc_start, last_pc;
3626
4779
uint16_t *gen_opc_end;
3627
4780
DisasContext dc1, *dc = &dc1;
4781
CPUBreakpoint *bp;
3628
4782
int j, lj = -1;
4783
int num_insns;
4784
int max_insns;
3629
4785
3630
4786
memset(dc, 0, sizeof(DisasContext));
3631
4787
dc->tb = tb;
3634
4790
last_pc = dc->pc;
3635
4791
dc->npc = (target_ulong) tb->cs_base;
3636
4792
dc->mem_idx = cpu_mmu_index(env);
3637
dc->fpu_enabled = cpu_fpu_enabled(env);
3638
gen_opc_ptr = gen_opc_buf;
4793
dc->def = env->def;
4794
if ((dc->def->features & CPU_FEATURE_FLOAT))
4795
dc->fpu_enabled = cpu_fpu_enabled(env);
4796
else
4797
dc->fpu_enabled = 0;
4798
#ifdef TARGET_SPARC64
4799
dc->address_mask_32bit = env->pstate & PS_AM;
4800
#endif
3639
4801
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3640
gen_opparam_ptr = gen_opparam_buf;
3641
nb_gen_labels = 0;
3642
4802
4803
cpu_tmp0 = tcg_temp_new();
4804
cpu_tmp32 = tcg_temp_new_i32();
4805
cpu_tmp64 = tcg_temp_new_i64();
4806
4807
cpu_dst = tcg_temp_local_new();
4808
4809
// loads and stores
4810
cpu_val = tcg_temp_local_new();
4811
cpu_addr = tcg_temp_local_new();
4812
4813
num_insns = 0;
4814
max_insns = tb->cflags & CF_COUNT_MASK;
4815
if (max_insns == 0)
4816
max_insns = CF_COUNT_MASK;
4817
gen_icount_start();
3643
4818
do {
3644
if (env->nb_breakpoints > 0) {
3645
for(j = 0; j < env->nb_breakpoints; j++) {
3646
if (env->breakpoints[j] == dc->pc) {
4819
if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
4820
TAILQ_FOREACH(bp, &env->breakpoints, entry) {
4821
if (bp->pc == dc->pc) {
3647
4822
if (dc->pc != pc_start)
3648
save_state(dc);
3649
gen_op_debug();
3650
gen_op_movl_T0_0();
3651
gen_op_exit_tb();
4823
save_state(dc, cpu_cond);
4824
gen_helper_debug();
4825
tcg_gen_exit_tb(0);
3652
4826
dc->is_br = 1;
3653
4827
goto exit_gen_loop;
3654
4828
}
3655
4829
}
3656
4830
}
3657
4831
if (spc) {
3658
if (loglevel > 0)
3659
fprintf(logfile, "Search PC...\n");
4832
qemu_log("Search PC...\n");
3660
4833
j = gen_opc_ptr - gen_opc_buf;
3661
4834
if (lj < j) {
3662
4835
lj++;
3665
4838
gen_opc_pc[lj] = dc->pc;
3666
4839
gen_opc_npc[lj] = dc->npc;
3667
4840
gen_opc_instr_start[lj] = 1;
4841
gen_opc_icount[lj] = num_insns;
3668
4842
}
3669
4843
}
4844
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
4845
gen_io_start();
3670
4846
last_pc = dc->pc;
3671
4847
disas_sparc_insn(dc);
4848
num_insns++;
3672
4849
3673
4850
if (dc->is_br)
3674
4851
break;
3682
4859
/* if single step mode, we generate only one instruction and
3683
4860
generate an exception */
3684
4861
if (env->singlestep_enabled) {
3685
gen_jmp_im(dc->pc);
3686
gen_op_movl_T0_0();
3687
gen_op_exit_tb();
4862
tcg_gen_movi_tl(cpu_pc, dc->pc);
4863
tcg_gen_exit_tb(0);
3688
4864
break;
3689
4865
}
3690
4866
} while ((gen_opc_ptr < gen_opc_end) &&
3691
(dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
4867
(dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32) &&
4868
num_insns < max_insns);
3692
4869
3693
4870
exit_gen_loop:
4871
tcg_temp_free(cpu_addr);
4872
tcg_temp_free(cpu_val);
4873
tcg_temp_free(cpu_dst);
4874
tcg_temp_free_i64(cpu_tmp64);
4875
tcg_temp_free_i32(cpu_tmp32);
4876
tcg_temp_free(cpu_tmp0);
4877
if (tb->cflags & CF_LAST_IO)
4878
gen_io_end();
3694
4879
if (!dc->is_br) {
3695
4880
if (dc->pc != DYNAMIC_PC &&
3696
4881
(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
3697
4882
/* static PC and NPC: we can use direct chaining */
3698
gen_branch(dc, dc->pc, dc->npc);
4883
gen_goto_tb(dc, 0, dc->pc, dc->npc);
3699
4884
} else {
3700
4885
if (dc->pc != DYNAMIC_PC)
3701
gen_jmp_im(dc->pc);
3702
save_npc(dc);
3703
gen_op_movl_T0_0();
3704
gen_op_exit_tb();
4886
tcg_gen_movi_tl(cpu_pc, dc->pc);
4887
save_npc(dc, cpu_cond);
4888
tcg_gen_exit_tb(0);
3705
4889
}
3706
4890
}
4891
gen_icount_end(tb, num_insns);
3707
4892
*gen_opc_ptr = INDEX_op_end;
3708
4893
if (spc) {
3709
4894
j = gen_opc_ptr - gen_opc_buf;
3711
4896
while (lj <= j)
3712
4897
gen_opc_instr_start[lj++] = 0;
3713
4898
#if 0
3714
if (loglevel > 0) {
3715
page_dump(logfile);
3716
}
4899
log_page_dump();
3717
4900
#endif
3718
4901
gen_opc_jump_pc[0] = dc->jump_pc[0];
3719
4902
gen_opc_jump_pc[1] = dc->jump_pc[1];
3720
4903
} else {
3721
4904
tb->size = last_pc + 4 - pc_start;
4905
tb->icount = num_insns;
3722
4906
}
3723
4907
#ifdef DEBUG_DISAS
3724
if (loglevel & CPU_LOG_TB_IN_ASM) {
3725
fprintf(logfile, "--------------\n");
3726
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
3727
target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
3728
fprintf(logfile, "\n");
3729
if (loglevel & CPU_LOG_TB_OP) {
3730
fprintf(logfile, "OP:\n");
3731
dump_ops(gen_opc_buf, gen_opparam_buf);
3732
fprintf(logfile, "\n");
3733
}
3734
}
3735
#endif
3736
return 0;
3737
}
3738
3739
int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
3740
{
3741
return gen_intermediate_code_internal(tb, 0, env);
3742
}
3743
3744
int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
3745
{
3746
return gen_intermediate_code_internal(tb, 1, env);
3747
}
3748
3749
extern int ram_size;
3750
3751
void cpu_reset(CPUSPARCState *env)
3752
{
3753
tlb_flush(env, 1);
3754
env->cwp = 0;
3755
env->wim = 1;
3756
env->regwptr = env->regbase + (env->cwp * 16);
3757
#if defined(CONFIG_USER_ONLY)
3758
env->user_mode_only = 1;
3759
#ifdef TARGET_SPARC64
3760
env->cleanwin = NWINDOWS - 2;
3761
env->cansave = NWINDOWS - 2;
3762
env->pstate = PS_RMO | PS_PEF | PS_IE;
3763
env->asi = 0x82; // Primary no-fault
3764
#endif
3765
#else
3766
env->psret = 0;
3767
env->psrs = 1;
3768
env->psrps = 1;
3769
#ifdef TARGET_SPARC64
3770
env->pstate = PS_PRIV;
3771
env->hpstate = HS_PRIV;
3772
env->pc = 0x1fff0000000ULL;
3773
#else
3774
env->pc = 0;
3775
env->mmuregs[0] &= ~(MMU_E | MMU_NF);
3776
env->mmuregs[0] |= env->mmu_bm;
3777
#endif
3778
env->npc = env->pc + 4;
3779
#endif
3780
}
3781
3782
CPUSPARCState *cpu_sparc_init(const char *cpu_model)
3783
{
3784
CPUSPARCState *env;
3785
const sparc_def_t *def;
3786
3787
def = cpu_sparc_find_by_name(cpu_model);
3788
if (!def)
3789
return NULL;
3790
3791
env = qemu_mallocz(sizeof(CPUSPARCState));
3792
if (!env)
3793
return NULL;
3794
cpu_exec_init(env);
3795
env->cpu_model_str = cpu_model;
3796
env->version = def->iu_version;
3797
env->fsr = def->fpu_version;
3798
#if !defined(TARGET_SPARC64)
3799
env->mmu_bm = def->mmu_bm;
3800
env->mmuregs[0] |= def->mmu_version;
3801
cpu_sparc_set_id(env, 0);
3802
#endif
3803
cpu_reset(env);
3804
3805
return env;
3806
}
3807
3808
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
3809
{
3810
#if !defined(TARGET_SPARC64)
3811
env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
3812
#endif
3813
}
3814
3815
static const sparc_def_t sparc_defs[] = {
3816
#ifdef TARGET_SPARC64
3817
{
3818
.name = "Fujitsu Sparc64",
3819
.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)
3820
| (MAXTL << 8) | (NWINDOWS - 1)),
3821
.fpu_version = 0x00000000,
3822
.mmu_version = 0,
3823
},
3824
{
3825
.name = "Fujitsu Sparc64 III",
3826
.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)
3827
| (MAXTL << 8) | (NWINDOWS - 1)),
3828
.fpu_version = 0x00000000,
3829
.mmu_version = 0,
3830
},
3831
{
3832
.name = "Fujitsu Sparc64 IV",
3833
.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)
3834
| (MAXTL << 8) | (NWINDOWS - 1)),
3835
.fpu_version = 0x00000000,
3836
.mmu_version = 0,
3837
},
3838
{
3839
.name = "Fujitsu Sparc64 V",
3840
.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)
3841
| (MAXTL << 8) | (NWINDOWS - 1)),
3842
.fpu_version = 0x00000000,
3843
.mmu_version = 0,
3844
},
3845
{
3846
.name = "TI UltraSparc I",
3847
.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
3848
| (MAXTL << 8) | (NWINDOWS - 1)),
3849
.fpu_version = 0x00000000,
3850
.mmu_version = 0,
3851
},
3852
{
3853
.name = "TI UltraSparc II",
3854
.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)
3855
| (MAXTL << 8) | (NWINDOWS - 1)),
3856
.fpu_version = 0x00000000,
3857
.mmu_version = 0,
3858
},
3859
{
3860
.name = "TI UltraSparc IIi",
3861
.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)
3862
| (MAXTL << 8) | (NWINDOWS - 1)),
3863
.fpu_version = 0x00000000,
3864
.mmu_version = 0,
3865
},
3866
{
3867
.name = "TI UltraSparc IIe",
3868
.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)
3869
| (MAXTL << 8) | (NWINDOWS - 1)),
3870
.fpu_version = 0x00000000,
3871
.mmu_version = 0,
3872
},
3873
{
3874
.name = "Sun UltraSparc III",
3875
.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)
3876
| (MAXTL << 8) | (NWINDOWS - 1)),
3877
.fpu_version = 0x00000000,
3878
.mmu_version = 0,
3879
},
3880
{
3881
.name = "Sun UltraSparc III Cu",
3882
.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)
3883
| (MAXTL << 8) | (NWINDOWS - 1)),
3884
.fpu_version = 0x00000000,
3885
.mmu_version = 0,
3886
},
3887
{
3888
.name = "Sun UltraSparc IIIi",
3889
.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)
3890
| (MAXTL << 8) | (NWINDOWS - 1)),
3891
.fpu_version = 0x00000000,
3892
.mmu_version = 0,
3893
},
3894
{
3895
.name = "Sun UltraSparc IV",
3896
.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)
3897
| (MAXTL << 8) | (NWINDOWS - 1)),
3898
.fpu_version = 0x00000000,
3899
.mmu_version = 0,
3900
},
3901
{
3902
.name = "Sun UltraSparc IV+",
3903
.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)
3904
| (MAXTL << 8) | (NWINDOWS - 1)),
3905
.fpu_version = 0x00000000,
3906
.mmu_version = 0,
3907
},
3908
{
3909
.name = "Sun UltraSparc IIIi+",
3910
.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)
3911
| (MAXTL << 8) | (NWINDOWS - 1)),
3912
.fpu_version = 0x00000000,
3913
.mmu_version = 0,
3914
},
3915
{
3916
.name = "NEC UltraSparc I",
3917
.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)
3918
| (MAXTL << 8) | (NWINDOWS - 1)),
3919
.fpu_version = 0x00000000,
3920
.mmu_version = 0,
3921
},
3922
#else
3923
{
3924
.name = "Fujitsu MB86900",
3925
.iu_version = 0x00 << 24, /* Impl 0, ver 0 */
3926
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3927
.mmu_version = 0x00 << 24, /* Impl 0, ver 0 */
3928
.mmu_bm = 0x00004000,
3929
},
3930
{
3931
.name = "Fujitsu MB86904",
3932
.iu_version = 0x04 << 24, /* Impl 0, ver 4 */
3933
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3934
.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
3935
.mmu_bm = 0x00004000,
3936
},
3937
{
3938
.name = "Fujitsu MB86907",
3939
.iu_version = 0x05 << 24, /* Impl 0, ver 5 */
3940
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
3941
.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
3942
.mmu_bm = 0x00004000,
3943
},
3944
{
3945
.name = "LSI L64811",
3946
.iu_version = 0x10 << 24, /* Impl 1, ver 0 */
3947
.fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */
3948
.mmu_version = 0x10 << 24,
3949
.mmu_bm = 0x00004000,
3950
},
3951
{
3952
.name = "Cypress CY7C601",
3953
.iu_version = 0x11 << 24, /* Impl 1, ver 1 */
3954
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
3955
.mmu_version = 0x10 << 24,
3956
.mmu_bm = 0x00004000,
3957
},
3958
{
3959
.name = "Cypress CY7C611",
3960
.iu_version = 0x13 << 24, /* Impl 1, ver 3 */
3961
.fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */
3962
.mmu_version = 0x10 << 24,
3963
.mmu_bm = 0x00004000,
3964
},
3965
{
3966
.name = "TI SuperSparc II",
3967
.iu_version = 0x40000000,
3968
.fpu_version = 0 << 17,
3969
.mmu_version = 0x04000000,
3970
.mmu_bm = 0x00002000,
3971
},
3972
{
3973
.name = "TI MicroSparc I",
3974
.iu_version = 0x41000000,
3975
.fpu_version = 4 << 17,
3976
.mmu_version = 0x41000000,
3977
.mmu_bm = 0x00004000,
3978
},
3979
{
3980
.name = "TI MicroSparc II",
3981
.iu_version = 0x42000000,
3982
.fpu_version = 4 << 17,
3983
.mmu_version = 0x02000000,
3984
.mmu_bm = 0x00004000,
3985
},
3986
{
3987
.name = "TI MicroSparc IIep",
3988
.iu_version = 0x42000000,
3989
.fpu_version = 4 << 17,
3990
.mmu_version = 0x04000000,
3991
.mmu_bm = 0x00004000,
3992
},
3993
{
3994
.name = "TI SuperSparc 51",
3995
.iu_version = 0x43000000,
3996
.fpu_version = 0 << 17,
3997
.mmu_version = 0x04000000,
3998
.mmu_bm = 0x00002000,
3999
},
4000
{
4001
.name = "TI SuperSparc 61",
4002
.iu_version = 0x44000000,
4003
.fpu_version = 0 << 17,
4004
.mmu_version = 0x04000000,
4005
.mmu_bm = 0x00002000,
4006
},
4007
{
4008
.name = "Ross RT625",
4009
.iu_version = 0x1e000000,
4010
.fpu_version = 1 << 17,
4011
.mmu_version = 0x1e000000,
4012
.mmu_bm = 0x00004000,
4013
},
4014
{
4015
.name = "Ross RT620",
4016
.iu_version = 0x1f000000,
4017
.fpu_version = 1 << 17,
4018
.mmu_version = 0x1f000000,
4019
.mmu_bm = 0x00004000,
4020
},
4021
{
4022
.name = "BIT B5010",
4023
.iu_version = 0x20000000,
4024
.fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */
4025
.mmu_version = 0x20000000,
4026
.mmu_bm = 0x00004000,
4027
},
4028
{
4029
.name = "Matsushita MN10501",
4030
.iu_version = 0x50000000,
4031
.fpu_version = 0 << 17,
4032
.mmu_version = 0x50000000,
4033
.mmu_bm = 0x00004000,
4034
},
4035
{
4036
.name = "Weitek W8601",
4037
.iu_version = 0x90 << 24, /* Impl 9, ver 0 */
4038
.fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */
4039
.mmu_version = 0x10 << 24,
4040
.mmu_bm = 0x00004000,
4041
},
4042
{
4043
.name = "LEON2",
4044
.iu_version = 0xf2000000,
4045
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4046
.mmu_version = 0xf2000000,
4047
.mmu_bm = 0x00004000,
4048
},
4049
{
4050
.name = "LEON3",
4051
.iu_version = 0xf3000000,
4052
.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
4053
.mmu_version = 0xf3000000,
4054
.mmu_bm = 0x00004000,
4055
},
4056
#endif
4057
};
4058
4059
static const sparc_def_t *cpu_sparc_find_by_name(const unsigned char *name)
4060
{
4061
unsigned int i;
4062
4063
for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
4064
if (strcasecmp(name, sparc_defs[i].name) == 0) {
4065
return &sparc_defs[i];
4066
}
4067
}
4068
return NULL;
4069
}
4070
4071
void sparc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
4072
{
4073
unsigned int i;
4074
4075
for (i = 0; i < sizeof(sparc_defs) / sizeof(sparc_def_t); i++) {
4076
(*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x\n",
4077
sparc_defs[i].name,
4078
sparc_defs[i].iu_version,
4079
sparc_defs[i].fpu_version,
4080
sparc_defs[i].mmu_version);
4081
}
4082
}
4083
4084
#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
4085
4086
void cpu_dump_state(CPUState *env, FILE *f,
4087
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
4088
int flags)
4089
{
4090
int i, x;
4091
4092
cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
4093
cpu_fprintf(f, "General Registers:\n");
4094
for (i = 0; i < 4; i++)
4095
cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
4096
cpu_fprintf(f, "\n");
4097
for (; i < 8; i++)
4098
cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
4099
cpu_fprintf(f, "\nCurrent Register Window:\n");
4100
for (x = 0; x < 3; x++) {
4101
for (i = 0; i < 4; i++)
4102
cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
4103
(x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
4104
env->regwptr[i + x * 8]);
4105
cpu_fprintf(f, "\n");
4106
for (; i < 8; i++)
4107
cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
4108
(x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
4109
env->regwptr[i + x * 8]);
4110
cpu_fprintf(f, "\n");
4111
}
4112
cpu_fprintf(f, "\nFloating Point Registers:\n");
4113
for (i = 0; i < 32; i++) {
4114
if ((i & 3) == 0)
4115
cpu_fprintf(f, "%%f%02d:", i);
4116
cpu_fprintf(f, " %016lf", env->fpr[i]);
4117
if ((i & 3) == 3)
4118
cpu_fprintf(f, "\n");
4119
}
4120
#ifdef TARGET_SPARC64
4121
cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
4122
env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs);
4123
cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d cleanwin %d cwp %d\n",
4124
env->cansave, env->canrestore, env->otherwin, env->wstate,
4125
env->cleanwin, NWINDOWS - 1 - env->cwp);
4126
#else
4127
cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
4128
GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
4129
GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
4130
env->psrs?'S':'-', env->psrps?'P':'-',
4131
env->psret?'E':'-', env->wim);
4132
#endif
4133
cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
4134
}
4135
4136
#if defined(CONFIG_USER_ONLY)
4137
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
4138
{
4139
return addr;
4140
}
4141
4142
#else
4143
extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
4144
int *access_index, target_ulong address, int rw,
4145
int mmu_idx);
4146
4147
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
4148
{
4149
target_phys_addr_t phys_addr;
4150
int prot, access_index;
4151
4152
if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
4153
if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 0, 0) != 0)
4154
return -1;
4155
if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
4156
return -1;
4157
return phys_addr;
4158
}
4159
#endif
4160
4161
void helper_flush(target_ulong addr)
4162
{
4163
addr &= ~7;
4164
tb_invalidate_page_range(addr, addr + 8);
4908
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
4909
qemu_log("--------------\n");
4910
qemu_log("IN: %s\n", lookup_symbol(pc_start));
4911
log_target_disas(pc_start, last_pc + 4 - pc_start, 0);
4912
qemu_log("\n");
4913
}
4914
#endif
4915
}
4916
4917
void gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4918
{
4919
gen_intermediate_code_internal(tb, 0, env);
4920
}
4921
4922
void gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4923
{
4924
gen_intermediate_code_internal(tb, 1, env);
4925
}
4926
4927
void gen_intermediate_code_init(CPUSPARCState *env)
4928
{
4929
unsigned int i;
4930
static int inited;
4931
static const char * const gregnames[8] = {
4932
NULL, // g0 not used
4933
"g1",
4934
"g2",
4935
"g3",
4936
"g4",
4937
"g5",
4938
"g6",
4939
"g7",
4940
};
4941
static const char * const fregnames[64] = {
4942
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
4943
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
4944
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
4945
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
4946
"f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
4947
"f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
4948
"f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
4949
"f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
4950
};
4951
4952
/* init various static tables */
4953
if (!inited) {
4954
inited = 1;
4955
4956
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
4957
cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0,
4958
offsetof(CPUState, regwptr),
4959
"regwptr");
4960
#ifdef TARGET_SPARC64
4961
cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, xcc),
4962
"xcc");
4963
cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, asi),
4964
"asi");
4965
cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, fprs),
4966
"fprs");
4967
cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, gsr),
4968
"gsr");
4969
cpu_tick_cmpr = tcg_global_mem_new(TCG_AREG0,
4970
offsetof(CPUState, tick_cmpr),
4971
"tick_cmpr");
4972
cpu_stick_cmpr = tcg_global_mem_new(TCG_AREG0,
4973
offsetof(CPUState, stick_cmpr),
4974
"stick_cmpr");
4975
cpu_hstick_cmpr = tcg_global_mem_new(TCG_AREG0,
4976
offsetof(CPUState, hstick_cmpr),
4977
"hstick_cmpr");
4978
cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hintp),
4979
"hintp");
4980
cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, htba),
4981
"htba");
4982
cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hver),
4983
"hver");
4984
cpu_ssr = tcg_global_mem_new(TCG_AREG0,
4985
offsetof(CPUState, ssr), "ssr");
4986
cpu_ver = tcg_global_mem_new(TCG_AREG0,
4987
offsetof(CPUState, version), "ver");
4988
cpu_softint = tcg_global_mem_new_i32(TCG_AREG0,
4989
offsetof(CPUState, softint),
4990
"softint");
4991
#else
4992
cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, wim),
4993
"wim");
4994
#endif
4995
cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cond),
4996
"cond");
4997
cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src),
4998
"cc_src");
4999
cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0,
5000
offsetof(CPUState, cc_src2),
5001
"cc_src2");
5002
cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst),
5003
"cc_dst");
5004
cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, psr),
5005
"psr");
5006
cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, fsr),
5007
"fsr");
5008
cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, pc),
5009
"pc");
5010
cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, npc),
5011
"npc");
5012
cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, y), "y");
5013
#ifndef CONFIG_USER_ONLY
5014
cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, tbr),
5015
"tbr");
5016
#endif
5017
for (i = 1; i < 8; i++)
5018
cpu_gregs[i] = tcg_global_mem_new(TCG_AREG0,
5019
offsetof(CPUState, gregs[i]),
5020
gregnames[i]);
5021
for (i = 0; i < TARGET_FPREGS; i++)
5022
cpu_fpr[i] = tcg_global_mem_new_i32(TCG_AREG0,
5023
offsetof(CPUState, fpr[i]),
5024
fregnames[i]);
5025
5026
/* register helpers */
5027
5028
#define GEN_HELPER 2
5029
#include "helper.h"
5030
}
5031
}
5032
5033
void gen_pc_load(CPUState *env, TranslationBlock *tb,
5034
unsigned long searched_pc, int pc_pos, void *puc)
5035
{
5036
target_ulong npc;
5037
env->pc = gen_opc_pc[pc_pos];
5038
npc = gen_opc_npc[pc_pos];
5039
if (npc == 1) {
5040
/* dynamic NPC: already stored */
5041
} else if (npc == 2) {
5042
target_ulong t2 = (target_ulong)(unsigned long)puc;
5043
/* jump PC: use T2 and the jump targets of the translation */
5044
if (t2)
5045
env->npc = gen_opc_jump_pc[0];
5046
else
5047
env->npc = gen_opc_jump_pc[1];
5048
} else {
5049
env->npc = npc;
5050
}
4165
5051
}
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Version: 2.0.1