7
SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
7
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
8
9
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
9
qemu_irq irq, CharDriverState *chr,
10
qemu_irq irq, int baudbase,
11
CharDriverState *chr, int ioregister);
11
12
uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
12
13
void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
13
14
uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
42
43
int apic_init(CPUState *env);
43
44
int apic_accept_pic_intr(CPUState *env);
45
void apic_deliver_pic_intr(CPUState *env, int level);
44
46
int apic_get_interrupt(CPUState *env);
45
47
IOAPICState *ioapic_init(void);
46
48
void ioapic_set_irq(void *opaque, int vector, int level);
49
void apic_reset_irq_delivered(void);
50
int apic_get_irq_delivered(void);
58
62
int pit_get_mode(PITState *pit, int channel);
59
63
int pit_get_out(PITState *pit, int channel, int64_t current_time);
65
void hpet_pit_disable(void);
66
void hpet_pit_enable(void);
62
void vmport_init(CPUState *env);
69
void vmport_init(void);
63
70
void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
70
77
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
71
78
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
72
target_phys_addr_t base, int it_shift);
79
target_phys_addr_t base, ram_addr_t size,
80
target_phys_addr_t mask);
74
82
/* mc146818rtc.c */
76
84
typedef struct RTCState RTCState;
78
RTCState *rtc_init(int base, qemu_irq irq);
79
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
86
RTCState *rtc_init(int base, qemu_irq irq, int base_year);
87
RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
80
89
void rtc_set_memory(RTCState *s, int addr, int val);
81
90
void rtc_set_date(RTCState *s, const struct tm *tm);
91
void cmos_set_s3_resume(void);
84
94
extern int fd_bootchk;
90
100
extern int acpi_enabled;
91
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
101
i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
92
103
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
93
104
void acpi_bios_init(void);
105
int acpi_table_add(const char *table_desc);
96
111
void pcspk_init(PITState *);
102
117
int piix3_init(PCIBus *bus, int devfn);
103
118
void i440fx_init_memory_mappings(PCIDevice *d);
120
extern PCIDevice *piix4_dev;
105
121
int piix4_init(PCIBus *bus, int devfn);
124
enum vga_retrace_method {
129
extern enum vga_retrace_method vga_retrace_method;
131
#if !defined(TARGET_SPARC) || defined(TARGET_SPARC64)
110
132
#define VGA_RAM_SIZE (8192 * 1024)
112
134
#define VGA_RAM_SIZE (9 * 1024 * 1024)
115
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
137
int isa_vga_init(uint8_t *vga_ram_base,
116
138
unsigned long vga_ram_offset, int vga_ram_size);
117
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
139
int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
118
140
unsigned long vga_ram_offset, int vga_ram_size,
119
141
unsigned long vga_bios_offset, int vga_bios_size);
120
int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
142
int isa_vga_mm_init(uint8_t *vga_ram_base,
121
143
unsigned long vga_ram_offset, int vga_ram_size,
122
144
target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
125
147
/* cirrus_vga.c */
126
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
127
unsigned long vga_ram_offset, int vga_ram_size);
128
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
129
unsigned long vga_ram_offset, int vga_ram_size);
148
void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
149
ram_addr_t vga_ram_offset, int vga_ram_size);
150
void isa_cirrus_vga_init(uint8_t *vga_ram_base,
151
ram_addr_t vga_ram_offset, int vga_ram_size);
132
154
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,