39
43
spin_unlock(&global_cpu_lock);
44
void do_vfp_abss(void)
46
FT0s = float32_abs(FT0s);
49
void do_vfp_absd(void)
51
FT0d = float64_abs(FT0d);
54
void do_vfp_sqrts(void)
56
FT0s = float32_sqrt(FT0s, &env->vfp.fp_status);
59
void do_vfp_sqrtd(void)
61
FT0d = float64_sqrt(FT0d, &env->vfp.fp_status);
64
/* XXX: check quiet/signaling case */
65
#define DO_VFP_cmp(p, size) \
66
void do_vfp_cmp##p(void) \
69
switch(float ## size ## _compare_quiet(FT0##p, FT1##p, &env->vfp.fp_status)) {\
70
case 0: flags = 0x6; break;\
71
case -1: flags = 0x8; break;\
72
case 1: flags = 0x2; break;\
73
default: case 2: flags = 0x3; break;\
75
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28)\
76
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
80
void do_vfp_cmpe##p(void) \
83
switch(float ## size ## _compare(FT0##p, FT1##p, &env->vfp.fp_status)) {\
84
case 0: flags = 0x6; break;\
85
case -1: flags = 0x8; break;\
86
case 1: flags = 0x2; break;\
87
default: case 2: flags = 0x3; break;\
89
env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28)\
90
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
97
/* Convert host exception flags to vfp form. */
98
static inline int vfp_exceptbits_from_host(int host_bits)
102
if (host_bits & float_flag_invalid)
104
if (host_bits & float_flag_divbyzero)
106
if (host_bits & float_flag_overflow)
108
if (host_bits & float_flag_underflow)
110
if (host_bits & float_flag_inexact)
115
/* Convert vfp exception flags to target form. */
116
static inline int vfp_exceptbits_to_host(int target_bits)
121
host_bits |= float_flag_invalid;
123
host_bits |= float_flag_divbyzero;
125
host_bits |= float_flag_overflow;
127
host_bits |= float_flag_underflow;
128
if (target_bits & 0x10)
129
host_bits |= float_flag_inexact;
133
void do_vfp_set_fpscr(void)
138
changed = env->vfp.xregs[ARM_VFP_FPSCR];
139
env->vfp.xregs[ARM_VFP_FPSCR] = (T0 & 0xffc8ffff);
140
env->vfp.vec_len = (T0 >> 16) & 7;
141
env->vfp.vec_stride = (T0 >> 20) & 3;
144
if (changed & (3 << 22)) {
148
i = float_round_nearest_even;
154
i = float_round_down;
157
i = float_round_to_zero;
160
set_float_rounding_mode(i, &env->vfp.fp_status);
163
i = vfp_exceptbits_to_host((T0 >> 8) & 0x1f);
164
set_float_exception_flags(i, &env->vfp.fp_status);
165
/* XXX: FZ and DN are not implemented. */
168
void do_vfp_get_fpscr(void)
172
T0 = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) | (env->vfp.vec_len << 16)
173
| (env->vfp.vec_stride << 20);
174
i = get_float_exception_flags(&env->vfp.fp_status);
175
T0 |= vfp_exceptbits_from_host(i);
178
float32 helper_recps_f32(float32 a, float32 b)
180
float_status *s = &env->vfp.fp_status;
181
float32 two = int32_to_float32(2, s);
182
return float32_sub(two, float32_mul(a, b, s), s);
185
float32 helper_rsqrts_f32(float32 a, float32 b)
187
float_status *s = &env->vfp.fp_status;
188
float32 three = int32_to_float32(3, s);
189
return float32_sub(three, float32_mul(a, b, s), s);
192
/* TODO: The architecture specifies the value that the estimate functions
193
should return. We return the exact reciprocal/root instead. */
194
float32 helper_recpe_f32(float32 a)
196
float_status *s = &env->vfp.fp_status;
197
float32 one = int32_to_float32(1, s);
198
return float32_div(one, a, s);
201
float32 helper_rsqrte_f32(float32 a)
203
float_status *s = &env->vfp.fp_status;
204
float32 one = int32_to_float32(1, s);
205
return float32_div(one, float32_sqrt(a, s), s);
208
uint32_t helper_recpe_u32(uint32_t a)
210
float_status *s = &env->vfp.fp_status;
212
tmp = int32_to_float32(a, s);
213
tmp = float32_scalbn(tmp, -32, s);
214
tmp = helper_recpe_f32(tmp);
215
tmp = float32_scalbn(tmp, 31, s);
216
return float32_to_int32(tmp, s);
219
uint32_t helper_rsqrte_u32(uint32_t a)
221
float_status *s = &env->vfp.fp_status;
223
tmp = int32_to_float32(a, s);
224
tmp = float32_scalbn(tmp, -32, s);
225
tmp = helper_rsqrte_f32(tmp);
226
tmp = float32_scalbn(tmp, 31, s);
227
return float32_to_int32(tmp, s);
230
void helper_neon_tbl(int rn, int maxindex)
46
uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def,
47
uint32_t rn, uint32_t maxindex)
238
54
table = (uint64_t *)&env->vfp.regs[rn];
241
56
for (shift = 0; shift < 32; shift += 8) {
242
index = (T1 >> shift) & 0xff;
243
if (index <= maxindex) {
244
tmp = (table[index >> 3] >> (index & 7)) & 0xff;
57
index = (ireg >> shift) & 0xff;
58
if (index < maxindex) {
59
tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
245
60
val |= tmp << shift;
247
val |= T0 & (0xff << shift);
62
val |= def & (0xff << shift);
253
68
#if !defined(CONFIG_USER_ONLY)
255
70
#define MMUSUFFIX _mmu
257
# define GETPC() ((void*)((unsigned long)__builtin_return_address(0) & 0x7fffffffUL))
259
# define GETPC() (__builtin_return_address(0))
263
73
#include "softmmu_template.h"
117
/* FIXME: Pass an axplicit pointer to QF to CPUState, and move saturating
118
instructions into helper.c */
119
uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)
121
uint32_t res = a + b;
122
if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
127
uint32_t HELPER(add_saturate)(uint32_t a, uint32_t b)
129
uint32_t res = a + b;
130
if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
132
res = ~(((int32_t)a >> 31) ^ SIGNBIT);
137
uint32_t HELPER(sub_saturate)(uint32_t a, uint32_t b)
139
uint32_t res = a - b;
140
if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
142
res = ~(((int32_t)a >> 31) ^ SIGNBIT);
147
uint32_t HELPER(double_saturate)(int32_t val)
150
if (val >= 0x40000000) {
153
} else if (val <= (int32_t)0xc0000000) {
162
uint32_t HELPER(add_usaturate)(uint32_t a, uint32_t b)
164
uint32_t res = a + b;
172
uint32_t HELPER(sub_usaturate)(uint32_t a, uint32_t b)
174
uint32_t res = a - b;
182
/* Signed saturation. */
183
static inline uint32_t do_ssat(int32_t val, int shift)
189
mask = (1u << shift) - 1;
193
} else if (top < -1) {
200
/* Unsigned saturation. */
201
static inline uint32_t do_usat(int32_t val, int shift)
205
max = (1u << shift) - 1;
209
} else if (val > max) {
216
/* Signed saturate. */
217
uint32_t HELPER(ssat)(uint32_t x, uint32_t shift)
219
return do_ssat(x, shift);
222
/* Dual halfword signed saturate. */
223
uint32_t HELPER(ssat16)(uint32_t x, uint32_t shift)
227
res = (uint16_t)do_ssat((int16_t)x, shift);
228
res |= do_ssat(((int32_t)x) >> 16, shift) << 16;
232
/* Unsigned saturate. */
233
uint32_t HELPER(usat)(uint32_t x, uint32_t shift)
235
return do_usat(x, shift);
238
/* Dual halfword unsigned saturate. */
239
uint32_t HELPER(usat16)(uint32_t x, uint32_t shift)
243
res = (uint16_t)do_usat((int16_t)x, shift);
244
res |= do_usat(((int32_t)x) >> 16, shift) << 16;
248
void HELPER(wfi)(void)
250
env->exception_index = EXCP_HLT;
255
void HELPER(exception)(uint32_t excp)
257
env->exception_index = excp;
261
uint32_t HELPER(cpsr_read)(void)
263
return cpsr_read(env) & ~CPSR_EXEC;
266
void HELPER(cpsr_write)(uint32_t val, uint32_t mask)
268
cpsr_write(env, val, mask);
271
/* Access to user mode registers from privileged modes. */
272
uint32_t HELPER(get_user_reg)(uint32_t regno)
277
val = env->banked_r13[0];
278
} else if (regno == 14) {
279
val = env->banked_r14[0];
280
} else if (regno >= 8
281
&& (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
282
val = env->usr_regs[regno - 8];
284
val = env->regs[regno];
289
void HELPER(set_user_reg)(uint32_t regno, uint32_t val)
292
env->banked_r13[0] = val;
293
} else if (regno == 14) {
294
env->banked_r14[0] = val;
295
} else if (regno >= 8
296
&& (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
297
env->usr_regs[regno - 8] = val;
299
env->regs[regno] = val;
303
/* ??? Flag setting arithmetic is awkward because we need to do comparisons.
304
The only way to do that in TCG is a conditional branch, which clobbers
305
all our temporaries. For now implement these as helper functions. */
307
uint32_t HELPER (add_cc)(uint32_t a, uint32_t b)
311
env->NF = env->ZF = result;
312
env->CF = result < a;
313
env->VF = (a ^ b ^ -1) & (a ^ result);
317
uint32_t HELPER(adc_cc)(uint32_t a, uint32_t b)
322
env->CF = result < a;
325
env->CF = result <= a;
327
env->VF = (a ^ b ^ -1) & (a ^ result);
328
env->NF = env->ZF = result;
332
uint32_t HELPER(sub_cc)(uint32_t a, uint32_t b)
336
env->NF = env->ZF = result;
338
env->VF = (a ^ b) & (a ^ result);
342
uint32_t HELPER(sbc_cc)(uint32_t a, uint32_t b)
352
env->VF = (a ^ b) & (a ^ result);
353
env->NF = env->ZF = result;
357
/* Similarly for variable shift instructions. */
359
uint32_t HELPER(shl)(uint32_t x, uint32_t i)
361
int shift = i & 0xff;
367
uint32_t HELPER(shr)(uint32_t x, uint32_t i)
369
int shift = i & 0xff;
372
return (uint32_t)x >> shift;
375
uint32_t HELPER(sar)(uint32_t x, uint32_t i)
377
int shift = i & 0xff;
380
return (int32_t)x >> shift;
383
uint32_t HELPER(ror)(uint32_t x, uint32_t i)
385
int shift = i & 0xff;
388
return (x >> shift) | (x << (32 - shift));
391
uint32_t HELPER(shl_cc)(uint32_t x, uint32_t i)
393
int shift = i & 0xff;
400
} else if (shift != 0) {
401
env->CF = (x >> (32 - shift)) & 1;
407
uint32_t HELPER(shr_cc)(uint32_t x, uint32_t i)
409
int shift = i & 0xff;
412
env->CF = (x >> 31) & 1;
416
} else if (shift != 0) {
417
env->CF = (x >> (shift - 1)) & 1;
423
uint32_t HELPER(sar_cc)(uint32_t x, uint32_t i)
425
int shift = i & 0xff;
427
env->CF = (x >> 31) & 1;
428
return (int32_t)x >> 31;
429
} else if (shift != 0) {
430
env->CF = (x >> (shift - 1)) & 1;
431
return (int32_t)x >> shift;
436
uint32_t HELPER(ror_cc)(uint32_t x, uint32_t i)
440
shift = shift1 & 0x1f;
443
env->CF = (x >> 31) & 1;
446
env->CF = (x >> (shift - 1)) & 1;
447
return ((uint32_t)x >> shift) | (x << (32 - shift));
451
uint64_t HELPER(neon_add_saturate_s64)(uint64_t src1, uint64_t src2)
456
if (((res ^ src1) & SIGNBIT64) && !((src1 ^ src2) & SIGNBIT64)) {
458
res = ((int64_t)src1 >> 63) ^ ~SIGNBIT64;
463
uint64_t HELPER(neon_add_saturate_u64)(uint64_t src1, uint64_t src2)
475
uint64_t HELPER(neon_sub_saturate_s64)(uint64_t src1, uint64_t src2)
480
if (((res ^ src1) & SIGNBIT64) && ((src1 ^ src2) & SIGNBIT64)) {
482
res = ((int64_t)src1 >> 63) ^ ~SIGNBIT64;
487
uint64_t HELPER(neon_sub_saturate_u64)(uint64_t src1, uint64_t src2)
500
/* These need to return a pair of value, so still use T0/T1. */
501
/* Transpose. Argument order is rather strange to avoid special casing
503
On input T0 = rm, T1 = rd. On output T0 = rd, T1 = rm */
504
void HELPER(neon_trn_u8)(void)
508
rd = ((T0 & 0x00ff00ff) << 8) | (T1 & 0x00ff00ff);
509
rm = ((T1 & 0xff00ff00) >> 8) | (T0 & 0xff00ff00);
514
void HELPER(neon_trn_u16)(void)
518
rd = (T0 << 16) | (T1 & 0xffff);
519
rm = (T1 >> 16) | (T0 & 0xffff0000);
524
/* Worker routines for zip and unzip. */
525
void HELPER(neon_unzip_u8)(void)
529
rd = (T0 & 0xff) | ((T0 >> 8) & 0xff00)
530
| ((T1 << 16) & 0xff0000) | ((T1 << 8) & 0xff000000);
531
rm = ((T0 >> 8) & 0xff) | ((T0 >> 16) & 0xff00)
532
| ((T1 << 8) & 0xff0000) | (T1 & 0xff000000);
537
void HELPER(neon_zip_u8)(void)
541
rd = (T0 & 0xff) | ((T1 << 8) & 0xff00)
542
| ((T0 << 16) & 0xff0000) | ((T1 << 24) & 0xff000000);
543
rm = ((T0 >> 16) & 0xff) | ((T1 >> 8) & 0xff00)
544
| ((T0 >> 8) & 0xff0000) | (T1 & 0xff000000);
549
void HELPER(neon_zip_u16)(void)
553
tmp = (T0 & 0xffff) | (T1 << 16);
554
T1 = (T1 & 0xffff0000) | (T0 >> 16);