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* Tiny Code Generator for QEMU
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* Copyright (c) 2008 Andrzej Zaborowski
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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static const int tcg_target_reg_alloc_order[] = {
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static const int tcg_target_call_iarg_regs[4] = {
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TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
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static const int tcg_target_call_oarg_regs[2] = {
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TCG_REG_R0, TCG_REG_R1
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static void patch_reloc(uint8_t *code_ptr, int type,
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tcg_target_long value, tcg_target_long addend)
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*(uint32_t *) code_ptr = value;
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*(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & 0xff000000) |
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(((value - ((tcg_target_long) code_ptr + 8)) >> 2) & 0xffffff);
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/* maximum number of register used for input function arguments */
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static inline int tcg_target_get_call_iarg_regs_count(int flags)
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/* parse target specific constraints */
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static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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#ifndef CONFIG_SOFTMMU
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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#ifdef CONFIG_SOFTMMU
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/* qemu_ld/st inputs (unless 'X', 'd' or 'D') */
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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/* qemu_ld64 data_reg */
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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/* r1 is still needed to load data_reg2, so don't use it. */
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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/* qemu_ld/st64 data_reg2 */
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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/* r0, r1 and optionally r2 will be overwritten by the address
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* and the low word of data, so don't use these. */
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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# if TARGET_LONG_BITS == 64
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
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# if TARGET_LONG_BITS == 64
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/* qemu_ld/st addr_reg2 */
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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/* r0 will be overwritten by the low word of base, so don't use it. */
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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/* Test if a constant matches the constraint.
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* TODO: define constraints for:
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* ldr/str offset: between -0xfff and 0xfff
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* ldrh/strh offset: between -0xff and 0xff
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* mov operand2: values represented with x << (2 * y), x < 0x100
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* add, sub, eor...: ditto
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static inline int tcg_target_const_match(tcg_target_long val,
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const TCGArgConstraint *arg_ct)
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if (ct & TCG_CT_CONST)
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enum arm_data_opc_e {
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#define TO_CPSR(opc) \
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((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
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#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
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#define SHIFT_IMM_LSR(im) (((im) << 7) | 0x20)
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#define SHIFT_IMM_ASR(im) (((im) << 7) | 0x40)
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#define SHIFT_IMM_ROR(im) (((im) << 7) | 0x60)
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#define SHIFT_REG_LSL(rs) (((rs) << 8) | 0x10)
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#define SHIFT_REG_LSR(rs) (((rs) << 8) | 0x30)
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#define SHIFT_REG_ASR(rs) (((rs) << 8) | 0x50)
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#define SHIFT_REG_ROR(rs) (((rs) << 8) | 0x70)
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enum arm_cond_code_e {
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COND_CS = 0x2, /* Unsigned greater or equal */
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COND_CC = 0x3, /* Unsigned less than */
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COND_MI = 0x4, /* Negative */
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COND_PL = 0x5, /* Zero or greater */
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COND_VS = 0x6, /* Overflow */
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COND_VC = 0x7, /* No overflow */
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COND_HI = 0x8, /* Unsigned greater than */
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COND_LS = 0x9, /* Unsigned less or equal */
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static const uint8_t tcg_cond_to_arm_cond[10] = {
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[TCG_COND_EQ] = COND_EQ,
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[TCG_COND_NE] = COND_NE,
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[TCG_COND_LT] = COND_LT,
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[TCG_COND_GE] = COND_GE,
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[TCG_COND_LE] = COND_LE,
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[TCG_COND_GT] = COND_GT,
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[TCG_COND_LTU] = COND_CC,
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[TCG_COND_GEU] = COND_CS,
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[TCG_COND_LEU] = COND_LS,
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[TCG_COND_GTU] = COND_HI,
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static inline void tcg_out_bx(TCGContext *s, int cond, int rn)
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tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
264
static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
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tcg_out32(s, (cond << 28) | 0x0a000000 |
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(((offset - 8) >> 2) & 0x00ffffff));
270
static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
272
#ifdef WORDS_BIGENDIAN
273
tcg_out8(s, (cond << 4) | 0x0a);
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tcg_out8(s, (cond << 4) | 0x0a);
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static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
283
tcg_out32(s, (cond << 28) | 0x0b000000 |
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(((offset - 8) >> 2) & 0x00ffffff));
287
static inline void tcg_out_dat_reg(TCGContext *s,
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int cond, int opc, int rd, int rn, int rm, int shift)
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tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
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(rn << 16) | (rd << 12) | shift | rm);
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static inline void tcg_out_dat_reg2(TCGContext *s,
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int cond, int opc0, int opc1, int rd0, int rd1,
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int rn0, int rn1, int rm0, int rm1, int shift)
298
if (rd0 == rn1 || rd0 == rm1) {
299
tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
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(rn0 << 16) | (8 << 12) | shift | rm0);
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tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
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(rn1 << 16) | (rd1 << 12) | shift | rm1);
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tcg_out_dat_reg(s, cond, ARITH_MOV,
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rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
306
tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
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(rn0 << 16) | (rd0 << 12) | shift | rm0);
308
tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
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(rn1 << 16) | (rd1 << 12) | shift | rm1);
313
static inline void tcg_out_dat_imm(TCGContext *s,
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int cond, int opc, int rd, int rn, int im)
316
tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
317
(rn << 16) | (rd << 12) | im);
320
static inline void tcg_out_movi32(TCGContext *s,
321
int cond, int rd, int32_t arg)
323
int offset = (uint32_t) arg - ((uint32_t) s->code_ptr + 8);
325
/* TODO: This is very suboptimal, we can easily have a constant
326
* pool somewhere after all the instructions. */
328
if (arg < 0 && arg > -0x100)
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return tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);
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if (offset < 0x100 && offset > -0x100)
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tcg_out_dat_imm(s, cond, ARITH_ADD, rd, 15, offset) :
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tcg_out_dat_imm(s, cond, ARITH_SUB, rd, 15, -offset);
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tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, arg & 0xff);
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if (arg & 0x0000ff00)
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tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
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((arg >> 8) & 0xff) | 0xc00);
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if (arg & 0x00ff0000)
341
tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
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((arg >> 16) & 0xff) | 0x800);
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if (arg & 0xff000000)
344
tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
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((arg >> 24) & 0xff) | 0x400);
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static inline void tcg_out_mul32(TCGContext *s,
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int cond, int rd, int rs, int rm)
352
tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
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(rs << 8) | 0x90 | rm);
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tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
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(rm << 8) | 0x90 | rs);
358
tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |
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(rs << 8) | 0x90 | rm);
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tcg_out_dat_reg(s, cond, ARITH_MOV,
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rd, 0, 8, SHIFT_IMM_LSL(0));
365
static inline void tcg_out_umull32(TCGContext *s,
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int cond, int rd0, int rd1, int rs, int rm)
368
if (rd0 != rm && rd1 != rm)
369
tcg_out32(s, (cond << 28) | 0x800090 |
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(rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
371
else if (rd0 != rs && rd1 != rs)
372
tcg_out32(s, (cond << 28) | 0x800090 |
373
(rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
375
tcg_out_dat_reg(s, cond, ARITH_MOV,
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TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
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tcg_out32(s, (cond << 28) | 0x800098 |
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(rd1 << 16) | (rd0 << 12) | (rs << 8));
382
static inline void tcg_out_smull32(TCGContext *s,
383
int cond, int rd0, int rd1, int rs, int rm)
385
if (rd0 != rm && rd1 != rm)
386
tcg_out32(s, (cond << 28) | 0xc00090 |
387
(rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
388
else if (rd0 != rs && rd1 != rs)
389
tcg_out32(s, (cond << 28) | 0xc00090 |
390
(rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
392
tcg_out_dat_reg(s, cond, ARITH_MOV,
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TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
394
tcg_out32(s, (cond << 28) | 0xc00098 |
395
(rd1 << 16) | (rd0 << 12) | (rs << 8));
399
static inline void tcg_out_ld32_12(TCGContext *s, int cond,
400
int rd, int rn, tcg_target_long im)
403
tcg_out32(s, (cond << 28) | 0x05900000 |
404
(rn << 16) | (rd << 12) | (im & 0xfff));
406
tcg_out32(s, (cond << 28) | 0x05100000 |
407
(rn << 16) | (rd << 12) | ((-im) & 0xfff));
410
static inline void tcg_out_st32_12(TCGContext *s, int cond,
411
int rd, int rn, tcg_target_long im)
414
tcg_out32(s, (cond << 28) | 0x05800000 |
415
(rn << 16) | (rd << 12) | (im & 0xfff));
417
tcg_out32(s, (cond << 28) | 0x05000000 |
418
(rn << 16) | (rd << 12) | ((-im) & 0xfff));
421
static inline void tcg_out_ld32_r(TCGContext *s, int cond,
422
int rd, int rn, int rm)
424
tcg_out32(s, (cond << 28) | 0x07900000 |
425
(rn << 16) | (rd << 12) | rm);
428
static inline void tcg_out_st32_r(TCGContext *s, int cond,
429
int rd, int rn, int rm)
431
tcg_out32(s, (cond << 28) | 0x07800000 |
432
(rn << 16) | (rd << 12) | rm);
435
/* Register pre-increment with base writeback. */
436
static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,
437
int rd, int rn, int rm)
439
tcg_out32(s, (cond << 28) | 0x07b00000 |
440
(rn << 16) | (rd << 12) | rm);
443
static inline void tcg_out_st32_rwb(TCGContext *s, int cond,
444
int rd, int rn, int rm)
446
tcg_out32(s, (cond << 28) | 0x07a00000 |
447
(rn << 16) | (rd << 12) | rm);
450
static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
451
int rd, int rn, tcg_target_long im)
454
tcg_out32(s, (cond << 28) | 0x01d000b0 |
455
(rn << 16) | (rd << 12) |
456
((im & 0xf0) << 4) | (im & 0xf));
458
tcg_out32(s, (cond << 28) | 0x015000b0 |
459
(rn << 16) | (rd << 12) |
460
(((-im) & 0xf0) << 4) | ((-im) & 0xf));
463
static inline void tcg_out_st16u_8(TCGContext *s, int cond,
464
int rd, int rn, tcg_target_long im)
467
tcg_out32(s, (cond << 28) | 0x01c000b0 |
468
(rn << 16) | (rd << 12) |
469
((im & 0xf0) << 4) | (im & 0xf));
471
tcg_out32(s, (cond << 28) | 0x014000b0 |
472
(rn << 16) | (rd << 12) |
473
(((-im) & 0xf0) << 4) | ((-im) & 0xf));
476
static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
477
int rd, int rn, int rm)
479
tcg_out32(s, (cond << 28) | 0x019000b0 |
480
(rn << 16) | (rd << 12) | rm);
483
static inline void tcg_out_st16u_r(TCGContext *s, int cond,
484
int rd, int rn, int rm)
486
tcg_out32(s, (cond << 28) | 0x018000b0 |
487
(rn << 16) | (rd << 12) | rm);
490
static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
491
int rd, int rn, tcg_target_long im)
494
tcg_out32(s, (cond << 28) | 0x01d000f0 |
495
(rn << 16) | (rd << 12) |
496
((im & 0xf0) << 4) | (im & 0xf));
498
tcg_out32(s, (cond << 28) | 0x015000f0 |
499
(rn << 16) | (rd << 12) |
500
(((-im) & 0xf0) << 4) | ((-im) & 0xf));
503
static inline void tcg_out_st16s_8(TCGContext *s, int cond,
504
int rd, int rn, tcg_target_long im)
507
tcg_out32(s, (cond << 28) | 0x01c000f0 |
508
(rn << 16) | (rd << 12) |
509
((im & 0xf0) << 4) | (im & 0xf));
511
tcg_out32(s, (cond << 28) | 0x014000f0 |
512
(rn << 16) | (rd << 12) |
513
(((-im) & 0xf0) << 4) | ((-im) & 0xf));
516
static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
517
int rd, int rn, int rm)
519
tcg_out32(s, (cond << 28) | 0x019000f0 |
520
(rn << 16) | (rd << 12) | rm);
523
static inline void tcg_out_st16s_r(TCGContext *s, int cond,
524
int rd, int rn, int rm)
526
tcg_out32(s, (cond << 28) | 0x018000f0 |
527
(rn << 16) | (rd << 12) | rm);
530
static inline void tcg_out_ld8_12(TCGContext *s, int cond,
531
int rd, int rn, tcg_target_long im)
534
tcg_out32(s, (cond << 28) | 0x05d00000 |
535
(rn << 16) | (rd << 12) | (im & 0xfff));
537
tcg_out32(s, (cond << 28) | 0x05500000 |
538
(rn << 16) | (rd << 12) | ((-im) & 0xfff));
541
static inline void tcg_out_st8_12(TCGContext *s, int cond,
542
int rd, int rn, tcg_target_long im)
545
tcg_out32(s, (cond << 28) | 0x05c00000 |
546
(rn << 16) | (rd << 12) | (im & 0xfff));
548
tcg_out32(s, (cond << 28) | 0x05400000 |
549
(rn << 16) | (rd << 12) | ((-im) & 0xfff));
552
static inline void tcg_out_ld8_r(TCGContext *s, int cond,
553
int rd, int rn, int rm)
555
tcg_out32(s, (cond << 28) | 0x07d00000 |
556
(rn << 16) | (rd << 12) | rm);
559
static inline void tcg_out_st8_r(TCGContext *s, int cond,
560
int rd, int rn, int rm)
562
tcg_out32(s, (cond << 28) | 0x07c00000 |
563
(rn << 16) | (rd << 12) | rm);
566
static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
567
int rd, int rn, tcg_target_long im)
570
tcg_out32(s, (cond << 28) | 0x01d000d0 |
571
(rn << 16) | (rd << 12) |
572
((im & 0xf0) << 4) | (im & 0xf));
574
tcg_out32(s, (cond << 28) | 0x015000d0 |
575
(rn << 16) | (rd << 12) |
576
(((-im) & 0xf0) << 4) | ((-im) & 0xf));
579
static inline void tcg_out_st8s_8(TCGContext *s, int cond,
580
int rd, int rn, tcg_target_long im)
583
tcg_out32(s, (cond << 28) | 0x01c000d0 |
584
(rn << 16) | (rd << 12) |
585
((im & 0xf0) << 4) | (im & 0xf));
587
tcg_out32(s, (cond << 28) | 0x014000d0 |
588
(rn << 16) | (rd << 12) |
589
(((-im) & 0xf0) << 4) | ((-im) & 0xf));
592
static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
593
int rd, int rn, int rm)
595
tcg_out32(s, (cond << 28) | 0x019000d0 |
596
(rn << 16) | (rd << 12) | rm);
599
static inline void tcg_out_st8s_r(TCGContext *s, int cond,
600
int rd, int rn, int rm)
602
tcg_out32(s, (cond << 28) | 0x018000d0 |
603
(rn << 16) | (rd << 12) | rm);
606
static inline void tcg_out_ld32u(TCGContext *s, int cond,
607
int rd, int rn, int32_t offset)
609
if (offset > 0xfff || offset < -0xfff) {
610
tcg_out_movi32(s, cond, TCG_REG_R8, offset);
611
tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8);
613
tcg_out_ld32_12(s, cond, rd, rn, offset);
616
static inline void tcg_out_st32(TCGContext *s, int cond,
617
int rd, int rn, int32_t offset)
619
if (offset > 0xfff || offset < -0xfff) {
620
tcg_out_movi32(s, cond, TCG_REG_R8, offset);
621
tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8);
623
tcg_out_st32_12(s, cond, rd, rn, offset);
626
static inline void tcg_out_ld16u(TCGContext *s, int cond,
627
int rd, int rn, int32_t offset)
629
if (offset > 0xff || offset < -0xff) {
630
tcg_out_movi32(s, cond, TCG_REG_R8, offset);
631
tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8);
633
tcg_out_ld16u_8(s, cond, rd, rn, offset);
636
static inline void tcg_out_ld16s(TCGContext *s, int cond,
637
int rd, int rn, int32_t offset)
639
if (offset > 0xff || offset < -0xff) {
640
tcg_out_movi32(s, cond, TCG_REG_R8, offset);
641
tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8);
643
tcg_out_ld16s_8(s, cond, rd, rn, offset);
646
static inline void tcg_out_st16u(TCGContext *s, int cond,
647
int rd, int rn, int32_t offset)
649
if (offset > 0xff || offset < -0xff) {
650
tcg_out_movi32(s, cond, TCG_REG_R8, offset);
651
tcg_out_st16u_r(s, cond, rd, rn, TCG_REG_R8);
653
tcg_out_st16u_8(s, cond, rd, rn, offset);
656
static inline void tcg_out_ld8u(TCGContext *s, int cond,
657
int rd, int rn, int32_t offset)
659
if (offset > 0xfff || offset < -0xfff) {
660
tcg_out_movi32(s, cond, TCG_REG_R8, offset);
661
tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8);
663
tcg_out_ld8_12(s, cond, rd, rn, offset);
666
static inline void tcg_out_ld8s(TCGContext *s, int cond,
667
int rd, int rn, int32_t offset)
669
if (offset > 0xff || offset < -0xff) {
670
tcg_out_movi32(s, cond, TCG_REG_R8, offset);
671
tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8);
673
tcg_out_ld8s_8(s, cond, rd, rn, offset);
676
static inline void tcg_out_st8u(TCGContext *s, int cond,
677
int rd, int rn, int32_t offset)
679
if (offset > 0xfff || offset < -0xfff) {
680
tcg_out_movi32(s, cond, TCG_REG_R8, offset);
681
tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8);
683
tcg_out_st8_12(s, cond, rd, rn, offset);
686
static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
690
val = addr - (tcg_target_long) s->code_ptr;
691
if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
692
tcg_out_b(s, cond, val);
697
if (cond == COND_AL) {
698
tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
699
tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
701
tcg_out_movi32(s, cond, TCG_REG_R8, val - 8);
702
tcg_out_dat_reg(s, cond, ARITH_ADD,
703
15, 15, TCG_REG_R8, SHIFT_IMM_LSL(0));
709
static inline void tcg_out_call(TCGContext *s, int cond, uint32_t addr)
714
tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R8, 0, 14, SHIFT_IMM_LSL(0));
717
val = addr - (tcg_target_long) s->code_ptr;
718
if (val < 0x01fffffd && val > -0x01fffffd)
719
tcg_out_bl(s, cond, val);
724
if (cond == COND_AL) {
725
tcg_out_dat_imm(s, cond, ARITH_ADD, 14, 15, 4);
726
tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
727
tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
729
tcg_out_movi32(s, cond, TCG_REG_R9, addr);
730
tcg_out_dat_imm(s, cond, ARITH_MOV, 14, 0, 15);
731
tcg_out_bx(s, cond, TCG_REG_R9);
737
tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
741
static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
744
tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R8, 0, 14, SHIFT_IMM_LSL(0));
746
/* TODO: on ARMv5 and ARMv6 replace with tcg_out_blx(s, cond, arg); */
747
tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 15, SHIFT_IMM_LSL(0));
748
tcg_out_bx(s, cond, arg);
750
tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
754
static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
756
TCGLabel *l = &s->labels[label_index];
759
tcg_out_goto(s, cond, l->u.value);
760
else if (cond == COND_AL) {
761
tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
762
tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337);
765
/* Probably this should be preferred even for COND_AL... */
766
tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337);
767
tcg_out_b_noaddr(s, cond);
771
static void tcg_out_div_helper(TCGContext *s, int cond, const TCGArg *args,
772
void *helper_div, void *helper_rem, int shift)
774
int div_reg = args[0];
775
int rem_reg = args[1];
777
/* stmdb sp!, { r0 - r3, ip, lr } */
778
/* (Note that we need an even number of registers as per EABI) */
779
tcg_out32(s, (cond << 28) | 0x092d500f);
781
tcg_out_dat_reg(s, cond, ARITH_MOV, 0, 0, args[2], SHIFT_IMM_LSL(0));
782
tcg_out_dat_reg(s, cond, ARITH_MOV, 1, 0, args[3], SHIFT_IMM_LSL(0));
783
tcg_out_dat_reg(s, cond, ARITH_MOV, 2, 0, args[4], SHIFT_IMM_LSL(0));
784
tcg_out_dat_reg(s, cond, ARITH_MOV, 3, 0, 2, shift);
786
tcg_out_call(s, cond, (uint32_t) helper_div);
787
tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 0, SHIFT_IMM_LSL(0));
789
/* ldmia sp, { r0 - r3, fp, lr } */
790
tcg_out32(s, (cond << 28) | 0x089d500f);
792
tcg_out_dat_reg(s, cond, ARITH_MOV, 0, 0, args[2], SHIFT_IMM_LSL(0));
793
tcg_out_dat_reg(s, cond, ARITH_MOV, 1, 0, args[3], SHIFT_IMM_LSL(0));
794
tcg_out_dat_reg(s, cond, ARITH_MOV, 2, 0, args[4], SHIFT_IMM_LSL(0));
795
tcg_out_dat_reg(s, cond, ARITH_MOV, 3, 0, 2, shift);
797
tcg_out_call(s, cond, (uint32_t) helper_rem);
799
tcg_out_dat_reg(s, cond, ARITH_MOV, rem_reg, 0, 0, SHIFT_IMM_LSL(0));
800
tcg_out_dat_reg(s, cond, ARITH_MOV, div_reg, 0, 8, SHIFT_IMM_LSL(0));
802
/* ldr r0, [sp], #4 */
803
if (rem_reg != 0 && div_reg != 0)
804
tcg_out32(s, (cond << 28) | 0x04bd0004);
805
/* ldr r1, [sp], #4 */
806
if (rem_reg != 1 && div_reg != 1)
807
tcg_out32(s, (cond << 28) | 0x04bd1004);
808
/* ldr r2, [sp], #4 */
809
if (rem_reg != 2 && div_reg != 2)
810
tcg_out32(s, (cond << 28) | 0x04bd2004);
811
/* ldr r3, [sp], #4 */
812
if (rem_reg != 3 && div_reg != 3)
813
tcg_out32(s, (cond << 28) | 0x04bd3004);
814
/* ldr ip, [sp], #4 */
815
if (rem_reg != 12 && div_reg != 12)
816
tcg_out32(s, (cond << 28) | 0x04bdc004);
817
/* ldr lr, [sp], #4 */
818
if (rem_reg != 14 && div_reg != 14)
819
tcg_out32(s, (cond << 28) | 0x04bde004);
822
#ifdef CONFIG_SOFTMMU
824
#include "../../softmmu_defs.h"
826
static void *qemu_ld_helpers[4] = {
833
static void *qemu_st_helpers[4] = {
841
#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
843
static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
844
const TCGArg *args, int opc)
846
int addr_reg, data_reg, data_reg2;
847
#ifdef CONFIG_SOFTMMU
848
int mem_index, s_bits;
849
# if TARGET_LONG_BITS == 64
859
data_reg2 = 0; /* surpress warning */
861
#ifdef CONFIG_SOFTMMU
862
# if TARGET_LONG_BITS == 64
868
/* Should generate something like the following:
869
* shr r8, addr_reg, #TARGET_PAGE_BITS
870
* and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
871
* add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
873
# if CPU_TLB_BITS > 8
876
tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
877
8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
878
tcg_out_dat_imm(s, COND_AL, ARITH_AND,
879
0, 8, CPU_TLB_SIZE - 1);
880
tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
881
0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
883
* ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
884
* below, the offset is likely to exceed 12 bits if mem_index != 0 and
885
* not exceed otherwise, so use an
886
* add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
890
tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0,
891
(mem_index << (TLB_SHIFT & 1)) |
892
((16 - (TLB_SHIFT >> 1)) << 8));
893
tcg_out_ld32_12(s, COND_AL, 1, 0,
894
offsetof(CPUState, tlb_table[0][0].addr_read));
895
tcg_out_dat_reg(s, COND_AL, ARITH_CMP,
896
0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
897
/* Check alignment. */
899
tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
900
0, addr_reg, (1 << s_bits) - 1);
901
# if TARGET_LONG_BITS == 64
902
/* XXX: possibly we could use a block data load or writeback in
903
* the first access. */
904
tcg_out_ld32_12(s, COND_EQ, 1, 0,
905
offsetof(CPUState, tlb_table[0][0].addr_read) + 4);
906
tcg_out_dat_reg(s, COND_EQ, ARITH_CMP,
907
0, 1, addr_reg2, SHIFT_IMM_LSL(0));
909
tcg_out_ld32_12(s, COND_EQ, 1, 0,
910
offsetof(CPUState, tlb_table[0][0].addend));
914
tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, 1);
917
tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, 1);
920
tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, 1);
923
tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, 1);
927
tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, 1);
930
tcg_out_ld32_rwb(s, COND_EQ, data_reg, 1, addr_reg);
931
tcg_out_ld32_12(s, COND_EQ, data_reg2, 1, 4);
935
label_ptr = (void *) s->code_ptr;
936
tcg_out_b(s, COND_EQ, 8);
939
tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 14, SHIFT_IMM_LSL(0));
942
/* TODO: move this code to where the constants pool will be */
944
tcg_out_dat_reg(s, cond, ARITH_MOV,
945
0, 0, addr_reg, SHIFT_IMM_LSL(0));
946
# if TARGET_LONG_BITS == 32
947
tcg_out_dat_imm(s, cond, ARITH_MOV, 1, 0, mem_index);
950
tcg_out_dat_reg(s, cond, ARITH_MOV,
951
1, 0, addr_reg2, SHIFT_IMM_LSL(0));
952
tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
954
tcg_out_bl(s, cond, (tcg_target_long) qemu_ld_helpers[s_bits] -
955
(tcg_target_long) s->code_ptr);
959
tcg_out_dat_reg(s, cond, ARITH_MOV,
960
0, 0, 0, SHIFT_IMM_LSL(24));
961
tcg_out_dat_reg(s, cond, ARITH_MOV,
962
data_reg, 0, 0, SHIFT_IMM_ASR(24));
965
tcg_out_dat_reg(s, cond, ARITH_MOV,
966
0, 0, 0, SHIFT_IMM_LSL(16));
967
tcg_out_dat_reg(s, cond, ARITH_MOV,
968
data_reg, 0, 0, SHIFT_IMM_ASR(16));
975
tcg_out_dat_reg(s, cond, ARITH_MOV,
976
data_reg, 0, 0, SHIFT_IMM_LSL(0));
980
tcg_out_dat_reg(s, cond, ARITH_MOV,
981
data_reg, 0, 0, SHIFT_IMM_LSL(0));
983
tcg_out_dat_reg(s, cond, ARITH_MOV,
984
data_reg2, 0, 1, SHIFT_IMM_LSL(0));
989
tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 8, SHIFT_IMM_LSL(0));
992
*label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
996
tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
999
tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
1002
tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
1005
tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
1009
tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1012
/* TODO: use block load -
1013
* check that data_reg2 > data_reg or the other way */
1014
tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1015
tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);
1021
static inline void tcg_out_qemu_st(TCGContext *s, int cond,
1022
const TCGArg *args, int opc)
1024
int addr_reg, data_reg, data_reg2;
1025
#ifdef CONFIG_SOFTMMU
1026
int mem_index, s_bits;
1027
# if TARGET_LONG_BITS == 64
1030
uint32_t *label_ptr;
1035
data_reg2 = *args++;
1037
data_reg2 = 0; /* surpress warning */
1039
#ifdef CONFIG_SOFTMMU
1040
# if TARGET_LONG_BITS == 64
1041
addr_reg2 = *args++;
1046
/* Should generate something like the following:
1047
* shr r8, addr_reg, #TARGET_PAGE_BITS
1048
* and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
1049
* add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
1051
tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1052
8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
1053
tcg_out_dat_imm(s, COND_AL, ARITH_AND,
1054
0, 8, CPU_TLB_SIZE - 1);
1055
tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
1056
0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
1058
* ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
1059
* below, the offset is likely to exceed 12 bits if mem_index != 0 and
1060
* not exceed otherwise, so use an
1061
* add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1065
tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0,
1066
(mem_index << (TLB_SHIFT & 1)) |
1067
((16 - (TLB_SHIFT >> 1)) << 8));
1068
tcg_out_ld32_12(s, COND_AL, 1, 0,
1069
offsetof(CPUState, tlb_table[0][0].addr_write));
1070
tcg_out_dat_reg(s, COND_AL, ARITH_CMP,
1071
0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
1072
/* Check alignment. */
1074
tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1075
0, addr_reg, (1 << s_bits) - 1);
1076
# if TARGET_LONG_BITS == 64
1077
/* XXX: possibly we could use a block data load or writeback in
1078
* the first access. */
1079
tcg_out_ld32_12(s, COND_EQ, 1, 0,
1080
offsetof(CPUState, tlb_table[0][0].addr_write)
1082
tcg_out_dat_reg(s, COND_EQ, ARITH_CMP,
1083
0, 1, addr_reg2, SHIFT_IMM_LSL(0));
1085
tcg_out_ld32_12(s, COND_EQ, 1, 0,
1086
offsetof(CPUState, tlb_table[0][0].addend));
1090
tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, 1);
1093
tcg_out_st8s_r(s, COND_EQ, data_reg, addr_reg, 1);
1096
tcg_out_st16u_r(s, COND_EQ, data_reg, addr_reg, 1);
1099
tcg_out_st16s_r(s, COND_EQ, data_reg, addr_reg, 1);
1103
tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, 1);
1106
tcg_out_st32_rwb(s, COND_EQ, data_reg, 1, addr_reg);
1107
tcg_out_st32_12(s, COND_EQ, data_reg2, 1, 4);
1111
label_ptr = (void *) s->code_ptr;
1112
tcg_out_b(s, COND_EQ, 8);
1114
/* TODO: move this code to where the constants pool will be */
1116
tcg_out_dat_reg(s, cond, ARITH_MOV,
1117
0, 0, addr_reg, SHIFT_IMM_LSL(0));
1118
# if TARGET_LONG_BITS == 32
1121
tcg_out_dat_imm(s, cond, ARITH_AND, 1, data_reg, 0xff);
1122
tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1125
tcg_out_dat_reg(s, cond, ARITH_MOV,
1126
1, 0, data_reg, SHIFT_IMM_LSL(16));
1127
tcg_out_dat_reg(s, cond, ARITH_MOV,
1128
1, 0, 1, SHIFT_IMM_LSR(16));
1129
tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1133
tcg_out_dat_reg(s, cond, ARITH_MOV,
1134
1, 0, data_reg, SHIFT_IMM_LSL(0));
1135
tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1139
tcg_out_dat_reg(s, cond, ARITH_MOV,
1140
1, 0, data_reg, SHIFT_IMM_LSL(0));
1142
tcg_out_dat_reg(s, cond, ARITH_MOV,
1143
2, 0, data_reg2, SHIFT_IMM_LSL(0));
1144
tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1149
tcg_out_dat_reg(s, cond, ARITH_MOV,
1150
1, 0, addr_reg2, SHIFT_IMM_LSL(0));
1153
tcg_out_dat_imm(s, cond, ARITH_AND, 2, data_reg, 0xff);
1154
tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1157
tcg_out_dat_reg(s, cond, ARITH_MOV,
1158
2, 0, data_reg, SHIFT_IMM_LSL(16));
1159
tcg_out_dat_reg(s, cond, ARITH_MOV,
1160
2, 0, 2, SHIFT_IMM_LSR(16));
1161
tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1165
tcg_out_dat_reg(s, cond, ARITH_MOV,
1166
2, 0, data_reg, SHIFT_IMM_LSL(0));
1167
tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1170
tcg_out_dat_imm(s, cond, ARITH_MOV, 8, 0, mem_index);
1171
tcg_out32(s, (cond << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
1173
tcg_out_dat_reg(s, cond, ARITH_MOV,
1174
2, 0, data_reg, SHIFT_IMM_LSL(0));
1176
tcg_out_dat_reg(s, cond, ARITH_MOV,
1177
3, 0, data_reg2, SHIFT_IMM_LSL(0));
1183
tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 14, SHIFT_IMM_LSL(0));
1186
tcg_out_bl(s, cond, (tcg_target_long) qemu_st_helpers[s_bits] -
1187
(tcg_target_long) s->code_ptr);
1188
# if TARGET_LONG_BITS == 64
1190
tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 0x10);
1194
tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 8, SHIFT_IMM_LSL(0));
1197
*label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
1201
tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
1204
tcg_out_st8s_8(s, COND_AL, data_reg, addr_reg, 0);
1207
tcg_out_st16u_8(s, COND_AL, data_reg, addr_reg, 0);
1210
tcg_out_st16s_8(s, COND_AL, data_reg, addr_reg, 0);
1214
tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1217
/* TODO: use block store -
1218
* check that data_reg2 > data_reg or the other way */
1219
tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1220
tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4);
1226
static uint8_t *tb_ret_addr;
1228
static inline void tcg_out_op(TCGContext *s, int opc,
1229
const TCGArg *args, const int *const_args)
1234
case INDEX_op_exit_tb:
1237
tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, 15, 0);
1239
tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]);
1240
tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 15, 0, 14, SHIFT_IMM_LSL(0));
1242
tcg_out32(s, args[0]);
1245
uint8_t *ld_ptr = s->code_ptr;
1247
tcg_out_ld32_12(s, COND_AL, 0, 15, 0);
1249
tcg_out_dat_imm(s, COND_AL, ARITH_MOV, 0, 0, args[0]);
1250
tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr);
1252
*ld_ptr = (uint8_t) (s->code_ptr - ld_ptr) - 8;
1253
tcg_out32(s, args[0]);
1258
case INDEX_op_goto_tb:
1259
if (s->tb_jmp_offset) {
1260
/* Direct jump method */
1261
#if defined(USE_DIRECT_JUMP)
1262
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1263
tcg_out_b(s, COND_AL, 8);
1265
tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
1266
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1270
/* Indirect jump method */
1272
c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8);
1273
if (c > 0xfff || c < -0xfff) {
1274
tcg_out_movi32(s, COND_AL, TCG_REG_R0,
1275
(tcg_target_long) (s->tb_next + args[0]));
1276
tcg_out_ld32_12(s, COND_AL, 15, TCG_REG_R0, 0);
1278
tcg_out_ld32_12(s, COND_AL, 15, 15, c);
1280
tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, 15, 0);
1281
tcg_out_ld32_12(s, COND_AL, 15, TCG_REG_R0, 0);
1282
tcg_out32(s, (tcg_target_long) (s->tb_next + args[0]));
1285
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1289
tcg_out_call(s, COND_AL, args[0]);
1291
tcg_out_callr(s, COND_AL, args[0]);
1295
tcg_out_goto(s, COND_AL, args[0]);
1297
tcg_out_bx(s, COND_AL, args[0]);
1300
tcg_out_goto_label(s, COND_AL, args[0]);
1303
case INDEX_op_ld8u_i32:
1304
tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1306
case INDEX_op_ld8s_i32:
1307
tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1309
case INDEX_op_ld16u_i32:
1310
tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1312
case INDEX_op_ld16s_i32:
1313
tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1315
case INDEX_op_ld_i32:
1316
tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1318
case INDEX_op_st8_i32:
1319
tcg_out_st8u(s, COND_AL, args[0], args[1], args[2]);
1321
case INDEX_op_st16_i32:
1322
tcg_out_st16u(s, COND_AL, args[0], args[1], args[2]);
1324
case INDEX_op_st_i32:
1325
tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1328
case INDEX_op_mov_i32:
1329
tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1330
args[0], 0, args[1], SHIFT_IMM_LSL(0));
1332
case INDEX_op_movi_i32:
1333
tcg_out_movi32(s, COND_AL, args[0], args[1]);
1335
case INDEX_op_add_i32:
1338
case INDEX_op_sub_i32:
1341
case INDEX_op_and_i32:
1344
case INDEX_op_or_i32:
1347
case INDEX_op_xor_i32:
1351
tcg_out_dat_reg(s, COND_AL, c,
1352
args[0], args[1], args[2], SHIFT_IMM_LSL(0));
1354
case INDEX_op_add2_i32:
1355
tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
1356
args[0], args[1], args[2], args[3],
1357
args[4], args[5], SHIFT_IMM_LSL(0));
1359
case INDEX_op_sub2_i32:
1360
tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC,
1361
args[0], args[1], args[2], args[3],
1362
args[4], args[5], SHIFT_IMM_LSL(0));
1364
case INDEX_op_neg_i32:
1365
tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1367
case INDEX_op_mul_i32:
1368
tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1370
case INDEX_op_mulu2_i32:
1371
tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1373
case INDEX_op_div2_i32:
1374
tcg_out_div_helper(s, COND_AL, args,
1375
tcg_helper_div_i64, tcg_helper_rem_i64,
1378
case INDEX_op_divu2_i32:
1379
tcg_out_div_helper(s, COND_AL, args,
1380
tcg_helper_divu_i64, tcg_helper_remu_i64,
1383
/* XXX: Perhaps args[2] & 0x1f is wrong */
1384
case INDEX_op_shl_i32:
1386
SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1388
case INDEX_op_shr_i32:
1389
c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1390
SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1392
case INDEX_op_sar_i32:
1393
c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1394
SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
1397
tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1400
case INDEX_op_brcond_i32:
1401
tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1402
args[0], args[1], SHIFT_IMM_LSL(0));
1403
tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
1405
case INDEX_op_brcond2_i32:
1406
/* The resulting conditions are:
1407
* TCG_COND_EQ --> a0 == a2 && a1 == a3,
1408
* TCG_COND_NE --> (a0 != a2 && a1 == a3) || a1 != a3,
1409
* TCG_COND_LT(U) --> (a0 < a2 && a1 == a3) || a1 < a3,
1410
* TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1411
* TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1412
* TCG_COND_GT(U) --> (a0 > a2 && a1 == a3) || a1 > a3,
1414
tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1415
args[1], args[3], SHIFT_IMM_LSL(0));
1416
tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1417
args[0], args[2], SHIFT_IMM_LSL(0));
1418
tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
1421
case INDEX_op_qemu_ld8u:
1422
tcg_out_qemu_ld(s, COND_AL, args, 0);
1424
case INDEX_op_qemu_ld8s:
1425
tcg_out_qemu_ld(s, COND_AL, args, 0 | 4);
1427
case INDEX_op_qemu_ld16u:
1428
tcg_out_qemu_ld(s, COND_AL, args, 1);
1430
case INDEX_op_qemu_ld16s:
1431
tcg_out_qemu_ld(s, COND_AL, args, 1 | 4);
1433
case INDEX_op_qemu_ld32u:
1434
tcg_out_qemu_ld(s, COND_AL, args, 2);
1436
case INDEX_op_qemu_ld64:
1437
tcg_out_qemu_ld(s, COND_AL, args, 3);
1440
case INDEX_op_qemu_st8:
1441
tcg_out_qemu_st(s, COND_AL, args, 0);
1443
case INDEX_op_qemu_st16:
1444
tcg_out_qemu_st(s, COND_AL, args, 1);
1446
case INDEX_op_qemu_st32:
1447
tcg_out_qemu_st(s, COND_AL, args, 2);
1449
case INDEX_op_qemu_st64:
1450
tcg_out_qemu_st(s, COND_AL, args, 3);
1453
case INDEX_op_ext8s_i32:
1454
tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1455
args[0], 0, args[1], SHIFT_IMM_LSL(24));
1456
tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1457
args[0], 0, args[0], SHIFT_IMM_ASR(24));
1459
case INDEX_op_ext16s_i32:
1460
tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1461
args[0], 0, args[1], SHIFT_IMM_LSL(16));
1462
tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1463
args[0], 0, args[0], SHIFT_IMM_ASR(16));
1471
static const TCGTargetOpDef arm_op_defs[] = {
1472
{ INDEX_op_exit_tb, { } },
1473
{ INDEX_op_goto_tb, { } },
1474
{ INDEX_op_call, { "ri" } },
1475
{ INDEX_op_jmp, { "ri" } },
1476
{ INDEX_op_br, { } },
1478
{ INDEX_op_mov_i32, { "r", "r" } },
1479
{ INDEX_op_movi_i32, { "r" } },
1481
{ INDEX_op_ld8u_i32, { "r", "r" } },
1482
{ INDEX_op_ld8s_i32, { "r", "r" } },
1483
{ INDEX_op_ld16u_i32, { "r", "r" } },
1484
{ INDEX_op_ld16s_i32, { "r", "r" } },
1485
{ INDEX_op_ld_i32, { "r", "r" } },
1486
{ INDEX_op_st8_i32, { "r", "r" } },
1487
{ INDEX_op_st16_i32, { "r", "r" } },
1488
{ INDEX_op_st_i32, { "r", "r" } },
1490
/* TODO: "r", "r", "ri" */
1491
{ INDEX_op_add_i32, { "r", "r", "r" } },
1492
{ INDEX_op_sub_i32, { "r", "r", "r" } },
1493
{ INDEX_op_mul_i32, { "r", "r", "r" } },
1494
{ INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1495
{ INDEX_op_div2_i32, { "r", "r", "r", "1", "2" } },
1496
{ INDEX_op_divu2_i32, { "r", "r", "r", "1", "2" } },
1497
{ INDEX_op_and_i32, { "r", "r", "r" } },
1498
{ INDEX_op_or_i32, { "r", "r", "r" } },
1499
{ INDEX_op_xor_i32, { "r", "r", "r" } },
1500
{ INDEX_op_neg_i32, { "r", "r" } },
1502
{ INDEX_op_shl_i32, { "r", "r", "ri" } },
1503
{ INDEX_op_shr_i32, { "r", "r", "ri" } },
1504
{ INDEX_op_sar_i32, { "r", "r", "ri" } },
1506
{ INDEX_op_brcond_i32, { "r", "r" } },
1508
/* TODO: "r", "r", "r", "r", "ri", "ri" */
1509
{ INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1510
{ INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1511
{ INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1513
{ INDEX_op_qemu_ld8u, { "r", "x", "X" } },
1514
{ INDEX_op_qemu_ld8s, { "r", "x", "X" } },
1515
{ INDEX_op_qemu_ld16u, { "r", "x", "X" } },
1516
{ INDEX_op_qemu_ld16s, { "r", "x", "X" } },
1517
{ INDEX_op_qemu_ld32u, { "r", "x", "X" } },
1518
{ INDEX_op_qemu_ld64, { "d", "r", "x", "X" } },
1520
{ INDEX_op_qemu_st8, { "x", "x", "X" } },
1521
{ INDEX_op_qemu_st16, { "x", "x", "X" } },
1522
{ INDEX_op_qemu_st32, { "x", "x", "X" } },
1523
{ INDEX_op_qemu_st64, { "x", "D", "x", "X" } },
1525
{ INDEX_op_ext8s_i32, { "r", "r" } },
1526
{ INDEX_op_ext16s_i32, { "r", "r" } },
1531
void tcg_target_init(TCGContext *s)
1534
if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1537
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,
1538
((2 << TCG_REG_R14) - 1) & ~(1 << TCG_REG_R8));
1539
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1540
((2 << TCG_REG_R3) - 1) |
1541
(1 << TCG_REG_R12) | (1 << TCG_REG_R14));
1543
tcg_regset_clear(s->reserved_regs);
1545
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R14);
1547
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
1548
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
1550
tcg_add_target_add_op_defs(arm_op_defs);
1553
static inline void tcg_out_ld(TCGContext *s, TCGType type, int arg,
1554
int arg1, tcg_target_long arg2)
1556
tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
1559
static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
1560
int arg1, tcg_target_long arg2)
1562
tcg_out_st32(s, COND_AL, arg, arg1, arg2);
1565
void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
1569
tcg_out_dat_imm(s, COND_AL, ARITH_ADD, reg, reg, val);
1574
tcg_out_dat_imm(s, COND_AL, ARITH_SUB, reg, reg, -val);
1580
static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
1582
tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
1585
static inline void tcg_out_movi(TCGContext *s, TCGType type,
1586
int ret, tcg_target_long arg)
1588
tcg_out_movi32(s, COND_AL, ret, arg);
1591
void tcg_target_qemu_prologue(TCGContext *s)
1593
/* stmdb sp!, { r9 - r11, lr } */
1594
tcg_out32(s, (COND_AL << 28) | 0x092d4e00);
1596
tcg_out_bx(s, COND_AL, TCG_REG_R0);
1597
tb_ret_addr = s->code_ptr;
1599
/* ldmia sp!, { r9 - r11, pc } */
1600
tcg_out32(s, (COND_AL << 28) | 0x08bd8e00);