2
* QEMU Sparc SLAVIO serial port emulation
4
* Copyright (c) 2003-2005 Fabrice Bellard
6
* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
8
* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26
#include "qemu-char.h"
30
//#define DEBUG_SERIAL
39
* This is the serial port, mouse and keyboard part of chip STP2001
40
* (Slave I/O), also produced as NCR89C105. See
41
* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
43
* The serial ports implement full AMD AM8530 or Zilog Z8530 chips,
44
* mouse and keyboard ports don't implement all functions and they are
45
* only asynchronous. There is no DMA.
51
* 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented
53
* Implemented serial mouse protocol.
57
#define SER_DPRINTF(fmt, args...) \
58
do { printf("SER: " fmt , ##args); } while (0)
60
#define SER_DPRINTF(fmt, args...)
63
#define KBD_DPRINTF(fmt, args...) \
64
do { printf("KBD: " fmt , ##args); } while (0)
66
#define KBD_DPRINTF(fmt, args...)
69
#define MS_DPRINTF(fmt, args...) \
70
do { printf("MSC: " fmt , ##args); } while (0)
72
#define MS_DPRINTF(fmt, args...)
79
#define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a')
85
#define SERIO_QUEUE_SIZE 256
88
uint8_t data[SERIO_QUEUE_SIZE];
89
int rptr, wptr, count;
92
#define SERIAL_REGS 16
93
typedef struct ChannelState {
96
int rxint, txint, rxint_under_svc, txint_under_svc;
97
chn_id_t chn; // this channel, A (base+4) or B (base+0)
99
struct ChannelState *otherchn;
100
uint8_t rx, tx, wregs[SERIAL_REGS], rregs[SERIAL_REGS];
102
CharDriverState *chr;
103
int e0_mode, led_mode, caps_lock_mode, num_lock_mode;
108
struct ChannelState chn[2];
111
#define SERIAL_MAXADDR 7
112
#define SERIAL_SIZE (SERIAL_MAXADDR + 1)
113
#define SERIAL_CTRL 0
114
#define SERIAL_DATA 1
117
#define CMD_PTR_MASK 0x07
118
#define CMD_CMD_MASK 0x38
120
#define CMD_CLR_TXINT 0x28
121
#define CMD_CLR_IUS 0x38
123
#define INTR_INTALL 0x01
124
#define INTR_TXINT 0x02
125
#define INTR_RXMODEMSK 0x18
126
#define INTR_RXINT1ST 0x08
127
#define INTR_RXINTALL 0x10
130
#define RXCTRL_RXEN 0x01
132
#define TXCTRL1_PAREN 0x01
133
#define TXCTRL1_PAREV 0x02
134
#define TXCTRL1_1STOP 0x04
135
#define TXCTRL1_1HSTOP 0x08
136
#define TXCTRL1_2STOP 0x0c
137
#define TXCTRL1_STPMSK 0x0c
138
#define TXCTRL1_CLK1X 0x00
139
#define TXCTRL1_CLK16X 0x40
140
#define TXCTRL1_CLK32X 0x80
141
#define TXCTRL1_CLK64X 0xc0
142
#define TXCTRL1_CLKMSK 0xc0
144
#define TXCTRL2_TXEN 0x08
145
#define TXCTRL2_BITMSK 0x60
146
#define TXCTRL2_5BITS 0x00
147
#define TXCTRL2_7BITS 0x20
148
#define TXCTRL2_6BITS 0x40
149
#define TXCTRL2_8BITS 0x60
154
#define MINTR_STATUSHI 0x10
155
#define MINTR_RST_MASK 0xc0
156
#define MINTR_RST_B 0x40
157
#define MINTR_RST_A 0x80
158
#define MINTR_RST_ALL 0xc0
161
#define CLOCK_TRXC 0x08
165
#define MISC2_PLLDIS 0x30
167
#define EXTINT_DCD 0x08
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#define EXTINT_SYNCINT 0x10
169
#define EXTINT_CTSINT 0x20
170
#define EXTINT_TXUNDRN 0x40
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#define EXTINT_BRKINT 0x80
174
#define STATUS_RXAV 0x01
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#define STATUS_ZERO 0x02
176
#define STATUS_TXEMPTY 0x04
177
#define STATUS_DCD 0x08
178
#define STATUS_SYNC 0x10
179
#define STATUS_CTS 0x20
180
#define STATUS_TXUNDRN 0x40
181
#define STATUS_BRK 0x80
183
#define SPEC_ALLSENT 0x01
184
#define SPEC_BITS8 0x06
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#define IVEC_TXINTB 0x00
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#define IVEC_LONOINT 0x06
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#define IVEC_LORXINTA 0x0c
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#define IVEC_LORXINTB 0x04
190
#define IVEC_LOTXINTA 0x08
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#define IVEC_HINOINT 0x60
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#define IVEC_HIRXINTA 0x30
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#define IVEC_HIRXINTB 0x20
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#define IVEC_HITXINTA 0x10
196
#define INTR_EXTINTB 0x01
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#define INTR_TXINTB 0x02
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#define INTR_RXINTB 0x04
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#define INTR_EXTINTA 0x08
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#define INTR_TXINTA 0x10
201
#define INTR_RXINTA 0x20
215
static void handle_kbd_command(ChannelState *s, int val);
216
static int serial_can_receive(void *opaque);
217
static void serial_receive_byte(ChannelState *s, int ch);
218
static inline void set_txint(ChannelState *s);
220
static void clear_queue(void *opaque)
222
ChannelState *s = opaque;
223
SERIOQueue *q = &s->queue;
224
q->rptr = q->wptr = q->count = 0;
227
static void put_queue(void *opaque, int b)
229
ChannelState *s = opaque;
230
SERIOQueue *q = &s->queue;
232
SER_DPRINTF("channel %c put: 0x%02x\n", CHN_C(s), b);
233
if (q->count >= SERIO_QUEUE_SIZE)
235
q->data[q->wptr] = b;
236
if (++q->wptr == SERIO_QUEUE_SIZE)
239
serial_receive_byte(s, 0);
242
static uint32_t get_queue(void *opaque)
244
ChannelState *s = opaque;
245
SERIOQueue *q = &s->queue;
251
val = q->data[q->rptr];
252
if (++q->rptr == SERIO_QUEUE_SIZE)
256
SER_DPRINTF("channel %c get 0x%02x\n", CHN_C(s), val);
258
serial_receive_byte(s, 0);
262
static int slavio_serial_update_irq_chn(ChannelState *s)
264
if ((s->wregs[W_INTR] & INTR_INTALL) && // interrupts enabled
265
(((s->wregs[W_INTR] & INTR_TXINT) && s->txint == 1) ||
266
// tx ints enabled, pending
267
((((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINT1ST) ||
268
((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINTALL)) &&
269
s->rxint == 1) || // rx ints enabled, pending
270
((s->wregs[W_EXTINT] & EXTINT_BRKINT) &&
271
(s->rregs[R_STATUS] & STATUS_BRK)))) { // break int e&p
277
static void slavio_serial_update_irq(ChannelState *s)
281
irq = slavio_serial_update_irq_chn(s);
282
irq |= slavio_serial_update_irq_chn(s->otherchn);
284
SER_DPRINTF("IRQ = %d\n", irq);
285
qemu_set_irq(s->irq, irq);
288
static void slavio_serial_reset_chn(ChannelState *s)
293
for (i = 0; i < SERIAL_SIZE; i++) {
297
s->wregs[W_TXCTRL1] = TXCTRL1_1STOP; // 1X divisor, 1 stop bit, no parity
298
s->wregs[W_MINTR] = MINTR_RST_ALL;
299
s->wregs[W_CLOCK] = CLOCK_TRXC; // Synch mode tx clock = TRxC
300
s->wregs[W_MISC2] = MISC2_PLLDIS; // PLL disabled
301
s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT |
302
EXTINT_TXUNDRN | EXTINT_BRKINT; // Enable most interrupts
304
s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC |
305
STATUS_CTS | STATUS_TXUNDRN;
307
s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN;
308
s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT;
311
s->rxint = s->txint = 0;
312
s->rxint_under_svc = s->txint_under_svc = 0;
313
s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0;
317
static void slavio_serial_reset(void *opaque)
319
SerialState *s = opaque;
320
slavio_serial_reset_chn(&s->chn[0]);
321
slavio_serial_reset_chn(&s->chn[1]);
324
static inline void clr_rxint(ChannelState *s)
327
s->rxint_under_svc = 0;
328
if (s->chn == chn_a) {
329
if (s->wregs[W_MINTR] & MINTR_STATUSHI)
330
s->otherchn->rregs[R_IVEC] = IVEC_HINOINT;
332
s->otherchn->rregs[R_IVEC] = IVEC_LONOINT;
333
s->rregs[R_INTR] &= ~INTR_RXINTA;
335
if (s->wregs[W_MINTR] & MINTR_STATUSHI)
336
s->rregs[R_IVEC] = IVEC_HINOINT;
338
s->rregs[R_IVEC] = IVEC_LONOINT;
339
s->otherchn->rregs[R_INTR] &= ~INTR_RXINTB;
343
slavio_serial_update_irq(s);
346
static inline void set_rxint(ChannelState *s)
349
if (!s->txint_under_svc) {
350
s->rxint_under_svc = 1;
351
if (s->chn == chn_a) {
352
if (s->wregs[W_MINTR] & MINTR_STATUSHI)
353
s->otherchn->rregs[R_IVEC] = IVEC_HIRXINTA;
355
s->otherchn->rregs[R_IVEC] = IVEC_LORXINTA;
357
if (s->wregs[W_MINTR] & MINTR_STATUSHI)
358
s->rregs[R_IVEC] = IVEC_HIRXINTB;
360
s->rregs[R_IVEC] = IVEC_LORXINTB;
364
s->rregs[R_INTR] |= INTR_RXINTA;
366
s->otherchn->rregs[R_INTR] |= INTR_RXINTB;
367
slavio_serial_update_irq(s);
370
static inline void clr_txint(ChannelState *s)
373
s->txint_under_svc = 0;
374
if (s->chn == chn_a) {
375
if (s->wregs[W_MINTR] & MINTR_STATUSHI)
376
s->otherchn->rregs[R_IVEC] = IVEC_HINOINT;
378
s->otherchn->rregs[R_IVEC] = IVEC_LONOINT;
379
s->rregs[R_INTR] &= ~INTR_TXINTA;
381
if (s->wregs[W_MINTR] & MINTR_STATUSHI)
382
s->rregs[R_IVEC] = IVEC_HINOINT;
384
s->rregs[R_IVEC] = IVEC_LONOINT;
385
s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB;
389
slavio_serial_update_irq(s);
392
static inline void set_txint(ChannelState *s)
395
if (!s->rxint_under_svc) {
396
s->txint_under_svc = 1;
397
if (s->chn == chn_a) {
398
if (s->wregs[W_MINTR] & MINTR_STATUSHI)
399
s->otherchn->rregs[R_IVEC] = IVEC_HITXINTA;
401
s->otherchn->rregs[R_IVEC] = IVEC_LOTXINTA;
403
s->rregs[R_IVEC] = IVEC_TXINTB;
407
s->rregs[R_INTR] |= INTR_TXINTA;
409
s->otherchn->rregs[R_INTR] |= INTR_TXINTB;
410
slavio_serial_update_irq(s);
413
static void slavio_serial_update_parameters(ChannelState *s)
415
int speed, parity, data_bits, stop_bits;
416
QEMUSerialSetParams ssp;
418
if (!s->chr || s->type != ser)
421
if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) {
422
if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV)
429
if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) == TXCTRL1_2STOP)
433
switch (s->wregs[W_TXCTRL2] & TXCTRL2_BITMSK) {
448
speed = 2457600 / ((s->wregs[W_BRGLO] | (s->wregs[W_BRGHI] << 8)) + 2);
449
switch (s->wregs[W_TXCTRL1] & TXCTRL1_CLKMSK) {
465
ssp.data_bits = data_bits;
466
ssp.stop_bits = stop_bits;
467
SER_DPRINTF("channel %c: speed=%d parity=%c data=%d stop=%d\n", CHN_C(s),
468
speed, parity, data_bits, stop_bits);
469
qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
472
static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr,
475
SerialState *serial = opaque;
481
saddr = (addr & 3) >> 1;
482
channel = (addr & SERIAL_MAXADDR) >> 2;
483
s = &serial->chn[channel];
486
SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg,
491
newreg = val & CMD_PTR_MASK;
501
if (s->rxint_under_svc)
503
else if (s->txint_under_svc)
510
case W_INTR ... W_RXCTRL:
511
case W_SYNC1 ... W_TXBUF:
512
case W_MISC1 ... W_CLOCK:
513
case W_MISC2 ... W_EXTINT:
514
s->wregs[s->reg] = val;
520
s->wregs[s->reg] = val;
521
slavio_serial_update_parameters(s);
524
switch (val & MINTR_RST_MASK) {
529
slavio_serial_reset_chn(&serial->chn[1]);
532
slavio_serial_reset_chn(&serial->chn[0]);
535
slavio_serial_reset(serial);
548
SER_DPRINTF("Write channel %c, ch %d\n", CHN_C(s), val);
550
if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled
552
qemu_chr_write(s->chr, &s->tx, 1);
553
else if (s->type == kbd && !s->disabled) {
554
handle_kbd_command(s, val);
557
s->rregs[R_STATUS] |= STATUS_TXEMPTY; // Tx buffer empty
558
s->rregs[R_SPEC] |= SPEC_ALLSENT; // All sent
566
static uint32_t slavio_serial_mem_readb(void *opaque, target_phys_addr_t addr)
568
SerialState *serial = opaque;
574
saddr = (addr & 3) >> 1;
575
channel = (addr & SERIAL_MAXADDR) >> 2;
576
s = &serial->chn[channel];
579
SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg,
581
ret = s->rregs[s->reg];
585
s->rregs[R_STATUS] &= ~STATUS_RXAV;
587
if (s->type == kbd || s->type == mouse)
591
SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret);
593
qemu_chr_accept_input(s->chr);
601
static int serial_can_receive(void *opaque)
603
ChannelState *s = opaque;
606
if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) == 0) // Rx not enabled
607
|| ((s->rregs[R_STATUS] & STATUS_RXAV) == STATUS_RXAV))
608
// char already available
615
static void serial_receive_byte(ChannelState *s, int ch)
617
SER_DPRINTF("channel %c put ch %d\n", CHN_C(s), ch);
618
s->rregs[R_STATUS] |= STATUS_RXAV;
623
static void serial_receive_break(ChannelState *s)
625
s->rregs[R_STATUS] |= STATUS_BRK;
626
slavio_serial_update_irq(s);
629
static void serial_receive1(void *opaque, const uint8_t *buf, int size)
631
ChannelState *s = opaque;
632
serial_receive_byte(s, buf[0]);
635
static void serial_event(void *opaque, int event)
637
ChannelState *s = opaque;
638
if (event == CHR_EVENT_BREAK)
639
serial_receive_break(s);
642
static CPUReadMemoryFunc *slavio_serial_mem_read[3] = {
643
slavio_serial_mem_readb,
648
static CPUWriteMemoryFunc *slavio_serial_mem_write[3] = {
649
slavio_serial_mem_writeb,
654
static void slavio_serial_save_chn(QEMUFile *f, ChannelState *s)
658
qemu_put_be32s(f, &tmp); /* unused, was IRQ. */
659
qemu_put_be32s(f, &s->reg);
660
qemu_put_be32s(f, &s->rxint);
661
qemu_put_be32s(f, &s->txint);
662
qemu_put_be32s(f, &s->rxint_under_svc);
663
qemu_put_be32s(f, &s->txint_under_svc);
664
qemu_put_8s(f, &s->rx);
665
qemu_put_8s(f, &s->tx);
666
qemu_put_buffer(f, s->wregs, SERIAL_REGS);
667
qemu_put_buffer(f, s->rregs, SERIAL_REGS);
670
static void slavio_serial_save(QEMUFile *f, void *opaque)
672
SerialState *s = opaque;
674
slavio_serial_save_chn(f, &s->chn[0]);
675
slavio_serial_save_chn(f, &s->chn[1]);
678
static int slavio_serial_load_chn(QEMUFile *f, ChannelState *s, int version_id)
685
qemu_get_be32s(f, &tmp); /* unused */
686
qemu_get_be32s(f, &s->reg);
687
qemu_get_be32s(f, &s->rxint);
688
qemu_get_be32s(f, &s->txint);
689
if (version_id >= 2) {
690
qemu_get_be32s(f, &s->rxint_under_svc);
691
qemu_get_be32s(f, &s->txint_under_svc);
693
qemu_get_8s(f, &s->rx);
694
qemu_get_8s(f, &s->tx);
695
qemu_get_buffer(f, s->wregs, SERIAL_REGS);
696
qemu_get_buffer(f, s->rregs, SERIAL_REGS);
700
static int slavio_serial_load(QEMUFile *f, void *opaque, int version_id)
702
SerialState *s = opaque;
705
ret = slavio_serial_load_chn(f, &s->chn[0], version_id);
708
ret = slavio_serial_load_chn(f, &s->chn[1], version_id);
713
SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
714
CharDriverState *chr1, CharDriverState *chr2)
716
int slavio_serial_io_memory, i;
719
s = qemu_mallocz(sizeof(SerialState));
723
slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read,
724
slavio_serial_mem_write,
726
cpu_register_physical_memory(base, SERIAL_SIZE, slavio_serial_io_memory);
728
s->chn[0].chr = chr1;
729
s->chn[1].chr = chr2;
730
s->chn[0].disabled = 0;
731
s->chn[1].disabled = 0;
733
for (i = 0; i < 2; i++) {
735
s->chn[i].chn = 1 - i;
736
s->chn[i].type = ser;
738
qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive,
739
serial_receive1, serial_event, &s->chn[i]);
742
s->chn[0].otherchn = &s->chn[1];
743
s->chn[1].otherchn = &s->chn[0];
744
register_savevm("slavio_serial", base, 2, slavio_serial_save,
745
slavio_serial_load, s);
746
qemu_register_reset(slavio_serial_reset, s);
747
slavio_serial_reset(s);
751
static const uint8_t keycodes[128] = {
752
127, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 43, 53,
753
54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 89, 76, 77, 78,
754
79, 80, 81, 82, 83, 84, 85, 86, 87, 42, 99, 88, 100, 101, 102, 103,
755
104, 105, 106, 107, 108, 109, 110, 47, 19, 121, 119, 5, 6, 8, 10, 12,
756
14, 16, 17, 18, 7, 98, 23, 68, 69, 70, 71, 91, 92, 93, 125, 112,
757
113, 114, 94, 50, 0, 0, 124, 9, 11, 0, 0, 0, 0, 0, 0, 0,
758
90, 0, 46, 22, 13, 111, 52, 20, 96, 24, 28, 74, 27, 123, 44, 66,
759
0, 45, 2, 4, 48, 0, 0, 21, 0, 0, 0, 0, 0, 120, 122, 67,
762
static const uint8_t e0_keycodes[128] = {
763
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
764
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 90, 76, 0, 0,
765
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
766
0, 0, 0, 0, 0, 109, 0, 0, 13, 0, 0, 0, 0, 0, 0, 0,
767
0, 0, 0, 0, 0, 0, 0, 68, 69, 70, 0, 91, 0, 93, 0, 112,
768
113, 114, 94, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
769
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
770
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
773
static void sunkbd_event(void *opaque, int ch)
775
ChannelState *s = opaque;
776
int release = ch & 0x80;
778
KBD_DPRINTF("Untranslated keycode %2.2x (%s)\n", ch, release? "release" :
781
case 58: // Caps lock press
782
s->caps_lock_mode ^= 1;
783
if (s->caps_lock_mode == 2)
784
return; // Drop second press
786
case 69: // Num lock press
787
s->num_lock_mode ^= 1;
788
if (s->num_lock_mode == 2)
789
return; // Drop second press
791
case 186: // Caps lock release
792
s->caps_lock_mode ^= 2;
793
if (s->caps_lock_mode == 3)
794
return; // Drop first release
796
case 197: // Num lock release
797
s->num_lock_mode ^= 2;
798
if (s->num_lock_mode == 3)
799
return; // Drop first release
809
ch = e0_keycodes[ch & 0x7f];
811
ch = keycodes[ch & 0x7f];
813
KBD_DPRINTF("Translated keycode %2.2x\n", ch);
814
put_queue(s, ch | release);
817
static void handle_kbd_command(ChannelState *s, int val)
819
KBD_DPRINTF("Command %d\n", val);
820
if (s->led_mode) { // Ignore led byte
825
case 1: // Reset, return type code
828
put_queue(s, 4); // Type 4
831
case 0xe: // Set leds
834
case 7: // Query layout
838
put_queue(s, 0); // XXX, layout?
845
static void sunmouse_event(void *opaque,
846
int dx, int dy, int dz, int buttons_state)
848
ChannelState *s = opaque;
851
MS_DPRINTF("dx=%d dy=%d buttons=%01x\n", dx, dy, buttons_state);
853
ch = 0x80 | 0x7; /* protocol start byte, no buttons pressed */
855
if (buttons_state & MOUSE_EVENT_LBUTTON)
857
if (buttons_state & MOUSE_EVENT_MBUTTON)
859
if (buttons_state & MOUSE_EVENT_RBUTTON)
871
put_queue(s, ch & 0xff);
880
put_queue(s, ch & 0xff);
882
// MSC protocol specify two extra motion bytes
888
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
891
int slavio_serial_io_memory, i;
894
s = qemu_mallocz(sizeof(SerialState));
897
for (i = 0; i < 2; i++) {
899
s->chn[i].chn = 1 - i;
900
s->chn[i].chr = NULL;
902
s->chn[0].otherchn = &s->chn[1];
903
s->chn[1].otherchn = &s->chn[0];
904
s->chn[0].type = mouse;
905
s->chn[1].type = kbd;
906
s->chn[0].disabled = disabled;
907
s->chn[1].disabled = disabled;
909
slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read,
910
slavio_serial_mem_write,
912
cpu_register_physical_memory(base, SERIAL_SIZE, slavio_serial_io_memory);
914
qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0,
916
qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]);
917
register_savevm("slavio_serial_mouse", base, 2, slavio_serial_save,
918
slavio_serial_load, s);
919
qemu_register_reset(slavio_serial_reset, s);
920
slavio_serial_reset(s);