52
53
#define PCNET_IOPORT_SIZE 0x20
53
54
#define PCNET_PNPMMIO_SIZE 0x20
56
#define PCNET_LOOPTEST_CRC 1
57
#define PCNET_LOOPTEST_NOCRC 2
56
60
typedef struct PCNetState_st PCNetState;
76
80
void (*phys_mem_write)(void *dma_opaque, target_phys_addr_t addr,
77
81
uint8_t *buf, int len, int do_bswap);
81
86
struct qemu_ether_header {
120
125
#define CSR_DRX(S) !!(((S)->csr[15])&0x0001)
121
126
#define CSR_DTX(S) !!(((S)->csr[15])&0x0002)
122
127
#define CSR_LOOP(S) !!(((S)->csr[15])&0x0004)
128
#define CSR_DXMTFCS(S) !!(((S)->csr[15])&0x0008)
123
129
#define CSR_DRCVPA(S) !!(((S)->csr[15])&0x2000)
124
130
#define CSR_DRCVBC(S) !!(((S)->csr[15])&0x4000)
125
131
#define CSR_PROM(S) !!(((S)->csr[15])&0x8000)
202
208
#define TMDS_LTINT_SH 12
203
209
#define TMDS_NOFCS_MASK 0x2000
204
210
#define TMDS_NOFCS_SH 13
211
#define TMDS_ADDFCS_MASK TMDS_NOFCS_MASK
212
#define TMDS_ADDFCS_SH TMDS_NOFCS_SH
205
213
#define TMDS_ERR_MASK 0x4000
206
214
#define TMDS_ERR_SH 14
207
215
#define TMDS_OWN_MASK 0x8000
971
979
s->csr[37] = nnrd >> 16;
972
980
#ifdef PCNET_DEBUG
974
printf("pcnet: BAD RMD RECORDS AFTER 0x%08x\n",
982
printf("pcnet: BAD RMD RECORDS AFTER 0x" TARGET_FMT_plx "\n",
975
983
PHYSADDR(s,crda));
978
printf("pcnet: BAD RMD RDA=0x%08x\n", PHYSADDR(s,crda));
986
printf("pcnet: BAD RMD RDA=0x" TARGET_FMT_plx "\n",
1116
1127
s->csr[0] |= 0x1000; /* Set MISS flag */
1117
1128
CSR_MISSC(s)++;
1119
uint8_t *src = &s->buffer[8];
1130
uint8_t *src = s->buffer;
1120
1131
target_phys_addr_t crda = CSR_CRDA(s);
1121
1132
struct pcnet_RMD rmd;
1122
1133
int pktcount = 0;
1124
memcpy(src, buf, size);
1127
/* no need to compute the CRC */
1134
/* XXX: avoid CRC generation */
1135
if (!CSR_ASTRP_RCV(s)) {
1143
while (p != &src[size]) {
1146
((uint32_t *)&src[size])[0] = htonl(fcs);
1147
size += 4; /* FCS at end of packet */
1136
memcpy(src, buf, size);
1137
/* no need to compute the CRC */
1143
} else if (s->looptest == PCNET_LOOPTEST_CRC ||
1144
!CSR_DXMTFCS(s) || size < MIN_BUF_SIZE+4) {
1148
while (p != &src[size])
1150
*(uint32_t *)p = htonl(fcs);
1156
while (p != &src[size-4])
1158
crc_err = (*(uint32_t *)p != htonl(fcs));
1151
1161
#ifdef PCNET_DEBUG_MATCH
1152
1162
PRINT_PKTHDR(buf);
1157
1167
SET_FIELD(&rmd.status, RMDS, STP, 1);
1159
1169
#define PCNET_RECV_STORE() do { \
1160
int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),size); \
1170
int count = MIN(4096 - GET_FIELD(rmd.buf_length, RMDL, BCNT),remaining); \
1161
1171
target_phys_addr_t rbadr = PHYSADDR(s, rmd.rbadr); \
1162
1172
s->phys_mem_write(s->dma_opaque, rbadr, src, count, CSR_BSWP(s)); \
1163
src += count; size -= count; \
1164
SET_FIELD(&rmd.msg_length, RMDM, MCNT, count); \
1173
src += count; remaining -= count; \
1165
1174
SET_FIELD(&rmd.status, RMDS, OWN, 0); \
1166
1175
RMDSTORE(&rmd, PHYSADDR(s,crda)); \
1170
1180
PCNET_RECV_STORE();
1171
if ((size > 0) && CSR_NRDA(s)) {
1181
if ((remaining > 0) && CSR_NRDA(s)) {
1172
1182
target_phys_addr_t nrda = CSR_NRDA(s);
1183
#ifdef PCNET_DEBUG_RMD
1173
1186
RMDLOAD(&rmd, PHYSADDR(s,nrda));
1174
1187
if (GET_FIELD(rmd.status, RMDS, OWN)) {
1176
1189
PCNET_RECV_STORE();
1177
if ((size > 0) && (nrda=CSR_NNRD(s))) {
1190
#ifdef PCNET_DEBUG_RMD
1193
if ((remaining > 0) && (nrda=CSR_NNRD(s))) {
1178
1194
RMDLOAD(&rmd, PHYSADDR(s,nrda));
1179
1195
if (GET_FIELD(rmd.status, RMDS, OWN)) {
1187
1203
#undef PCNET_RECV_STORE
1189
1205
RMDLOAD(&rmd, PHYSADDR(s,crda));
1206
if (remaining == 0) {
1207
SET_FIELD(&rmd.msg_length, RMDM, MCNT, size);
1191
1208
SET_FIELD(&rmd.status, RMDS, ENP, 1);
1192
1209
SET_FIELD(&rmd.status, RMDS, PAM, !CSR_PROM(s) && is_padr);
1193
1210
SET_FIELD(&rmd.status, RMDS, LFAM, !CSR_PROM(s) && is_ladr);
1194
1211
SET_FIELD(&rmd.status, RMDS, BAM, !CSR_PROM(s) && is_bcast);
1213
SET_FIELD(&rmd.status, RMDS, CRC, 1);
1214
SET_FIELD(&rmd.status, RMDS, ERR, 1);
1196
1217
SET_FIELD(&rmd.status, RMDS, OFLO, 1);
1197
1218
SET_FIELD(&rmd.status, RMDS, BUFF, 1);
1250
1273
if (GET_FIELD(tmd.status, TMDS, STP)) {
1251
1274
s->xmit_pos = 0;
1252
if (!GET_FIELD(tmd.status, TMDS, ENP)) {
1253
int bcnt = 4096 - GET_FIELD(tmd.length, TMDL, BCNT);
1254
s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
1255
s->buffer, bcnt, CSR_BSWP(s));
1256
s->xmit_pos += bcnt;
1258
1275
xmit_cxda = PHYSADDR(s,CSR_CXDA(s));
1276
if (BCR_SWSTYLE(s) != 1)
1277
add_crc = GET_FIELD(tmd.status, TMDS, ADDFCS);
1260
if (GET_FIELD(tmd.status, TMDS, ENP) && (s->xmit_pos >= 0)) {
1279
if (!GET_FIELD(tmd.status, TMDS, ENP)) {
1280
int bcnt = 4096 - GET_FIELD(tmd.length, TMDL, BCNT);
1281
s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
1282
s->buffer + s->xmit_pos, bcnt, CSR_BSWP(s));
1283
s->xmit_pos += bcnt;
1284
} else if (s->xmit_pos >= 0) {
1261
1285
int bcnt = 4096 - GET_FIELD(tmd.length, TMDL, BCNT);
1262
1286
s->phys_mem_read(s->dma_opaque, PHYSADDR(s, tmd.tbadr),
1263
1287
s->buffer + s->xmit_pos, bcnt, CSR_BSWP(s));
1265
1289
#ifdef PCNET_DEBUG
1266
1290
printf("pcnet_transmit size=%d\n", s->xmit_pos);
1293
if (BCR_SWSTYLE(s) == 1)
1294
add_crc = !GET_FIELD(tmd.status, TMDS, NOFCS);
1295
s->looptest = add_crc ? PCNET_LOOPTEST_CRC : PCNET_LOOPTEST_NOCRC;
1269
1296
pcnet_receive(s, s->buffer, s->xmit_pos);
1272
1300
qemu_send_packet(s->vc, s->buffer, s->xmit_pos);
1745
1773
PCNetState *d = opaque;
1746
1774
#ifdef PCNET_DEBUG_IO
1747
printf("pcnet_mmio_writeb addr=0x%08x val=0x%02x\n", addr, val);
1775
printf("pcnet_mmio_writeb addr=0x" TARGET_FMT_plx" val=0x%02x\n", addr,
1749
1778
if (!(addr & 0x10))
1750
1779
pcnet_aprom_writeb(d, addr & 0x0f, val);
1757
1786
if (!(addr & 0x10))
1758
1787
val = pcnet_aprom_readb(d, addr & 0x0f);
1759
1788
#ifdef PCNET_DEBUG_IO
1760
printf("pcnet_mmio_readb addr=0x%08x val=0x%02x\n", addr, val & 0xff);
1789
printf("pcnet_mmio_readb addr=0x" TARGET_FMT_plx " val=0x%02x\n", addr,
1767
1797
PCNetState *d = opaque;
1768
1798
#ifdef PCNET_DEBUG_IO
1769
printf("pcnet_mmio_writew addr=0x%08x val=0x%04x\n", addr, val);
1799
printf("pcnet_mmio_writew addr=0x" TARGET_FMT_plx " val=0x%04x\n", addr,
1771
1802
if (addr & 0x10)
1772
1803
pcnet_ioport_writew(d, addr & 0x0f, val);
1790
1821
val |= pcnet_aprom_readb(d, addr);
1792
1823
#ifdef PCNET_DEBUG_IO
1793
printf("pcnet_mmio_readw addr=0x%08x val = 0x%04x\n", addr, val & 0xffff);
1824
printf("pcnet_mmio_readw addr=0x" TARGET_FMT_plx" val = 0x%04x\n", addr,
1800
1832
PCNetState *d = opaque;
1801
1833
#ifdef PCNET_DEBUG_IO
1802
printf("pcnet_mmio_writel addr=0x%08x val=0x%08x\n", addr, val);
1834
printf("pcnet_mmio_writel addr=0x" TARGET_FMT_plx" val=0x%08x\n", addr,
1804
1837
if (addr & 0x10)
1805
1838
pcnet_ioport_writel(d, addr & 0x0f, val);
1829
1862
val |= pcnet_aprom_readb(d, addr);
1831
1864
#ifdef PCNET_DEBUG_IO
1832
printf("pcnet_mmio_readl addr=0x%08x val=0x%08x\n", addr, val);
1865
printf("pcnet_mmio_readl addr=0x" TARGET_FMT_plx " val=0x%08x\n", addr,
1843
1877
if (s->pci_dev)
1844
1878
pci_device_save(s->pci_dev, f);
1846
qemu_put_be32(f, s->rap);
1847
qemu_put_be32(f, s->isr);
1848
qemu_put_be32(f, s->lnkst);
1880
qemu_put_sbe32(f, s->rap);
1881
qemu_put_sbe32(f, s->isr);
1882
qemu_put_sbe32(f, s->lnkst);
1849
1883
qemu_put_be32s(f, &s->rdra);
1850
1884
qemu_put_be32s(f, &s->tdra);
1851
1885
qemu_put_buffer(f, s->prom, 16);
1854
1888
for (i = 0; i < 32; i++)
1855
1889
qemu_put_be16s(f, &s->bcr[i]);
1856
1890
qemu_put_be64s(f, &s->timer);
1857
qemu_put_be32(f, s->xmit_pos);
1858
qemu_put_be32(f, s->recv_pos);
1891
qemu_put_sbe32(f, s->xmit_pos);
1892
qemu_put_sbe32(f, s->recv_pos);
1859
1893
qemu_put_buffer(f, s->buffer, 4096);
1860
qemu_put_be32(f, s->tx_busy);
1894
qemu_put_sbe32(f, s->tx_busy);
1861
1895
qemu_put_timer(f, s->poll_timer);
1878
qemu_get_be32s(f, (uint32_t*)&s->rap);
1879
qemu_get_be32s(f, (uint32_t*)&s->isr);
1880
qemu_get_be32s(f, (uint32_t*)&s->lnkst);
1912
qemu_get_sbe32s(f, &s->rap);
1913
qemu_get_sbe32s(f, &s->isr);
1914
qemu_get_sbe32s(f, &s->lnkst);
1881
1915
qemu_get_be32s(f, &s->rdra);
1882
1916
qemu_get_be32s(f, &s->tdra);
1883
1917
qemu_get_buffer(f, s->prom, 16);
1886
1920
for (i = 0; i < 32; i++)
1887
1921
qemu_get_be16s(f, &s->bcr[i]);
1888
1922
qemu_get_be64s(f, &s->timer);
1889
qemu_get_be32s(f, (uint32_t*)&s->xmit_pos);
1890
qemu_get_be32s(f, (uint32_t*)&s->recv_pos);
1923
qemu_get_sbe32s(f, &s->xmit_pos);
1924
qemu_get_sbe32s(f, &s->recv_pos);
1891
1925
qemu_get_buffer(f, s->buffer, 4096);
1892
qemu_get_be32s(f, (uint32_t*)&s->tx_busy);
1926
qemu_get_sbe32s(f, &s->tx_busy);
1893
1927
qemu_get_timer(f, s->poll_timer);
1898
static void pcnet_common_init(PCNetState *d, NICInfo *nd, const char *info_str)
1932
static void pcnet_common_init(PCNetState *d, NICInfo *nd)
1900
1934
d->poll_timer = qemu_new_timer(vm_clock, pcnet_poll_timer, d);
1904
1938
if (nd && nd->vlan) {
1905
d->vc = qemu_new_vlan_client(nd->vlan, pcnet_receive,
1906
pcnet_can_receive, d);
1939
d->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
1940
pcnet_receive, pcnet_can_receive, d);
1908
snprintf(d->vc->info_str, sizeof(d->vc->info_str),
1909
"pcnet macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
1942
qemu_format_nic_info_str(d->vc, d->nd->macaddr);
1919
1946
pcnet_h_reset(d);
1920
register_savevm("pcnet", 0, 2, pcnet_save, pcnet_load, d);
1947
register_savevm("pcnet", -1, 2, pcnet_save, pcnet_load, d);
1923
1950
/* PCI interface */
1940
1967
PCNetState *d = (PCNetState *)pci_dev;
1942
1969
#ifdef PCNET_DEBUG_IO
1943
printf("pcnet_ioport_map addr=0x%08x 0x%08x\n", addr, size);
1970
printf("pcnet_mmio_map addr=0x%08x 0x%08x\n", addr, size);
1946
1973
cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE, d->mmio_index);
1958
1985
cpu_physical_memory_read(addr, buf, len);
1961
void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn)
1988
PCIDevice *pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn)
1964
1991
uint8_t *pci_conf;
1974
2001
pci_conf = d->dev.config;
1976
*(uint16_t *)&pci_conf[0x00] = cpu_to_le16(0x1022);
1977
*(uint16_t *)&pci_conf[0x02] = cpu_to_le16(0x2000);
2003
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_AMD);
2004
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_AMD_LANCE);
1978
2005
*(uint16_t *)&pci_conf[0x04] = cpu_to_le16(0x0007);
1979
2006
*(uint16_t *)&pci_conf[0x06] = cpu_to_le16(0x0280);
1980
2007
pci_conf[0x08] = 0x10;
1981
2008
pci_conf[0x09] = 0x00;
1982
pci_conf[0x0a] = 0x00; // ethernet network controller
1983
pci_conf[0x0b] = 0x02;
2009
pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
1984
2010
pci_conf[0x0e] = 0x00; // header_type
1986
2012
*(uint32_t *)&pci_conf[0x10] = cpu_to_le32(0x00000001);
2005
2031
d->phys_mem_write = pci_physical_memory_write;
2006
2032
d->pci_dev = &d->dev;
2008
pcnet_common_init(d, nd, "pcnet");
2034
pcnet_common_init(d, nd);
2035
return (PCIDevice *)d;
2011
2038
/* SPARC32 interface */
2026
2053
printf("lance_mem_writew addr=" TARGET_FMT_plx " val=0x%04x\n", addr,
2029
pcnet_ioport_writew(opaque, addr & 7, val & 0xffff);
2056
pcnet_ioport_writew(opaque, addr, val & 0xffff);
2032
2059
static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)
2036
val = pcnet_ioport_readw(opaque, addr & 7);
2063
val = pcnet_ioport_readw(opaque, addr);
2037
2064
#ifdef PCNET_DEBUG_IO
2038
printf("pcnet_mmio_readw addr=" TARGET_FMT_plx " val = 0x%04x\n", addr,
2065
printf("lance_mem_readw addr=" TARGET_FMT_plx " val = 0x%04x\n", addr,
2061
2088
int lance_io_memory;
2090
qemu_check_nic_model(nd, "lance");
2063
2092
d = qemu_mallocz(sizeof(PCNetState));
2067
2094
lance_io_memory =
2068
2095
cpu_register_io_memory(0, lance_mem_read, lance_mem_write, d);
2077
2104
d->phys_mem_read = ledma_memory_read;
2078
2105
d->phys_mem_write = ledma_memory_write;
2080
pcnet_common_init(d, nd, "lance");
2107
pcnet_common_init(d, nd);
2082
2109
#endif /* TARGET_SPARC */