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#include "sysemu.h"
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#include "boards.h"
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#include "sh7750_regs.h"
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#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
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#define SDRAM_SIZE 0x04000000
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static void r2d_init(int ram_size, int vga_ram_size,
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const char *boot_device, DisplayState * ds,
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#define SM501_VRAM_SIZE 0x800000
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#define PA_IRLMSK 0x00
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#define PA_POWOFF 0x30
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#define PA_VERREG 0x32
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#define PA_OUTPORT 0x36
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PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
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SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
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static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
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[CF_IDE] = { 1, 1<<9 },
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[CF_CD] = { 2, 1<<8 },
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[PCI_INTA] = { 9, 1<<14 },
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[PCI_INTB] = { 10, 1<<13 },
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[PCI_INTC] = { 3, 1<<12 },
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[PCI_INTD] = { 0, 1<<11 },
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[SM501] = { 4, 1<<10 },
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[RTC_A] = { 6, 1<<5 },
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[RTC_T] = { 7, 1<<4 },
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[SDCARD] = { 8, 1<<7 },
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static void update_irl(r2d_fpga_t *fpga)
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for (i = 0; i < NR_IRQS; i++)
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if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
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if (irqtab[i].irl < irl)
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qemu_set_irq(fpga->irl, irl ^ 15);
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static void r2d_fpga_irq_set(void *opaque, int n, int level)
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r2d_fpga_t *fpga = opaque;
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fpga->irlmon |= irqtab[n].msk;
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fpga->irlmon &= ~irqtab[n].msk;
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static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
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r2d_fpga_t *s = opaque;
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r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
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r2d_fpga_t *s = opaque;
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static CPUReadMemoryFunc *r2d_fpga_readfn[] = {
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static CPUWriteMemoryFunc *r2d_fpga_writefn[] = {
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static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
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s = qemu_mallocz(sizeof(r2d_fpga_t));
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iomemtype = cpu_register_io_memory(0, r2d_fpga_readfn,
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r2d_fpga_writefn, s);
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cpu_register_physical_memory(base, 0x40, iomemtype);
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return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
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static void r2d_pci_set_irq(qemu_irq *p, int n, int l)
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qemu_set_irq(p[n], l);
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static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
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const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD };
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return intx[d->devfn >> 3];
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static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
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const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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struct SH7750State *s;
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ram_addr_t sdram_addr, sm501_vga_ram_addr;
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cpu_model = "SH7751R";
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env = cpu_init(cpu_model);
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/* Allocate memory space */
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cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, 0);
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sdram_addr = qemu_ram_alloc(SDRAM_SIZE);
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cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
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/* Register peripherals */
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s = sh7750_init(env);
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irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
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pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
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sm501_vga_ram_addr = qemu_ram_alloc(SM501_VRAM_SIZE);
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sm501_init(0x10000000, sm501_vga_ram_addr, SM501_VRAM_SIZE,
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/* onboard CF (True IDE mode, Master only). */
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if ((i = drive_get_index(IF_IDE, 0, 0)) != -1)
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mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
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drives_table[i].bdrv, NULL);
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/* NIC: rtl8139 on-board, and 2 slots. */
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for (i = 0; i < nb_nics; i++)
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pci_nic_init(pci, &nd_table[i], (i==0)? 2<<3: -1, "rtl8139");
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/* Todo: register on board registers */
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/* initialization which should be done by firmware */
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stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
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stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
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kernel_size = load_image(kernel_filename, phys_ram_base);