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.TH DELAYV_f 5 "Janvier 1997" "Scilab Group" "Scicos Block"
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DELAYV_f - Scicos time varying delay block
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.SH DIALOGUE PARAMETERS
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: size of the delayed vector (-1 not allowed)
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Register initial state
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: register initial state vector. Dimension must be greater than or
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: Maximum delay that can be produced by this block
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This block implements a time varying discretized delay. The value of
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the delay is given by the second input port. The delayed signal enters
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the first input port and leaves the unique output prot.
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The first event output port must be connected to unique input event port if
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auto clocking is desired. But the input event port can also be driven
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by outside clock. In that case, the max delay is size of initial
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condition times the period of the incoming clock.
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The second output event port generates an event if the second input
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goes above the maximum delay specified. This signal can be ignored. In
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that case the output will be delayed by max delay.
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DELAY_f, EVTDLY_f, REGISTER_f