6
/* The registers' definition is from section 3.2 of
7
* Embedded Cross Trigger Revision: r0p0
9
#define CTICONTROL 0x000
10
#define CTISTATUS 0x004
12
#define CTIPROTECTION 0x00C
13
#define CTIINTACK 0x010
14
#define CTIAPPSET 0x014
15
#define CTIAPPCLEAR 0x018
16
#define CTIAPPPULSE 0x01c
18
#define CTIOUTEN 0x0A0
19
#define CTITRIGINSTATUS 0x130
20
#define CTITRIGOUTSTATUS 0x134
21
#define CTICHINSTATUS 0x138
22
#define CTICHOUTSTATUS 0x13c
23
#define CTIPERIPHID0 0xFE0
24
#define CTIPERIPHID1 0xFE4
25
#define CTIPERIPHID2 0xFE8
26
#define CTIPERIPHID3 0xFEC
27
#define CTIPCELLID0 0xFF0
28
#define CTIPCELLID1 0xFF4
29
#define CTIPCELLID2 0xFF8
30
#define CTIPCELLID3 0xFFC
32
/* The below are from section 3.6.4 of
33
* CoreSight v1.0 Architecture Specification
35
#define LOCKACCESS 0xFB0
36
#define LOCKSTATUS 0xFB4
38
/* write this value to LOCKACCESS will unlock the module, and
39
* other value will lock the module
41
#define LOCKCODE 0xC5ACCE55
44
* struct cti - cross trigger interface struct
45
* @base: mapped virtual address for the cti base
46
* @irq: irq number for the cti
47
* @trig_out_for_irq: triger out number which will cause
50
* cti struct used to operate cti registers.
59
* cti_init - initialize the cti instance
61
* @base: mapped virtual address for the cti base
62
* @irq: irq number for the cti
63
* @trig_out: triger out number which will cause
66
* called by machine code to pass the board dependent
67
* @base, @irq and @trig_out to cti.
69
static inline void cti_init(struct cti *cti,
70
void __iomem *base, int irq, int trig_out)
74
cti->trig_out_for_irq = trig_out;
78
* cti_map_trigger - use the @chan to map @trig_in to @trig_out
80
* @trig_in: trigger in number
81
* @trig_out: trigger out number
82
* @channel: channel number
84
* This function maps one trigger in of @trig_in to one trigger
85
* out of @trig_out using the channel @chan.
87
static inline void cti_map_trigger(struct cti *cti,
88
int trig_in, int trig_out, int chan)
90
void __iomem *base = cti->base;
93
val = __raw_readl(base + CTIINEN + trig_in * 4);
95
__raw_writel(val, base + CTIINEN + trig_in * 4);
97
val = __raw_readl(base + CTIOUTEN + trig_out * 4);
99
__raw_writel(val, base + CTIOUTEN + trig_out * 4);
103
* cti_enable - enable the cti module
106
* enable the cti module
108
static inline void cti_enable(struct cti *cti)
110
__raw_writel(0x1, cti->base + CTICONTROL);
114
* cti_disable - disable the cti module
117
* enable the cti module
119
static inline void cti_disable(struct cti *cti)
121
__raw_writel(0, cti->base + CTICONTROL);
125
* cti_irq_ack - clear the cti irq
130
static inline void cti_irq_ack(struct cti *cti)
132
void __iomem *base = cti->base;
135
val = __raw_readl(base + CTIINTACK);
136
val |= BIT(cti->trig_out_for_irq);
137
__raw_writel(val, base + CTIINTACK);
141
* cti_unlock - unlock cti module
144
* unlock the cti module, or else any writes to the cti
145
* module is not allowed.
147
static inline void cti_unlock(struct cti *cti)
149
void __iomem *base = cti->base;
152
val = __raw_readl(base + LOCKSTATUS);
156
__raw_writel(val, base + LOCKACCESS);
161
* cti_lock - lock cti module
164
* lock the cti module, so any writes to the cti
165
* module will be not allowed.
167
static inline void cti_lock(struct cti *cti)
169
void __iomem *base = cti->base;
172
val = __raw_readl(base + LOCKSTATUS);
176
__raw_writel(val, base + LOCKACCESS);