2
* arch/powerpc/platforms/pseries/xics.c
4
* Copyright 2000 IBM Corporation.
6
* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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#include <linux/types.h>
13
#include <linux/threads.h>
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/radix-tree.h>
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#include <linux/cpu.h>
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#include <linux/msi.h>
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#include <linux/percpu.h>
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#include <asm/firmware.h>
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#include <asm/pgtable.h>
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#include <asm/hvcall.h>
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#include <asm/machdep.h>
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#include "plpar_wrappers.h"
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static struct irq_host *xics_host;
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#define XICS_IRQ_SPURIOUS 0
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/* Want a priority other than 0. Various HW issues require this. */
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#define DEFAULT_PRIORITY 5
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* Mark IPIs as higher priority so we can take them inside interrupts that
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* arent marked IRQF_DISABLED
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#define IPI_PRIORITY 4
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/* The least favored priority */
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#define LOWEST_PRIORITY 0xFF
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/* The number of priorities defined above */
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#define MAX_NUM_PRIORITIES 3
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static unsigned int default_server = 0xFF;
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static unsigned int default_distrib_server = 0;
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static unsigned int interrupt_server_size = 8;
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/* RTAS service tokens */
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static int ibm_get_xive;
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static int ibm_set_xive;
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static int ibm_int_on;
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static int ibm_int_off;
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unsigned char stack[MAX_NUM_PRIORITIES];
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static DEFINE_PER_CPU(struct xics_cppr, xics_cppr);
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/* Direct hardware low level accessors */
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/* The part of the interrupt presentation layer that we care about */
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static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
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static inline unsigned int direct_xirr_info_get(void)
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int cpu = smp_processor_id();
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return in_be32(&xics_per_cpu[cpu]->xirr.word);
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static inline void direct_xirr_info_set(unsigned int value)
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int cpu = smp_processor_id();
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out_be32(&xics_per_cpu[cpu]->xirr.word, value);
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static inline void direct_cppr_info(u8 value)
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int cpu = smp_processor_id();
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out_8(&xics_per_cpu[cpu]->xirr.bytes[0], value);
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static inline void direct_qirr_info(int n_cpu, u8 value)
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out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
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/* LPAR low level accessors */
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static inline unsigned int lpar_xirr_info_get(unsigned char cppr)
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unsigned long lpar_rc;
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unsigned long return_value;
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lpar_rc = plpar_xirr(&return_value, cppr);
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if (lpar_rc != H_SUCCESS)
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panic(" bad return code xirr - rc = %lx\n", lpar_rc);
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return (unsigned int)return_value;
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static inline void lpar_xirr_info_set(unsigned int value)
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unsigned long lpar_rc;
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lpar_rc = plpar_eoi(value);
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if (lpar_rc != H_SUCCESS)
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panic("bad return code EOI - rc = %ld, value=%x\n", lpar_rc,
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static inline void lpar_cppr_info(u8 value)
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unsigned long lpar_rc;
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lpar_rc = plpar_cppr(value);
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if (lpar_rc != H_SUCCESS)
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panic("bad return code cppr - rc = %lx\n", lpar_rc);
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static inline void lpar_qirr_info(int n_cpu , u8 value)
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unsigned long lpar_rc;
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lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value);
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if (lpar_rc != H_SUCCESS)
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panic("bad return code qirr - rc = %lx\n", lpar_rc);
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/* Interface to generic irq subsystem */
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* For the moment we only implement delivery to all cpus or one cpu.
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* If the requested affinity is cpu_all_mask, we set global affinity.
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* If not we set it to the first cpu in the mask, even if multiple cpus
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* are set. This is so things like irqbalance (which set core and package
172
* wide affinities) do the right thing.
174
static int get_irq_server(unsigned int virq, const struct cpumask *cpumask,
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unsigned int strict_check)
178
if (!distribute_irqs)
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return default_server;
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if (!cpumask_subset(cpu_possible_mask, cpumask)) {
182
int server = cpumask_first_and(cpu_online_mask, cpumask);
184
if (server < nr_cpu_ids)
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return get_hard_smp_processor_id(server);
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* Workaround issue with some versions of JS20 firmware that
193
* deliver interrupts to cpus which haven't been started. This
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* happens when using the maxcpus= boot option.
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if (cpumask_equal(cpu_online_mask, cpu_present_mask))
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return default_distrib_server;
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return default_server;
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#define get_irq_server(virq, cpumask, strict_check) (default_server)
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static void xics_unmask_irq(struct irq_data *d)
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pr_devel("xics: unmask virq %d\n", d->irq);
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hwirq = (unsigned int)irq_map[d->irq].hwirq;
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pr_devel(" -> map to hwirq 0x%x\n", hwirq);
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if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS)
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server = get_irq_server(d->irq, d->affinity, 0);
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call_status = rtas_call(ibm_set_xive, 3, 1, NULL, hwirq, server,
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if (call_status != 0) {
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"%s: ibm_set_xive irq %u server %x returned %d\n",
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__func__, hwirq, server, call_status);
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/* Now unmask the interrupt (often a no-op) */
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call_status = rtas_call(ibm_int_on, 1, 1, NULL, hwirq);
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if (call_status != 0) {
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printk(KERN_ERR "%s: ibm_int_on irq=%u returned %d\n",
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__func__, hwirq, call_status);
238
static unsigned int xics_startup(struct irq_data *d)
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* The generic MSI code returns with the interrupt disabled on the
242
* card, using the MSI mask bits. Firmware doesn't appear to unmask
243
* at that level, so we do it here by hand.
253
static void xics_mask_real_irq(unsigned int hwirq)
257
if (hwirq == XICS_IPI)
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call_status = rtas_call(ibm_int_off, 1, 1, NULL, hwirq);
261
if (call_status != 0) {
262
printk(KERN_ERR "%s: ibm_int_off irq=%u returned %d\n",
263
__func__, hwirq, call_status);
267
/* Have to set XIVE to 0xff to be able to remove a slot */
268
call_status = rtas_call(ibm_set_xive, 3, 1, NULL, hwirq,
269
default_server, 0xff);
270
if (call_status != 0) {
271
printk(KERN_ERR "%s: ibm_set_xive(0xff) irq=%u returned %d\n",
272
__func__, hwirq, call_status);
277
static void xics_mask_irq(struct irq_data *d)
281
pr_devel("xics: mask virq %d\n", d->irq);
283
hwirq = (unsigned int)irq_map[d->irq].hwirq;
284
if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS)
286
xics_mask_real_irq(hwirq);
289
static void xics_mask_unknown_vec(unsigned int vec)
291
printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec);
292
xics_mask_real_irq(vec);
295
static inline unsigned int xics_xirr_vector(unsigned int xirr)
298
* The top byte is the old cppr, to be restored on EOI.
299
* The remaining 24 bits are the vector.
301
return xirr & 0x00ffffff;
304
static void push_cppr(unsigned int vec)
306
struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
308
if (WARN_ON(os_cppr->index >= MAX_NUM_PRIORITIES - 1))
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os_cppr->stack[++os_cppr->index] = IPI_PRIORITY;
314
os_cppr->stack[++os_cppr->index] = DEFAULT_PRIORITY;
317
static unsigned int xics_get_irq_direct(void)
319
unsigned int xirr = direct_xirr_info_get();
320
unsigned int vec = xics_xirr_vector(xirr);
323
if (vec == XICS_IRQ_SPURIOUS)
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irq = irq_radix_revmap_lookup(xics_host, vec);
327
if (likely(irq != NO_IRQ)) {
332
/* We don't have a linux mapping, so have rtas mask it. */
333
xics_mask_unknown_vec(vec);
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/* We might learn about it later, so EOI it */
336
direct_xirr_info_set(xirr);
340
static unsigned int xics_get_irq_lpar(void)
342
struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
343
unsigned int xirr = lpar_xirr_info_get(os_cppr->stack[os_cppr->index]);
344
unsigned int vec = xics_xirr_vector(xirr);
347
if (vec == XICS_IRQ_SPURIOUS)
350
irq = irq_radix_revmap_lookup(xics_host, vec);
351
if (likely(irq != NO_IRQ)) {
356
/* We don't have a linux mapping, so have RTAS mask it. */
357
xics_mask_unknown_vec(vec);
359
/* We might learn about it later, so EOI it */
360
lpar_xirr_info_set(xirr);
364
static unsigned char pop_cppr(void)
366
struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
368
if (WARN_ON(os_cppr->index < 1))
369
return LOWEST_PRIORITY;
371
return os_cppr->stack[--os_cppr->index];
374
static void xics_eoi_direct(struct irq_data *d)
376
unsigned int hwirq = (unsigned int)irq_map[d->irq].hwirq;
379
direct_xirr_info_set((pop_cppr() << 24) | hwirq);
382
static void xics_eoi_lpar(struct irq_data *d)
384
unsigned int hwirq = (unsigned int)irq_map[d->irq].hwirq;
387
lpar_xirr_info_set((pop_cppr() << 24) | hwirq);
391
xics_set_affinity(struct irq_data *d, const struct cpumask *cpumask, bool force)
398
hwirq = (unsigned int)irq_map[d->irq].hwirq;
399
if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS)
402
status = rtas_call(ibm_get_xive, 1, 3, xics_status, hwirq);
405
printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n",
406
__func__, hwirq, status);
410
irq_server = get_irq_server(d->irq, cpumask, 1);
411
if (irq_server == -1) {
413
cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
415
"%s: No online cpus in the mask %s for irq %d\n",
416
__func__, cpulist, d->irq);
420
status = rtas_call(ibm_set_xive, 3, 1, NULL,
421
hwirq, irq_server, xics_status[1]);
424
printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n",
425
__func__, hwirq, status);
432
static struct irq_chip xics_pic_direct = {
434
.irq_startup = xics_startup,
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.irq_mask = xics_mask_irq,
436
.irq_unmask = xics_unmask_irq,
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.irq_eoi = xics_eoi_direct,
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.irq_set_affinity = xics_set_affinity
441
static struct irq_chip xics_pic_lpar = {
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.irq_startup = xics_startup,
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.irq_mask = xics_mask_irq,
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.irq_unmask = xics_unmask_irq,
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.irq_eoi = xics_eoi_lpar,
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.irq_set_affinity = xics_set_affinity
451
/* Interface to arch irq controller subsystem layer */
453
/* Points to the irq_chip we're actually using */
454
static struct irq_chip *xics_irq_chip;
456
static int xics_host_match(struct irq_host *h, struct device_node *node)
458
/* IBM machines have interrupt parents of various funky types for things
459
* like vdevices, events, etc... The trick we use here is to match
460
* everything here except the legacy 8259 which is compatible "chrp,iic"
462
return !of_device_is_compatible(node, "chrp,iic");
465
static int xics_host_map(struct irq_host *h, unsigned int virq,
468
pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
470
/* Insert the interrupt mapping into the radix tree for fast lookup */
471
irq_radix_revmap_insert(xics_host, virq, hw);
473
irq_set_status_flags(virq, IRQ_LEVEL);
474
irq_set_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
478
static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
479
const u32 *intspec, unsigned int intsize,
480
irq_hw_number_t *out_hwirq, unsigned int *out_flags)
483
/* Current xics implementation translates everything
484
* to level. It is not technically right for MSIs but this
485
* is irrelevant at this point. We might get smarter in the future
487
*out_hwirq = intspec[0];
488
*out_flags = IRQ_TYPE_LEVEL_LOW;
493
static struct irq_host_ops xics_host_ops = {
494
.match = xics_host_match,
495
.map = xics_host_map,
496
.xlate = xics_host_xlate,
499
static void __init xics_init_host(void)
501
if (firmware_has_feature(FW_FEATURE_LPAR))
502
xics_irq_chip = &xics_pic_lpar;
504
xics_irq_chip = &xics_pic_direct;
506
xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops,
508
BUG_ON(xics_host == NULL);
509
irq_set_default_host(xics_host);
513
/* Inter-processor interrupt support */
517
* XICS only has a single IPI, so encode the messages per CPU
519
static DEFINE_PER_CPU_SHARED_ALIGNED(unsigned long, xics_ipi_message);
521
static inline void smp_xics_do_message(int cpu, int msg)
523
unsigned long *tgt = &per_cpu(xics_ipi_message, cpu);
527
if (firmware_has_feature(FW_FEATURE_LPAR))
528
lpar_qirr_info(cpu, IPI_PRIORITY);
530
direct_qirr_info(cpu, IPI_PRIORITY);
533
void smp_xics_message_pass(int target, int msg)
537
if (target < NR_CPUS) {
538
smp_xics_do_message(target, msg);
540
for_each_online_cpu(i) {
541
if (target == MSG_ALL_BUT_SELF
542
&& i == smp_processor_id())
544
smp_xics_do_message(i, msg);
549
static irqreturn_t xics_ipi_dispatch(int cpu)
551
unsigned long *tgt = &per_cpu(xics_ipi_message, cpu);
553
mb(); /* order mmio clearing qirr */
555
if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, tgt)) {
556
smp_message_recv(PPC_MSG_CALL_FUNCTION);
558
if (test_and_clear_bit(PPC_MSG_RESCHEDULE, tgt)) {
559
smp_message_recv(PPC_MSG_RESCHEDULE);
561
if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE, tgt)) {
562
smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE);
564
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
565
if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK, tgt)) {
566
smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
573
static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id)
575
int cpu = smp_processor_id();
577
direct_qirr_info(cpu, 0xff);
579
return xics_ipi_dispatch(cpu);
582
static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id)
584
int cpu = smp_processor_id();
586
lpar_qirr_info(cpu, 0xff);
588
return xics_ipi_dispatch(cpu);
591
static void xics_request_ipi(void)
596
ipi = irq_create_mapping(xics_host, XICS_IPI);
597
BUG_ON(ipi == NO_IRQ);
600
* IPIs are marked IRQF_DISABLED as they must run with irqs
603
irq_set_handler(ipi, handle_percpu_irq);
604
if (firmware_has_feature(FW_FEATURE_LPAR))
605
rc = request_irq(ipi, xics_ipi_action_lpar,
606
IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL);
608
rc = request_irq(ipi, xics_ipi_action_direct,
609
IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL);
613
int __init smp_xics_probe(void)
617
return cpumask_weight(cpu_possible_mask);
620
#endif /* CONFIG_SMP */
625
static void xics_update_irq_servers(void)
628
struct device_node *np;
633
/* Find the server numbers for the boot cpu. */
634
np = of_get_cpu_node(boot_cpuid, NULL);
637
ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
643
i = ilen / sizeof(int);
644
hcpuid = get_hard_smp_processor_id(boot_cpuid);
646
/* Global interrupt distribution server is specified in the last
647
* entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
648
* entry fom this property for current boot cpu id and use it as
649
* default distribution server
651
for (j = 0; j < i; j += 2) {
652
if (ireg[j] == hcpuid) {
653
default_server = hcpuid;
654
default_distrib_server = ireg[j+1];
661
static void __init xics_map_one_cpu(int hw_id, unsigned long addr,
666
/* This may look gross but it's good enough for now, we don't quite
667
* have a hard -> linux processor id matching.
669
for_each_possible_cpu(i) {
672
if (hw_id == get_hard_smp_processor_id(i)) {
673
xics_per_cpu[i] = ioremap(addr, size);
679
static void __init xics_init_one_node(struct device_node *np,
685
/* This code does the theorically broken assumption that the interrupt
686
* server numbers are the same as the hard CPU numbers.
687
* This happens to be the case so far but we are playing with fire...
688
* should be fixed one of these days. -BenH.
690
ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL);
692
/* Do that ever happen ? we'll know soon enough... but even good'old
693
* f80 does have that property ..
695
WARN_ON(ireg == NULL);
698
* set node starting index for this node
702
ireg = of_get_property(np, "reg", &ilen);
704
panic("xics_init_IRQ: can't find interrupt reg property");
706
while (ilen >= (4 * sizeof(u32))) {
707
unsigned long addr, size;
709
/* XXX Use proper OF parsing code here !!! */
710
addr = (unsigned long)*ireg++ << 32;
714
size = (unsigned long)*ireg++ << 32;
718
xics_map_one_cpu(*indx, addr, size);
723
void __init xics_init_IRQ(void)
725
struct device_node *np;
730
ppc64_boot_msg(0x20, "XICS Init");
732
ibm_get_xive = rtas_token("ibm,get-xive");
733
ibm_set_xive = rtas_token("ibm,set-xive");
734
ibm_int_on = rtas_token("ibm,int-on");
735
ibm_int_off = rtas_token("ibm,int-off");
737
for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") {
739
if (firmware_has_feature(FW_FEATURE_LPAR)) {
743
xics_init_one_node(np, &indx);
748
/* get the bit size of server numbers */
751
for_each_compatible_node(np, NULL, "ibm,ppc-xics") {
752
isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
758
interrupt_server_size = *isize;
760
} else if (*isize != interrupt_server_size) {
761
printk(KERN_WARNING "XICS: "
762
"mismatched ibm,interrupt-server#-size\n");
763
interrupt_server_size = max(*isize,
764
interrupt_server_size);
768
xics_update_irq_servers();
771
if (firmware_has_feature(FW_FEATURE_LPAR))
772
ppc_md.get_irq = xics_get_irq_lpar;
774
ppc_md.get_irq = xics_get_irq_direct;
778
ppc64_boot_msg(0x21, "XICS Done");
781
/* Cpu startup, shutdown, and hotplug */
783
static void xics_set_cpu_priority(unsigned char cppr)
785
struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
788
* we only really want to set the priority when there's
789
* just one cppr value on the stack
791
WARN_ON(os_cppr->index != 0);
793
os_cppr->stack[0] = cppr;
795
if (firmware_has_feature(FW_FEATURE_LPAR))
796
lpar_cppr_info(cppr);
798
direct_cppr_info(cppr);
802
/* Have the calling processor join or leave the specified global queue */
803
static void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
808
if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
811
index = (1UL << interrupt_server_size) - 1 - gserver;
813
status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);
815
WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
816
GLOBAL_INTERRUPT_QUEUE, index, join, status);
819
void xics_setup_cpu(void)
821
xics_set_cpu_priority(LOWEST_PRIORITY);
823
xics_set_cpu_giq(default_distrib_server, 1);
826
void xics_teardown_cpu(void)
828
struct xics_cppr *os_cppr = &__get_cpu_var(xics_cppr);
829
int cpu = smp_processor_id();
832
* we have to reset the cppr index to 0 because we're
833
* not going to return from the IPI
836
xics_set_cpu_priority(0);
838
/* Clear any pending IPI request */
839
if (firmware_has_feature(FW_FEATURE_LPAR))
840
lpar_qirr_info(cpu, 0xff);
842
direct_qirr_info(cpu, 0xff);
845
void xics_kexec_teardown_cpu(int secondary)
850
* we take the ipi irq but and never return so we
851
* need to EOI the IPI, but want to leave our priority 0
853
* should we check all the other interrupts too?
854
* should we be flagging idle loop instead?
855
* or creating some task to be scheduled?
858
if (firmware_has_feature(FW_FEATURE_LPAR))
859
lpar_xirr_info_set((0x00 << 24) | XICS_IPI);
861
direct_xirr_info_set((0x00 << 24) | XICS_IPI);
864
* Some machines need to have at least one cpu in the GIQ,
865
* so leave the master cpu in the group.
868
xics_set_cpu_giq(default_distrib_server, 0);
871
#ifdef CONFIG_HOTPLUG_CPU
873
/* Interrupts are disabled. */
874
void xics_migrate_irqs_away(void)
876
int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
879
/* If we used to be the default server, move to the new "boot_cpuid" */
880
if (hw_cpu == default_server)
881
xics_update_irq_servers();
883
/* Reject any interrupt that was queued to us... */
884
xics_set_cpu_priority(0);
886
/* Remove ourselves from the global interrupt queue */
887
xics_set_cpu_giq(default_distrib_server, 0);
889
/* Allow IPIs again... */
890
xics_set_cpu_priority(DEFAULT_PRIORITY);
893
struct irq_desc *desc;
894
struct irq_chip *chip;
900
/* We can't set affinity on ISA interrupts */
901
if (virq < NUM_ISA_INTERRUPTS)
903
if (irq_map[virq].host != xics_host)
905
hwirq = (unsigned int)irq_map[virq].hwirq;
906
/* We need to get IPIs still. */
907
if (hwirq == XICS_IPI || hwirq == XICS_IRQ_SPURIOUS)
910
desc = irq_to_desc(virq);
912
/* We only need to migrate enabled IRQS */
913
if (desc == NULL || desc->action == NULL)
916
chip = irq_desc_get_chip(desc);
917
if (chip == NULL || chip->irq_set_affinity == NULL)
920
raw_spin_lock_irqsave(&desc->lock, flags);
922
status = rtas_call(ibm_get_xive, 1, 3, xics_status, hwirq);
924
printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n",
925
__func__, hwirq, status);
930
* We only support delivery to all cpus or to one cpu.
931
* The irq has to be migrated only in the single cpu
934
if (xics_status[0] != hw_cpu)
937
/* This is expected during cpu offline. */
939
printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n",
942
/* Reset affinity to all cpus */
943
cpumask_setall(desc->irq_data.affinity);
944
chip->irq_set_affinity(&desc->irq_data, cpu_all_mask, true);
946
raw_spin_unlock_irqrestore(&desc->lock, flags);
added
removed
arch/powerpc/platforms/pseries/xics.c
