~ubuntu-branches/ubuntu/quantal/linux-linaro-mx51/quantal : revision 10

64

MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");

65

MODULE_VERSION("3.6.26");

66

MODULE_LICENSE("GPL");

67

static int cciss_tape_cmds = 6;

68

module_param(cciss_tape_cmds, int, 0644);

69

MODULE_PARM_DESC(cciss_tape_cmds,

70

"number of commands to allocate for tape devices (default: 6)");

67

71

68

72

static DEFINE_MUTEX(cciss_mutex);

69

73

static struct proc_dir_entry *proc_cciss;

194

198

static int __devinit cciss_pci_find_memory_BAR(struct pci_dev *pdev,

195

199

unsigned long *memory_bar);

196

200

static inline u32 cciss_tag_discard_error_bits(ctlr_info_t *h, u32 tag);

201

static __devinit int write_driver_ver_to_cfgtable(

202

CfgTable_struct __iomem *cfgtable);

197

203

198

204

/* performant mode helper functions */

199

205

static void calc_bucket_map(int *bucket, int num_buckets, int nsgs,

556

562

#define to_hba(n) container_of(n, struct ctlr_info, dev)

557

563

#define to_drv(n) container_of(n, drive_info_struct, dev)

558

564

559

/* List of controllers which cannot be reset on kexec with reset_devices */

565

/* List of controllers which cannot be hard reset on kexec with reset_devices */

560

566

static u32 unresettable_controller[] = {

561

567

0x324a103C, /* Smart Array P712m */

562

568

0x324b103C, /* SmartArray P711m */

574

580

0x409D0E11, /* Smart Array 6400 EM */

575

581

};

576

582

577

static int ctlr_is_resettable(struct ctlr_info *h)

583

/* List of controllers which cannot even be soft reset */

584

static u32 soft_unresettable_controller[] = {

585

0x409C0E11, /* Smart Array 6400 */

586

0x409D0E11, /* Smart Array 6400 EM */

587

};

588

589

static int ctlr_is_hard_resettable(u32 board_id)

578

590

{

579

591

int i;

580

592

581

593

for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)

582

if (unresettable_controller[i] == h->board_id)

583

return 0;

584

return 1;

594

if (unresettable_controller[i] == board_id)

595

return 0;

596

return 1;

597

}

598

599

static int ctlr_is_soft_resettable(u32 board_id)

600

{

601

int i;

602

603

for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)

604

if (soft_unresettable_controller[i] == board_id)

605

return 0;

606

return 1;

607

}

608

609

static int ctlr_is_resettable(u32 board_id)

610

{

611

return ctlr_is_hard_resettable(board_id) ||

612

ctlr_is_soft_resettable(board_id);

585

613

}

586

614

587

615

static ssize_t host_show_resettable(struct device *dev,

590

618

{

591

619

struct ctlr_info *h = to_hba(dev);

592

620

593

return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h));

621

return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));

594

622

}

595

623

static DEVICE_ATTR(resettable, S_IRUGO, host_show_resettable, NULL);

596

624

2567

2595

}

2568

2596

} else if (cmd_type == TYPE_MSG) {

2569

2597

switch (cmd) {

2570

case 0: /* ABORT message */

2598

case CCISS_ABORT_MSG:

2571

2599

c->Request.CDBLen = 12;

2572

2600

c->Request.Type.Attribute = ATTR_SIMPLE;

2573

2601

c->Request.Type.Direction = XFER_WRITE;

2577

2605

/* buff contains the tag of the command to abort */

2578

2606

memcpy(&c->Request.CDB[4], buff, 8);

2579

2607

break;

2580

case 1: /* RESET message */

2608

case CCISS_RESET_MSG:

2581

2609

c->Request.CDBLen = 16;

2582

2610

c->Request.Type.Attribute = ATTR_SIMPLE;

2583

2611

c->Request.Type.Direction = XFER_NONE;

2584

2612

c->Request.Timeout = 0;

2585

2613

memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));

2586

2614

c->Request.CDB[0] = cmd; /* reset */

2587

c->Request.CDB[1] = 0x03; /* reset a target */

2615

c->Request.CDB[1] = CCISS_RESET_TYPE_TARGET;

2588

2616

break;

2589

case 3: /* No-Op message */

2617

case CCISS_NOOP_MSG:

2590

2618

c->Request.CDBLen = 1;

2591

2619

c->Request.Type.Attribute = ATTR_SIMPLE;

2592

2620

c->Request.Type.Direction = XFER_WRITE;

2615

2643

return status;

2616

2644

}

2617

2645

2646

static int __devinit cciss_send_reset(ctlr_info_t *h, unsigned char *scsi3addr,

2647

u8 reset_type)

2648

{

2649

CommandList_struct *c;

2650

int return_status;

2651

2652

c = cmd_alloc(h);

2653

if (!c)

2654

return -ENOMEM;

2655

return_status = fill_cmd(h, c, CCISS_RESET_MSG, NULL, 0, 0,

2656

CTLR_LUNID, TYPE_MSG);

2657

c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */

2658

if (return_status != IO_OK) {

2659

cmd_special_free(h, c);

2660

return return_status;

2661

}

2662

c->waiting = NULL;

2663

enqueue_cmd_and_start_io(h, c);

2664

/* Don't wait for completion, the reset won't complete. Don't free

2665

* the command either. This is the last command we will send before

2666

* re-initializing everything, so it doesn't matter and won't leak.

2667

*/

2668

return 0;

2669

}

2670

2618

2671

static int check_target_status(ctlr_info_t *h, CommandList_struct *c)

2619

2672

{

2620

2673

switch (c->err_info->ScsiStatus) {

3461

3514

return next_command(h);

3462

3515

}

3463

3516

3517

/* Some controllers, like p400, will give us one interrupt

3518

* after a soft reset, even if we turned interrupts off.

3519

* Only need to check for this in the cciss_xxx_discard_completions

3520

* functions.

3521

*/

3522

static int ignore_bogus_interrupt(ctlr_info_t *h)

3523

{

3524

if (likely(!reset_devices))

3525

return 0;

3526

3527

if (likely(h->interrupts_enabled))

3528

return 0;

3529

3530

dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "

3531

"(known firmware bug.) Ignoring.\n");

3532

3533

return 1;

3534

}

3535

3536

static irqreturn_t cciss_intx_discard_completions(int irq, void *dev_id)

3537

{

3538

ctlr_info_t *h = dev_id;

3539

unsigned long flags;

3540

u32 raw_tag;

3541

3542

if (ignore_bogus_interrupt(h))

3543

return IRQ_NONE;

3544

3545

if (interrupt_not_for_us(h))

3546

return IRQ_NONE;

3547

spin_lock_irqsave(&h->lock, flags);

3548

while (interrupt_pending(h)) {

3549

raw_tag = get_next_completion(h);

3550

while (raw_tag != FIFO_EMPTY)

3551

raw_tag = next_command(h);

3552

}

3553

spin_unlock_irqrestore(&h->lock, flags);

3554

return IRQ_HANDLED;

3555

}

3556

3557

static irqreturn_t cciss_msix_discard_completions(int irq, void *dev_id)

3558

{

3559

ctlr_info_t *h = dev_id;

3560

unsigned long flags;

3561

u32 raw_tag;

3562

3563

if (ignore_bogus_interrupt(h))

3564

return IRQ_NONE;

3565

3566

spin_lock_irqsave(&h->lock, flags);

3567

raw_tag = get_next_completion(h);

3568

while (raw_tag != FIFO_EMPTY)

3569

raw_tag = next_command(h);

3570

spin_unlock_irqrestore(&h->lock, flags);

3571

return IRQ_HANDLED;

3572

}

3573

3464

3574

static irqreturn_t do_cciss_intx(int irq, void *dev_id)

3465

3575

{

3466

3576

ctlr_info_t *h = dev_id;

4078

4188

cfg_base_addr_index) + cfg_offset, sizeof(h->cfgtable));

4079

4189

if (!h->cfgtable)

4080

4190

return -ENOMEM;

4191

rc = write_driver_ver_to_cfgtable(h->cfgtable);

4192

if (rc)

4193

return rc;

4081

4194

/* Find performant mode table. */

4082

4195

trans_offset = readl(&h->cfgtable->TransMethodOffset);

4083

4196

h->transtable = remap_pci_mem(pci_resource_start(h->pdev,

4112

4225

static void __devinit cciss_find_board_params(ctlr_info_t *h)

4113

4226

{

4114

4227

cciss_get_max_perf_mode_cmds(h);

4115

h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */

4228

h->nr_cmds = h->max_commands - 4 - cciss_tape_cmds;

4116

4229

h->maxsgentries = readl(&(h->cfgtable->MaxSGElements));

4117

4230

/*

4118

4231

* Limit in-command s/g elements to 32 save dma'able memory.

4348

4461

tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);

4349

4462

if ((tag & ~3) == paddr32)

4350

4463

break;

4351

schedule_timeout_uninterruptible(HZ);

4464

msleep(CCISS_POST_RESET_NOOP_TIMEOUT_MSECS);

4352

4465

}

4353

4466

4354

4467

iounmap(vaddr);

4375

4488

return 0;

4376

4489

}

4377

4490

4378

#define cciss_soft_reset_controller(p) cciss_message(p, 1, 0)

4379

4491

#define cciss_noop(p) cciss_message(p, 3, 0)

4380

4492

4381

4493

static int cciss_controller_hard_reset(struct pci_dev *pdev,

4382

void * __iomem vaddr, bool use_doorbell)

4494

void * __iomem vaddr, u32 use_doorbell)

4383

4495

{

4384

4496

u16 pmcsr;

4385

4497

int pos;

4390

4502

* other way using the doorbell register.

4391

4503

*/

4392

4504

dev_info(&pdev->dev, "using doorbell to reset controller\n");

4393

writel(DOORBELL_CTLR_RESET, vaddr + SA5_DOORBELL);

4394

msleep(1000);

4505

writel(use_doorbell, vaddr + SA5_DOORBELL);

4395

4506

} else { /* Try to do it the PCI power state way */

4396

4507

4397

4508

/* Quoting from the Open CISS Specification: "The Power

4422

4533

pmcsr &= ~PCI_PM_CTRL_STATE_MASK;

4423

4534

pmcsr |= PCI_D0;

4424

4535

pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);

4425

4426

msleep(500);

4427

4536

}

4428

4537

return 0;

4429

4538

}

4430

4539

4540

static __devinit void init_driver_version(char *driver_version, int len)

4541

{

4542

memset(driver_version, 0, len);

4543

strncpy(driver_version, "cciss " DRIVER_NAME, len - 1);

4544

}

4545

4546

static __devinit int write_driver_ver_to_cfgtable(

4547

CfgTable_struct __iomem *cfgtable)

4548

{

4549

char *driver_version;

4550

int i, size = sizeof(cfgtable->driver_version);

4551

4552

driver_version = kmalloc(size, GFP_KERNEL);

4553

if (!driver_version)

4554

return -ENOMEM;

4555

4556

init_driver_version(driver_version, size);

4557

for (i = 0; i < size; i++)

4558

writeb(driver_version[i], &cfgtable->driver_version[i]);

4559

kfree(driver_version);

4560

return 0;

4561

}

4562

4563

static __devinit void read_driver_ver_from_cfgtable(

4564

CfgTable_struct __iomem *cfgtable, unsigned char *driver_ver)

4565

{

4566

int i;

4567

4568

for (i = 0; i < sizeof(cfgtable->driver_version); i++)

4569

driver_ver[i] = readb(&cfgtable->driver_version[i]);

4570

}

4571

4572

static __devinit int controller_reset_failed(

4573

CfgTable_struct __iomem *cfgtable)

4574

{

4575

4576

char *driver_ver, *old_driver_ver;

4577

int rc, size = sizeof(cfgtable->driver_version);

4578

4579

old_driver_ver = kmalloc(2 * size, GFP_KERNEL);

4580

if (!old_driver_ver)

4581

return -ENOMEM;

4582

driver_ver = old_driver_ver + size;

4583

4584

/* After a reset, the 32 bytes of "driver version" in the cfgtable

4585

* should have been changed, otherwise we know the reset failed.

4586

*/

4587

init_driver_version(old_driver_ver, size);

4588

read_driver_ver_from_cfgtable(cfgtable, driver_ver);

4589

rc = !memcmp(driver_ver, old_driver_ver, size);

4590

kfree(old_driver_ver);

4591

return rc;

4592

}

4593

4431

4594

/* This does a hard reset of the controller using PCI power management

4432

4595

* states or using the doorbell register. */

4433

4596

static __devinit int cciss_kdump_hard_reset_controller(struct pci_dev *pdev)

4437

4600

u64 cfg_base_addr_index;

4438

4601

void __iomem *vaddr;

4439

4602

unsigned long paddr;

4440

u32 misc_fw_support, active_transport;

4603

u32 misc_fw_support;

4441

4604

int rc;

4442

4605

CfgTable_struct __iomem *cfgtable;

4443

bool use_doorbell;

4606

u32 use_doorbell;

4444

4607

u32 board_id;

4445

4608

u16 command_register;

4446

4609

4464

4627

* likely not be happy. Just forbid resetting this conjoined mess.

4465

4628

*/

4466

4629

cciss_lookup_board_id(pdev, &board_id);

4467

if (board_id == 0x409C0E11 || board_id == 0x409D0E11) {

4630

if (!ctlr_is_resettable(board_id)) {

4468

4631

dev_warn(&pdev->dev, "Cannot reset Smart Array 640x "

4469

4632

"due to shared cache module.");

4470

4633

return -ENODEV;

4471

4634

}

4472

4635

4636

/* if controller is soft- but not hard resettable... */

4637

if (!ctlr_is_hard_resettable(board_id))

4638

return -ENOTSUPP; /* try soft reset later. */

4639

4473

4640

/* Save the PCI command register */

4474

4641

pci_read_config_word(pdev, 4, &command_register);

4475

4642

/* Turn the board off. This is so that later pci_restore_state()

4497

4664

rc = -ENOMEM;

4498

4665

goto unmap_vaddr;

4499

4666

}

4667

rc = write_driver_ver_to_cfgtable(cfgtable);

4668

if (rc)

4669

goto unmap_vaddr;

4500

4670

4501

/* If reset via doorbell register is supported, use that. */

4671

/* If reset via doorbell register is supported, use that.

4672

* There are two such methods. Favor the newest method.

4673

*/

4502

4674

misc_fw_support = readl(&cfgtable->misc_fw_support);

4503

use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;

4504

4505

/* The doorbell reset seems to cause lockups on some Smart

4506

* Arrays (e.g. P410, P410i, maybe others). Until this is

4507

* fixed or at least isolated, avoid the doorbell reset.

4508

*/

4509

use_doorbell = 0;

4675

use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;

4676

if (use_doorbell) {

4677

use_doorbell = DOORBELL_CTLR_RESET2;

4678

} else {

4679

use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;

4680

if (use_doorbell) {

4681

dev_warn(&pdev->dev, "Controller claims that "

4682

"'Bit 2 doorbell reset' is "

4683

"supported, but not 'bit 5 doorbell reset'. "

4684

"Firmware update is recommended.\n");

4685

rc = -ENOTSUPP; /* use the soft reset */

4686

goto unmap_cfgtable;

4687

}

4688

}

4510

4689

4511

4690

rc = cciss_controller_hard_reset(pdev, vaddr, use_doorbell);

4512

4691

if (rc)

4524

4703

msleep(CCISS_POST_RESET_PAUSE_MSECS);

4525

4704

4526

4705

/* Wait for board to become not ready, then ready. */

4527

dev_info(&pdev->dev, "Waiting for board to become ready.\n");

4706

dev_info(&pdev->dev, "Waiting for board to reset.\n");

4528

4707

rc = cciss_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);

4529

if (rc) /* Don't bail, might be E500, etc. which can't be reset */

4530

dev_warn(&pdev->dev,

4531

"failed waiting for board to become not ready\n");

4708

if (rc) {

4709

dev_warn(&pdev->dev, "Failed waiting for board to hard reset."

4710

" Will try soft reset.\n");

4711

rc = -ENOTSUPP; /* Not expected, but try soft reset later */

4712

goto unmap_cfgtable;

4713

}

4532

4714

rc = cciss_wait_for_board_state(pdev, vaddr, BOARD_READY);

4533

4715

if (rc) {

4534

4716

dev_warn(&pdev->dev,

4535

"failed waiting for board to become ready\n");

4717

"failed waiting for board to become ready "

4718

"after hard reset\n");

4536

4719

goto unmap_cfgtable;

4537

4720

}

4538

dev_info(&pdev->dev, "board ready.\n");

4539

4721

4540

/* Controller should be in simple mode at this point. If it's not,

4541

* It means we're on one of those controllers which doesn't support

4542

* the doorbell reset method and on which the PCI power management reset

4543

* method doesn't work (P800, for example.)

4544

* In those cases, don't try to proceed, as it generally doesn't work.

4545

*/

4546

active_transport = readl(&cfgtable->TransportActive);

4547

if (active_transport & PERFORMANT_MODE) {

4548

dev_warn(&pdev->dev, "Unable to successfully reset controller,"

4549

" Ignoring controller.\n");

4550

rc = -ENODEV;

4722

rc = controller_reset_failed(vaddr);

4723

if (rc < 0)

4724

goto unmap_cfgtable;

4725

if (rc) {

4726

dev_warn(&pdev->dev, "Unable to successfully hard reset "

4727

"controller. Will try soft reset.\n");

4728

rc = -ENOTSUPP; /* Not expected, but try soft reset later */

4729

} else {

4730

dev_info(&pdev->dev, "Board ready after hard reset.\n");

4551

4731

}

4552

4732

4553

4733

unmap_cfgtable:

4574

4754

* due to concerns about shared bbwc between 6402/6404 pair.

4575

4755

*/

4576

4756

if (rc == -ENOTSUPP)

4577

return 0; /* just try to do the kdump anyhow. */

4757

return rc; /* just try to do the kdump anyhow. */

4578

4758

if (rc)

4579

4759

return -ENODEV;

4580

4760

4581

4761

/* Now try to get the controller to respond to a no-op */

4762

dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");

4582

4763

for (i = 0; i < CCISS_POST_RESET_NOOP_RETRIES; i++) {

4583

4764

if (cciss_noop(pdev) == 0)

4584

4765

break;

4591

4772

return 0;

4592

4773

}

4593

4774

4775

static __devinit int cciss_allocate_cmd_pool(ctlr_info_t *h)

4776

{

4777

h->cmd_pool_bits = kmalloc(

4778

DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *

4779

sizeof(unsigned long), GFP_KERNEL);

4780

h->cmd_pool = pci_alloc_consistent(h->pdev,

4781

h->nr_cmds * sizeof(CommandList_struct),

4782

&(h->cmd_pool_dhandle));

4783

h->errinfo_pool = pci_alloc_consistent(h->pdev,

4784

h->nr_cmds * sizeof(ErrorInfo_struct),

4785

&(h->errinfo_pool_dhandle));

4786

if ((h->cmd_pool_bits == NULL)

4787

|| (h->cmd_pool == NULL)

4788

|| (h->errinfo_pool == NULL)) {

4789

dev_err(&h->pdev->dev, "out of memory");

4790

return -ENOMEM;

4791

}

4792

return 0;

4793

}

4794

4795

static __devinit int cciss_allocate_scatterlists(ctlr_info_t *h)

4796

{

4797

int i;

4798

4799

/* zero it, so that on free we need not know how many were alloc'ed */

4800

h->scatter_list = kzalloc(h->max_commands *

4801

sizeof(struct scatterlist *), GFP_KERNEL);

4802

if (!h->scatter_list)

4803

return -ENOMEM;

4804

4805

for (i = 0; i < h->nr_cmds; i++) {

4806

h->scatter_list[i] = kmalloc(sizeof(struct scatterlist) *

4807

h->maxsgentries, GFP_KERNEL);

4808

if (h->scatter_list[i] == NULL) {

4809

dev_err(&h->pdev->dev, "could not allocate "

4810

"s/g lists\n");

4811

return -ENOMEM;

4812

}

4813

}

4814

return 0;

4815

}

4816

4817

static void cciss_free_scatterlists(ctlr_info_t *h)

4818

{

4819

int i;

4820

4821

if (h->scatter_list) {

4822

for (i = 0; i < h->nr_cmds; i++)

4823

kfree(h->scatter_list[i]);

4824

kfree(h->scatter_list);

4825

}

4826

}

4827

4828

static void cciss_free_cmd_pool(ctlr_info_t *h)

4829

{

4830

kfree(h->cmd_pool_bits);

4831

if (h->cmd_pool)

4832

pci_free_consistent(h->pdev,

4833

h->nr_cmds * sizeof(CommandList_struct),

4834

h->cmd_pool, h->cmd_pool_dhandle);

4835

if (h->errinfo_pool)

4836

pci_free_consistent(h->pdev,

4837

h->nr_cmds * sizeof(ErrorInfo_struct),

4838

h->errinfo_pool, h->errinfo_pool_dhandle);

4839

}

4840

4841

static int cciss_request_irq(ctlr_info_t *h,

4842

irqreturn_t (*msixhandler)(int, void *),

4843

irqreturn_t (*intxhandler)(int, void *))

4844

{

4845

if (h->msix_vector || h->msi_vector) {

4846

if (!request_irq(h->intr[PERF_MODE_INT], msixhandler,

4847

IRQF_DISABLED, h->devname, h))

4848

return 0;

4849

dev_err(&h->pdev->dev, "Unable to get msi irq %d"

4850

" for %s\n", h->intr[PERF_MODE_INT],

4851

h->devname);

4852

return -1;

4853

}

4854

4855

if (!request_irq(h->intr[PERF_MODE_INT], intxhandler,

4856

IRQF_DISABLED, h->devname, h))

4857

return 0;

4858

dev_err(&h->pdev->dev, "Unable to get irq %d for %s\n",

4859

h->intr[PERF_MODE_INT], h->devname);

4860

return -1;

4861

}

4862

4863

static int __devinit cciss_kdump_soft_reset(ctlr_info_t *h)

4864

{

4865

if (cciss_send_reset(h, CTLR_LUNID, CCISS_RESET_TYPE_CONTROLLER)) {

4866

dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");

4867

return -EIO;

4868

}

4869

4870

dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");

4871

if (cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {

4872

dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");

4873

return -1;

4874

}

4875

4876

dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");

4877

if (cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {

4878

dev_warn(&h->pdev->dev, "Board failed to become ready "

4879

"after soft reset.\n");

4880

return -1;

4881

}

4882

4883

return 0;

4884

}

4885

4886

static void cciss_undo_allocations_after_kdump_soft_reset(ctlr_info_t *h)

4887

{

4888

int ctlr = h->ctlr;

4889

4890

free_irq(h->intr[PERF_MODE_INT], h);

4891

#ifdef CONFIG_PCI_MSI

4892

if (h->msix_vector)

4893

pci_disable_msix(h->pdev);

4894

else if (h->msi_vector)

4895

pci_disable_msi(h->pdev);

4896

#endif /* CONFIG_PCI_MSI */

4897

cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);

4898

cciss_free_scatterlists(h);

4899

cciss_free_cmd_pool(h);

4900

kfree(h->blockFetchTable);

4901

if (h->reply_pool)

4902

pci_free_consistent(h->pdev, h->max_commands * sizeof(__u64),

4903

h->reply_pool, h->reply_pool_dhandle);

4904

if (h->transtable)

4905

iounmap(h->transtable);

4906

if (h->cfgtable)

4907

iounmap(h->cfgtable);

4908

if (h->vaddr)

4909

iounmap(h->vaddr);

4910

unregister_blkdev(h->major, h->devname);

4911

cciss_destroy_hba_sysfs_entry(h);

4912

pci_release_regions(h->pdev);

4913

kfree(h);

4914

hba[ctlr] = NULL;

4915

}

4916

4594

4917

/*

4595

4918

* This is it. Find all the controllers and register them. I really hate

4596

4919

* stealing all these major device numbers.

4601

4924

{

4602

4925

int i;

4603

4926

int j = 0;

4604

int k = 0;

4605

4927

int rc;

4928

int try_soft_reset = 0;

4606

4929

int dac, return_code;

4607

4930

InquiryData_struct *inq_buff;

4608

4931

ctlr_info_t *h;

4932

unsigned long flags;

4609

4933

4610

4934

rc = cciss_init_reset_devices(pdev);

4611

if (rc)

4612

return rc;

4935

if (rc) {

4936

if (rc != -ENOTSUPP)

4937

return rc;

4938

/* If the reset fails in a particular way (it has no way to do

4939

* a proper hard reset, so returns -ENOTSUPP) we can try to do

4940

* a soft reset once we get the controller configured up to the

4941

* point that it can accept a command.

4942

*/

4943

try_soft_reset = 1;

4944

rc = 0;

4945

}

4946

4947

reinit_after_soft_reset:

4948

4613

4949

i = alloc_cciss_hba(pdev);

4614

4950

if (i < 0)

4615

4951

return -1;

4627

4963

sprintf(h->devname, "cciss%d", i);

4628

4964

h->ctlr = i;

4629

4965

4966

if (cciss_tape_cmds < 2)

4967

cciss_tape_cmds = 2;

4968

if (cciss_tape_cmds > 16)

4969

cciss_tape_cmds = 16;

4970

4630

4971

init_completion(&h->scan_wait);

4631

4972

4632

4973

if (cciss_create_hba_sysfs_entry(h))

4662

5003

4663

5004

/* make sure the board interrupts are off */

4664

5005

h->access.set_intr_mask(h, CCISS_INTR_OFF);

4665

if (h->msi_vector || h->msix_vector) {

4666

if (request_irq(h->intr[PERF_MODE_INT],

4667

do_cciss_msix_intr,

4668

IRQF_DISABLED, h->devname, h)) {

4669

dev_err(&h->pdev->dev, "Unable to get irq %d for %s\n",

4670

h->intr[PERF_MODE_INT], h->devname);

4671

goto clean2;

4672

}

4673

} else {

4674

if (request_irq(h->intr[PERF_MODE_INT], do_cciss_intx,

4675

IRQF_DISABLED, h->devname, h)) {

4676

dev_err(&h->pdev->dev, "Unable to get irq %d for %s\n",

4677

h->intr[PERF_MODE_INT], h->devname);

4678

goto clean2;

4679

}

4680

}

5006

rc = cciss_request_irq(h, do_cciss_msix_intr, do_cciss_intx);

5007

if (rc)

5008

goto clean2;

4681

5009

4682

5010

dev_info(&h->pdev->dev, "%s: <0x%x> at PCI %s IRQ %d%s using DAC\n",

4683

5011

h->devname, pdev->device, pci_name(pdev),

4684

5012

h->intr[PERF_MODE_INT], dac ? "" : " not");

4685

5013

4686

h->cmd_pool_bits =

4687

kmalloc(DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG)

4688

* sizeof(unsigned long), GFP_KERNEL);

4689

h->cmd_pool = (CommandList_struct *)

4690

pci_alloc_consistent(h->pdev,

4691

h->nr_cmds * sizeof(CommandList_struct),

4692

&(h->cmd_pool_dhandle));

4693

h->errinfo_pool = (ErrorInfo_struct *)

4694

pci_alloc_consistent(h->pdev,

4695

h->nr_cmds * sizeof(ErrorInfo_struct),

4696

&(h->errinfo_pool_dhandle));

4697

if ((h->cmd_pool_bits == NULL)

4698

|| (h->cmd_pool == NULL)

4699

|| (h->errinfo_pool == NULL)) {

4700

dev_err(&h->pdev->dev, "out of memory");

4701

goto clean4;

4702

}

4703

4704

/* Need space for temp scatter list */

4705

h->scatter_list = kmalloc(h->max_commands *

4706

sizeof(struct scatterlist *),

4707

GFP_KERNEL);

4708

if (!h->scatter_list)

4709

goto clean4;

4710

4711

for (k = 0; k < h->nr_cmds; k++) {

4712

h->scatter_list[k] = kmalloc(sizeof(struct scatterlist) *

4713

h->maxsgentries,

4714

GFP_KERNEL);

4715

if (h->scatter_list[k] == NULL) {

4716

dev_err(&h->pdev->dev,

4717

"could not allocate s/g lists\n");

4718

goto clean4;

4719

}

4720

}

5014

if (cciss_allocate_cmd_pool(h))

5015

goto clean4;

5016

5017

if (cciss_allocate_scatterlists(h))

5018

goto clean4;

5019

4721

5020

h->cmd_sg_list = cciss_allocate_sg_chain_blocks(h,

4722

5021

h->chainsize, h->nr_cmds);

4723

5022

if (!h->cmd_sg_list && h->chainsize > 0)

4741

5040

h->gendisk[j] = NULL;

4742

5041

}

4743

5042

5043

/* At this point, the controller is ready to take commands.

5044

* Now, if reset_devices and the hard reset didn't work, try

5045

* the soft reset and see if that works.

5046

*/

5047

if (try_soft_reset) {

5048

5049

/* This is kind of gross. We may or may not get a completion

5050

* from the soft reset command, and if we do, then the value

5051

* from the fifo may or may not be valid. So, we wait 10 secs

5052

* after the reset throwing away any completions we get during

5053

* that time. Unregister the interrupt handler and register

5054

* fake ones to scoop up any residual completions.

5055

*/

5056

spin_lock_irqsave(&h->lock, flags);

5057

h->access.set_intr_mask(h, CCISS_INTR_OFF);

5058

spin_unlock_irqrestore(&h->lock, flags);

5059

free_irq(h->intr[PERF_MODE_INT], h);

5060

rc = cciss_request_irq(h, cciss_msix_discard_completions,

5061

cciss_intx_discard_completions);

5062

if (rc) {

5063

dev_warn(&h->pdev->dev, "Failed to request_irq after "

5064

"soft reset.\n");

5065

goto clean4;

5066

}

5067

5068

rc = cciss_kdump_soft_reset(h);

5069

if (rc) {

5070

dev_warn(&h->pdev->dev, "Soft reset failed.\n");

5071

goto clean4;

5072

}

5073

5074

dev_info(&h->pdev->dev, "Board READY.\n");

5075

dev_info(&h->pdev->dev,

5076

"Waiting for stale completions to drain.\n");

5077

h->access.set_intr_mask(h, CCISS_INTR_ON);

5078

msleep(10000);

5079

h->access.set_intr_mask(h, CCISS_INTR_OFF);

5080

5081

rc = controller_reset_failed(h->cfgtable);

5082

if (rc)

5083

dev_info(&h->pdev->dev,

5084

"Soft reset appears to have failed.\n");

5085

5086

/* since the controller's reset, we have to go back and re-init

5087

* everything. Easiest to just forget what we've done and do it

5088

* all over again.

5089

*/

5090

cciss_undo_allocations_after_kdump_soft_reset(h);

5091

try_soft_reset = 0;

5092

if (rc)

5093

/* don't go to clean4, we already unallocated */

5094

return -ENODEV;

5095

5096

goto reinit_after_soft_reset;

5097

}

5098

4744

5099

cciss_scsi_setup(h);

4745

5100

4746

5101

/* Turn the interrupts on so we can service requests */

4775

5130

return 1;

4776

5131

4777

5132

clean4:

4778

kfree(h->cmd_pool_bits);

4779

/* Free up sg elements */

4780

for (k-- ; k >= 0; k--)

4781

kfree(h->scatter_list[k]);

4782

kfree(h->scatter_list);

5133

cciss_free_cmd_pool(h);

5134

cciss_free_scatterlists(h);

4783

5135

cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);

4784

if (h->cmd_pool)

4785

pci_free_consistent(h->pdev,

4786

h->nr_cmds * sizeof(CommandList_struct),

4787

h->cmd_pool, h->cmd_pool_dhandle);

4788

if (h->errinfo_pool)

4789

pci_free_consistent(h->pdev,

4790

h->nr_cmds * sizeof(ErrorInfo_struct),

4791

h->errinfo_pool,

4792

h->errinfo_pool_dhandle);

4793

5136

free_irq(h->intr[PERF_MODE_INT], h);

4794

5137

clean2:

4795

5138

unregister_blkdev(h->major, h->devname);

4887

5230

iounmap(h->cfgtable);

4888

5231

iounmap(h->vaddr);

4889

5232

4890

pci_free_consistent(h->pdev, h->nr_cmds * sizeof(CommandList_struct),

4891

h->cmd_pool, h->cmd_pool_dhandle);

4892

pci_free_consistent(h->pdev, h->nr_cmds * sizeof(ErrorInfo_struct),

4893

h->errinfo_pool, h->errinfo_pool_dhandle);

4894

kfree(h->cmd_pool_bits);

5233

cciss_free_cmd_pool(h);

4895

5234

/* Free up sg elements */

4896

5235

for (j = 0; j < h->nr_cmds; j++)

4897

5236

kfree(h->scatter_list[j]);

4898

5237

kfree(h->scatter_list);

4899

5238

cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);

5239

kfree(h->blockFetchTable);

5240

if (h->reply_pool)

5241

pci_free_consistent(h->pdev, h->max_commands * sizeof(__u64),

5242

h->reply_pool, h->reply_pool_dhandle);

4900

5243

/*

4901

5244

* Deliberately omit pci_disable_device(): it does something nasty to

4902

5245

* Smart Array controllers that pci_enable_device does not undo