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Viewing changes to drivers/net/wireless/ath/ath9k/phy.h

  • Committer: Package Import Robot
  • Author(s): John Rigby, John Rigby
  • Date: 2011-09-26 10:44:23 UTC
  • Revision ID: package-import@ubuntu.com-20110926104423-3o58a3c1bj7x00rs
Tags: 3.0.0-1007.9
https://launchpad.net/bugs/826021
[ John Rigby ]

Enable crypto modules and remove crypto-modules from
exclude-module files
LP: #826021

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drivers/net/wireless/ath/ath9k/phy.h
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/*
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 * Copyright (c) 2008-2009 Atheros Communications Inc.
 
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 * Copyright (c) 2008-2011 Atheros Communications Inc.
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 *
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 * Permission to use, copy, modify, and/or distribute this software for any
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 * purpose with or without fee is hereby granted, provided that the above
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#define CHANSEL_DIV             15
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#define CHANSEL_2G(_freq)       (((_freq) * 0x10000) / CHANSEL_DIV)
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#define CHANSEL_2G_9485(_freq)  ((((_freq) * 0x10000) - 215) / CHANSEL_DIV)
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#define CHANSEL_5G(_freq)       (((_freq) * 0x8000) / CHANSEL_DIV)
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#define AR_PHY_BASE     0x9800
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#define AR_PHY_CLC_Q0        0x0000ffd0
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#define AR_PHY_CLC_Q0_S      5
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#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do {               \
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                int r;                                                  \
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                for (r = 0; r < ((iniarray)->ia_rows); r++) {           \
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                        REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
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                        DO_DELAY(regWr);                                \
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                }                                                       \
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        } while (0)
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#define ANTSWAP_AB 0x0001
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#define REDUCE_CHAIN_0 0x00000050
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#define REDUCE_CHAIN_1 0x00000051
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#define AR_PHY_CHIP_ID 0x9818
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#define RF_BANK_SETUP(_bank, _iniarray, _col) do {                      \
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                int i;                                                  \
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                for (i = 0; i < (_iniarray)->ia_rows; i++)              \
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                        (_bank)[i] = INI_RA((_iniarray), i, _col);;     \
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        } while (0)
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#define AR_PHY_TIMING11_SPUR_FREQ_SD            0x3FF00000
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#define AR_PHY_TIMING11_SPUR_FREQ_SD_S          20
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#define AR_PHY_PLL_CONTROL 0x16180
 
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#define AR_PHY_PLL_MODE 0x16184
 
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#endif