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Viewing changes to drivers/net/wireless/ath/ath9k/ar9003_phy.c

  • Committer: Package Import Robot
  • Author(s): John Rigby, John Rigby
  • Date: 2011-09-26 10:44:23 UTC
  • Revision ID: package-import@ubuntu.com-20110926104423-3o58a3c1bj7x00rs
Tags: 3.0.0-1007.9
https://launchpad.net/bugs/826021
[ John Rigby ]

Enable crypto modules and remove crypto-modules from
exclude-module files
LP: #826021

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drivers/net/wireless/ath/ath9k/ar9003_phy.c
1
1
/*
2
 
 * Copyright (c) 2010 Atheros Communications Inc.
 
2
 * Copyright (c) 2010-2011 Atheros Communications Inc.
3
3
 *
4
4
 * Permission to use, copy, modify, and/or distribute this software for any
5
5
 * purpose with or without fee is hereby granted, provided that the above
75
75
        freq = centers.synth_center;
76
76
 
77
77
        if (freq < 4800) {     /* 2 GHz, fractional mode */
78
 
                if (AR_SREV_9485(ah))
79
 
                        channelSel = CHANSEL_2G_9485(freq);
80
 
                else
 
78
                if (AR_SREV_9485(ah)) {
 
79
                        u32 chan_frac;
 
80
 
 
81
                        /*
 
82
                         * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
 
83
                         * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
 
84
                         * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
 
85
                         */
 
86
                        channelSel = (freq * 4) / 120;
 
87
                        chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
 
88
                        channelSel = (channelSel << 17) | chan_frac;
 
89
                } else if (AR_SREV_9340(ah)) {
 
90
                        if (ah->is_clk_25mhz) {
 
91
                                u32 chan_frac;
 
92
 
 
93
                                channelSel = (freq * 2) / 75;
 
94
                                chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
 
95
                                channelSel = (channelSel << 17) | chan_frac;
 
96
                        } else
 
97
                                channelSel = CHANSEL_2G(freq) >> 1;
 
98
                } else
81
99
                        channelSel = CHANSEL_2G(freq);
82
100
                /* Set to 2G mode */
83
101
                bMode = 1;
84
102
        } else {
85
 
                channelSel = CHANSEL_5G(freq);
86
 
                /* Doubler is ON, so, divide channelSel by 2. */
87
 
                channelSel >>= 1;
 
103
                if (AR_SREV_9340(ah) && ah->is_clk_25mhz) {
 
104
                        u32 chan_frac;
 
105
 
 
106
                        channelSel = (freq * 2) / 75;
 
107
                        chan_frac = ((freq % 75) * 0x20000) / 75;
 
108
                        channelSel = (channelSel << 17) | chan_frac;
 
109
                } else {
 
110
                        channelSel = CHANSEL_5G(freq);
 
111
                        /* Doubler is ON, so, divide channelSel by 2. */
 
112
                        channelSel >>= 1;
 
113
                }
88
114
                /* Set to 5G mode */
89
115
                bMode = 0;
90
116
        }
142
168
         * is out-of-band and can be ignored.
143
169
         */
144
170
 
145
 
        if (AR_SREV_9485(ah)) {
 
171
        if (AR_SREV_9485(ah) || AR_SREV_9340(ah)) {
146
172
                spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
147
173
                                                         IS_CHAN_2GHZ(chan));
148
174
                if (spur_fbin_ptr[0] == 0) /* No spur */
167
193
 
168
194
        for (i = 0; i < max_spur_cnts; i++) {
169
195
                negative = 0;
170
 
                if (AR_SREV_9485(ah))
 
196
                if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
171
197
                        cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
172
198
                                        IS_CHAN_2GHZ(chan)) - synth_freq;
173
199
                else
401
427
 
402
428
        ar9003_hw_spur_ofdm_clear(ah);
403
429
 
404
 
        for (i = 0; spurChansPtr[i] && i < 5; i++) {
 
430
        for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
405
431
                freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
406
432
                if (abs(freq_offset) < range) {
407
433
                        ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
590
616
        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
591
617
        unsigned int regWrites = 0, i;
592
618
        struct ieee80211_channel *channel = chan->chan;
593
 
        u32 modesIndex, freqIndex;
 
619
        u32 modesIndex;
594
620
 
595
621
        switch (chan->chanmode) {
596
622
        case CHANNEL_A:
597
623
        case CHANNEL_A_HT20:
598
624
                modesIndex = 1;
599
 
                freqIndex = 1;
600
625
                break;
601
626
        case CHANNEL_A_HT40PLUS:
602
627
        case CHANNEL_A_HT40MINUS:
603
628
                modesIndex = 2;
604
 
                freqIndex = 1;
605
629
                break;
606
630
        case CHANNEL_G:
607
631
        case CHANNEL_G_HT20:
608
632
        case CHANNEL_B:
609
633
                modesIndex = 4;
610
 
                freqIndex = 2;
611
634
                break;
612
635
        case CHANNEL_G_HT40PLUS:
613
636
        case CHANNEL_G_HT40MINUS:
614
637
                modesIndex = 3;
615
 
                freqIndex = 2;
616
638
                break;
617
639
 
618
640
        default:
637
659
                REG_WRITE_ARRAY(&ah->iniModesAdditional,
638
660
                                modesIndex, regWrites);
639
661
 
 
662
        if (AR_SREV_9340(ah) && !ah->is_clk_25mhz)
 
663
                REG_WRITE_ARRAY(&ah->iniModesAdditional_40M, 1, regWrites);
 
664
 
640
665
        ar9003_hw_override_ini(ah);
641
666
        ar9003_hw_set_channel_regs(ah, chan);
642
667
        ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
1159
1184
        conf->radar_inband = 8;
1160
1185
}
1161
1186
 
 
1187
static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
 
1188
                                   struct ath_hw_antcomb_conf *antconf)
 
1189
{
 
1190
        u32 regval;
 
1191
 
 
1192
        regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
 
1193
        antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
 
1194
                                  AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
 
1195
        antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
 
1196
                                 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
 
1197
        antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
 
1198
                                  AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
 
1199
        antconf->lna1_lna2_delta = -9;
 
1200
        antconf->div_group = 2;
 
1201
}
 
1202
 
 
1203
static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
 
1204
                                   struct ath_hw_antcomb_conf *antconf)
 
1205
{
 
1206
        u32 regval;
 
1207
 
 
1208
        regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
 
1209
        regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
 
1210
                    AR_PHY_9485_ANT_DIV_ALT_LNACONF |
 
1211
                    AR_PHY_9485_ANT_FAST_DIV_BIAS |
 
1212
                    AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
 
1213
                    AR_PHY_9485_ANT_DIV_ALT_GAINTB);
 
1214
        regval |= ((antconf->main_lna_conf <<
 
1215
                                        AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
 
1216
                   & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
 
1217
        regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
 
1218
                   & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
 
1219
        regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
 
1220
                   & AR_PHY_9485_ANT_FAST_DIV_BIAS);
 
1221
        regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
 
1222
                   & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
 
1223
        regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
 
1224
                   & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
 
1225
 
 
1226
        REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
 
1227
}
 
1228
 
1162
1229
void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1163
1230
{
1164
1231
        struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 
1232
        struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1165
1233
        static const u32 ar9300_cca_regs[6] = {
1166
1234
                AR_PHY_CCA_0,
1167
1235
                AR_PHY_CCA_1,
1188
1256
        priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1189
1257
        priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1190
1258
 
 
1259
        ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
 
1260
        ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
 
1261
 
1191
1262
        ar9003_hw_set_nf_limits(ah);
1192
1263
        ar9003_hw_set_radar_conf(ah);
1193
1264
        memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1310
1381
                "==== BB update: done ====\n\n");
1311
1382
}
1312
1383
EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
 
1384
 
 
1385
void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
 
1386
{
 
1387
        u32 val;
 
1388
 
 
1389
        /* While receiving unsupported rate frame rx state machine
 
1390
         * gets into a state 0xb and if phy_restart happens in that
 
1391
         * state, BB would go hang. If RXSM is in 0xb state after
 
1392
         * first bb panic, ensure to disable the phy_restart.
 
1393
         */
 
1394
        if (!((MS(ah->bb_watchdog_last_status,
 
1395
                  AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
 
1396
            ah->bb_hang_rx_ofdm))
 
1397
                return;
 
1398
 
 
1399
        ah->bb_hang_rx_ofdm = true;
 
1400
        val = REG_READ(ah, AR_PHY_RESTART);
 
1401
        val &= ~AR_PHY_RESTART_ENA;
 
1402
 
 
1403
        REG_WRITE(ah, AR_PHY_RESTART, val);
 
1404
}
 
1405
EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);