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  • Committer: Package Import Robot
  • Author(s): John Rigby, John Rigby
  • Date: 2011-09-26 10:44:23 UTC
  • Revision ID: package-import@ubuntu.com-20110926104423-3o58a3c1bj7x00rs
Tags: 3.0.0-1007.9
https://launchpad.net/bugs/826021
[ John Rigby ]

Enable crypto modules and remove crypto-modules from
exclude-module files
LP: #826021

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ubuntu/rtl8192se/rtl8192s/r8192S_rtl6052.c
1
 
/******************************************************************************
2
 
 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3
 
 *
4
 
 * This program is distributed in the hope that it will be useful, but WITHOUT
5
 
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6
 
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
7
 
 * more details.
8
 
 *
9
 
 * You should have received a copy of the GNU General Public License along with
10
 
 * this program; if not, write to the Free Software Foundation, Inc.,
11
 
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
12
 
 *
13
 
 * The full GNU General Public License is included in this distribution in the
14
 
 * file called LICENSE.
15
 
 *
16
 
 * Contact Information:
17
 
 * wlanfae <wlanfae@realtek.com>
18
 
******************************************************************************/
19
 
 
20
 
#ifdef RTL8192SE
21
 
#include "../rtl_core.h"
22
 
#include "../rtl_dm.h"
23
 
 
24
 
/*---------------------------Define Local Constant---------------------------*/
25
 
typedef struct RF_Shadow_Compare_Map {
26
 
        u32             Value;
27
 
        u8              Compare;
28
 
        u8              ErrorOrNot;
29
 
        u8              Recorver;
30
 
        u8              Driver_Write;
31
 
}RF_SHADOW_T;
32
 
/*---------------------------Define Local Constant---------------------------*/
33
 
 
34
 
 
35
 
/*------------------------Define global variable-----------------------------*/
36
 
/*------------------------Define global variable-----------------------------*/
37
 
 
38
 
 
39
 
 
40
 
 
41
 
/*---------------------Define local function prototype-----------------------*/
42
 
void phy_RF6052_Config_HardCode(struct net_device* dev);
43
 
 
44
 
bool phy_RF6052_Config_ParaFile(struct net_device* dev);
45
 
/*---------------------Define local function prototype-----------------------*/
46
 
 
47
 
/*------------------------Define function prototype--------------------------*/
48
 
extern void RF_ChangeTxPath(struct net_device* dev,  u16 DataRate);
49
 
 
50
 
/*------------------------Define function prototype--------------------------*/
51
 
 
52
 
/*------------------------Define local variable------------------------------*/
53
 
static  RF_SHADOW_T     RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
54
 
/*------------------------Define local variable------------------------------*/
55
 
 
56
 
/*------------------------Define function prototype--------------------------*/
57
 
extern void RF_ChangeTxPath(struct net_device* dev,  u16 DataRate)
58
 
{
59
 
#if 0
60
 
        static  u1Byte  RF_Path_Type = 2;       
61
 
        static  u4Byte  tx_gain_tbl1[6] 
62
 
                        = {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};
63
 
        static  u4Byte  tx_gain_tbl2[6] 
64
 
                        = {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
65
 
        u1Byte  i;
66
 
        
67
 
        if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)
68
 
        {
69
 
                PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, 
70
 
                                        RF_TXPA_G2, bMask20Bits, 0x0f000);
71
 
                PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, 
72
 
                                        RF_TXPA_G3, bMask20Bits, 0xeacf1);
73
 
 
74
 
                for (i = 0; i < 6; i++)                                 
75
 
                        PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, 
76
 
                                                RF_TX_AGC, bMask20Bits, tx_gain_tbl1[i]);
77
 
 
78
 
                PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, 
79
 
                                        RF_TXPA_G2, bMask20Bits, 0x01e39);
80
 
        }
81
 
        else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
82
 
        {
83
 
                PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, 
84
 
                                        RF_TXPA_G2, bMask20Bits, 0x04440);
85
 
                PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, 
86
 
                                        RF_TXPA_G3, bMask20Bits, 0xea4f1);
87
 
 
88
 
                for (i = 0; i < 6; i++)
89
 
                        PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, 
90
 
                                                RF_TX_AGC, bMask20Bits, tx_gain_tbl2[i]);
91
 
 
92
 
                PHY_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, 
93
 
                                        RF_TXPA_G2, bMask20Bits, 0x01e19);
94
 
        }
95
 
#endif  
96
 
        
97
 
}       /* RF_ChangeTxPath */
98
 
 
99
 
 
100
 
void PHY_RF6052SetBandwidth(struct net_device* dev, HT_CHANNEL_WIDTH Bandwidth) 
101
 
{       
102
 
        u8                              eRFPath;        
103
 
        struct r8192_priv       *priv = rtllib_priv(dev);
104
 
        
105
 
 
106
 
        if (IS_HARDWARE_TYPE_8192SE(dev))
107
 
        {               
108
 
#if (RTL92SE_FPGA_VERIFY == 0)
109
 
                switch(Bandwidth)
110
 
                {
111
 
                        case HT_CHANNEL_WIDTH_20:
112
 
#if 1
113
 
                                priv->RfRegChnlVal[0] = ((priv->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400);
114
 
                                rtl8192_phy_SetRFReg(dev, RF90_PATH_A, RF_CHNLBW, bRFRegOffsetMask, priv->RfRegChnlVal[0]);
115
 
#else
116
 
                                rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01);
117
 
#endif
118
 
                                break;
119
 
                        case HT_CHANNEL_WIDTH_20_40:
120
 
#if 1
121
 
                                priv->RfRegChnlVal[0] = ((priv->RfRegChnlVal[0] & 0xfffff3ff));
122
 
                                rtl8192_phy_SetRFReg(dev, RF90_PATH_A, RF_CHNLBW, bRFRegOffsetMask, priv->RfRegChnlVal[0]);
123
 
#else
124
 
                                rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00);
125
 
#endif
126
 
                                break;
127
 
                        default:
128
 
                                RT_TRACE(COMP_DBG, "PHY_SetRF6052Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth);
129
 
                                break;                  
130
 
                }
131
 
#endif  
132
 
        }
133
 
        else
134
 
        {
135
 
                for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
136
 
                {
137
 
                        switch(Bandwidth)
138
 
                        {
139
 
                                case HT_CHANNEL_WIDTH_20:
140
 
                                        break;
141
 
                                case HT_CHANNEL_WIDTH_20_40:
142
 
                                        break;
143
 
                                default:
144
 
                                        RT_TRACE(COMP_DBG, "PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
145
 
                                        break;
146
 
                                        
147
 
                        }
148
 
                }
149
 
        }
150
 
}
151
 
 
152
 
 
153
 
extern void PHY_RF6052SetCckTxPower(struct net_device* dev, u8  powerlevel)
154
 
{
155
 
        struct r8192_priv *priv = rtllib_priv(dev);
156
 
        u32                             TxAGC=0;
157
 
        bool                            dontIncCCKOrTurboScanOff=false;
158
 
 
159
 
        if (((priv->eeprom_version >= 2) && (priv->TxPwrSafetyFlag == 1)) ||
160
 
             ((priv->eeprom_version >= 2) && (priv->EEPROMRegulatory != 0))) {
161
 
                dontIncCCKOrTurboScanOff = true;
162
 
        }
163
 
 
164
 
        if(rtllib_act_scanning(priv->rtllib,true) == true){
165
 
                TxAGC = 0x3f;
166
 
 
167
 
                if(dontIncCCKOrTurboScanOff )
168
 
                        TxAGC = powerlevel;
169
 
        } else {
170
 
                TxAGC = powerlevel;
171
 
 
172
 
                if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
173
 
                        TxAGC = 0x10;
174
 
                else if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
175
 
                        TxAGC = 0x0;
176
 
        }
177
 
        
178
 
        if(TxAGC > RF6052_MAX_TX_PWR)
179
 
                TxAGC = RF6052_MAX_TX_PWR;
180
 
 
181
 
        rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
182
 
 
183
 
}       /* PHY_RF6052SetCckTxPower */
184
 
 
185
 
 
186
 
#if 0
187
 
extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel, u8 Channel)
188
 
{
189
 
        struct r8192_priv *priv = rtllib_priv(dev);
190
 
        u32     writeVal, powerBase0, powerBase1;
191
 
        u8      index = 0;
192
 
        u16     RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
193
 
        u8      rfa_pwr[4];
194
 
        u8      rfa_lower_bound = 0, rfa_upper_bound = 0;
195
 
        u8      i;
196
 
        u8      rf_pwr_diff = 0, chnlGroup = 0;
197
 
        u8      Legacy_pwrdiff=0, HT20_pwrdiff=0;
198
 
 
199
 
        if (priv->eeprom_version < 2)
200
 
                powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf); 
201
 
        else if (priv->eeprom_version >= 2)     
202
 
        {
203
 
                Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][Channel-1];
204
 
                powerBase0 = powerlevel + Legacy_pwrdiff; 
205
 
                RT_TRACE(COMP_POWER, " [LagacyToHT40 pwr diff = %d]\n", Legacy_pwrdiff);                
206
 
                RT_TRACE(COMP_POWER, " [OFDM power base index = 0x%x]\n", powerBase0);
207
 
        }
208
 
        powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
209
 
        
210
 
        if(priv->eeprom_version >= 2)
211
 
        {       
212
 
        
213
 
                if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
214
 
                {
215
 
                        HT20_pwrdiff = priv->TxPwrHt20Diff[RF90_PATH_A][Channel-1];
216
 
 
217
 
                        if (HT20_pwrdiff < 8)   
218
 
                                powerlevel += HT20_pwrdiff;     
219
 
                        else                            
220
 
                                powerlevel -= (16-HT20_pwrdiff);
221
 
 
222
 
                        RT_TRACE(COMP_POWER, " [HT20 to HT40 pwrdiff = %d]\n", HT20_pwrdiff);
223
 
                        RT_TRACE(COMP_POWER, " [MCS power base index = 0x%x]\n", powerlevel);
224
 
                }
225
 
        }
226
 
        powerBase1 = powerlevel;                                                        
227
 
        powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
228
 
 
229
 
        RT_TRACE(COMP_POWER, " [Legacy/HT power index= %x/%x]\n", powerBase0, powerBase1);
230
 
        
231
 
        for(index=0; index<6; index++)
232
 
        {
233
 
 
234
 
                if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
235
 
                {
236
 
                        writeVal = ((index<2)?powerBase0:powerBase1);
237
 
                }
238
 
                else
239
 
                {
240
 
                        if(priv->pwrGroupCnt == 0)
241
 
                                chnlGroup = 0;
242
 
                        if(priv->pwrGroupCnt >= 3)
243
 
                        {
244
 
                                if(Channel <= 3)
245
 
                                        chnlGroup = 0;
246
 
                                else if(Channel >= 4 && Channel <= 9)
247
 
                                        chnlGroup = 1;
248
 
                                else if(Channel >= 10)
249
 
                                        chnlGroup = 2;
250
 
                                if(priv->pwrGroupCnt == 4)
251
 
                                        chnlGroup ++;
252
 
                        }
253
 
                else
254
 
                                chnlGroup = 0;
255
 
                        writeVal = priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index] + 
256
 
                                        ((index<2)?powerBase0:powerBase1);
257
 
                }
258
 
                RT_TRACE(COMP_POWER, "Reg 0x%x, chnlGroup = %d, Original=%x writeVal=%x\n", 
259
 
                        RegOffset[index], chnlGroup, priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index], 
260
 
                        writeVal);
261
 
 
262
 
                if (priv->rf_type == RF_2T2R)
263
 
                {                       
264
 
                        rf_pwr_diff = priv->AntennaTxPwDiff[0];
265
 
                        RT_TRACE(COMP_POWER, "2T2R RF-B to RF-A PWR DIFF=%d\n", rf_pwr_diff);
266
 
 
267
 
                        if (rf_pwr_diff >= 8)           
268
 
                        {       
269
 
                                rfa_lower_bound = 0x10-rf_pwr_diff;
270
 
                                RT_TRACE(COMP_POWER, "rfa_lower_bound= %d\n", rfa_lower_bound);
271
 
                        }
272
 
                        else if (rf_pwr_diff >= 0)      
273
 
                        {
274
 
                                rfa_upper_bound = RF6052_MAX_TX_PWR-rf_pwr_diff;
275
 
                                RT_TRACE(COMP_POWER, "rfa_upper_bound= %d\n", rfa_upper_bound);
276
 
                        }                       
277
 
                }
278
 
 
279
 
                for (i=  0; i <4; i++)
280
 
                {
281
 
                        rfa_pwr[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
282
 
                        if (rfa_pwr[i]  > RF6052_MAX_TX_PWR)
283
 
                                rfa_pwr[i]  = RF6052_MAX_TX_PWR;
284
 
 
285
 
                        if (priv->rf_type == RF_2T2R)
286
 
                        {
287
 
                                if (rf_pwr_diff >= 8)           
288
 
                                {       
289
 
                                        if (rfa_pwr[i] <rfa_lower_bound)
290
 
                                        {
291
 
                                                RT_TRACE(COMP_POWER, "Underflow");
292
 
                                                rfa_pwr[i] = rfa_lower_bound;
293
 
                                        }
294
 
                                }
295
 
                                else if (rf_pwr_diff >= 1)      
296
 
                                {       
297
 
                                        if (rfa_pwr[i] > rfa_upper_bound)
298
 
                                        {
299
 
                                                RT_TRACE(COMP_POWER, "Overflow");
300
 
                                                rfa_pwr[i] = rfa_upper_bound;
301
 
                                        }
302
 
                                }
303
 
                                RT_TRACE(COMP_POWER, "rfa_pwr[%d]=%x\n", i, rfa_pwr[i]);
304
 
                        }
305
 
 
306
 
                }
307
 
 
308
 
#if 1
309
 
                writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0];
310
 
                RT_TRACE(COMP_POWER, "WritePower=%08x\n", writeVal);
311
 
#else
312
 
                if(priv->bDynamicTxHighPower == true)     
313
 
                {       
314
 
                        if(index > 1)   
315
 
                        {
316
 
                                writeVal = 0x03030303;
317
 
                        }
318
 
                        else
319
 
                        {
320
 
                                writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0];
321
 
                        }
322
 
                        RT_TRACE(COMP_POWER, "HighPower=%08x\n", writeVal);
323
 
                }
324
 
                else
325
 
                {
326
 
                        writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0];
327
 
                        RT_TRACE(COMP_POWER, "NormalPower=%08x\n", writeVal);
328
 
                }
329
 
#endif
330
 
                rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
331
 
        }
332
 
 
333
 
}       /* PHY_RF6052SetOFDMTxPower */
334
 
#endif
335
 
 
336
 
void getPowerBase(
337
 
        struct net_device* dev,
338
 
        u8*             pPowerLevel,
339
 
        u8              Channel,
340
 
        u32*    OfdmBase,
341
 
        u32*    MCSBase,
342
 
        u8*             pFinalPowerIndex
343
 
        )
344
 
{
345
 
        struct r8192_priv *priv = rtllib_priv(dev);
346
 
        u32                     powerBase0, powerBase1;
347
 
        u8                      Legacy_pwrdiff=0, HT20_pwrdiff=0;
348
 
        u8                      i, powerlevel[4];
349
 
        
350
 
        for(i=0; i<2; i++)
351
 
                powerlevel[i] = pPowerLevel[i];
352
 
        if (priv->eeprom_version < 2)
353
 
                powerBase0 = powerlevel[0] + (priv->LegacyHTTxPowerDiff & 0xf); 
354
 
        else if (priv->eeprom_version >= 2)
355
 
        {
356
 
                Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][Channel-1];
357
 
                powerBase0 = powerlevel[0] + Legacy_pwrdiff; 
358
 
        }
359
 
        powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
360
 
        *OfdmBase = powerBase0;
361
 
        RT_TRACE(COMP_POWER, " [OFDM power base index = 0x%x]\n", powerBase0);
362
 
        
363
 
        if(priv->eeprom_version >= 2)
364
 
        {
365
 
                if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
366
 
                {
367
 
                        for(i=0; i<2; i++)      
368
 
                        {       
369
 
                                HT20_pwrdiff = priv->TxPwrHt20Diff[i][Channel-1];
370
 
                                if (HT20_pwrdiff < 8)   
371
 
                                        powerlevel[i] += HT20_pwrdiff;  
372
 
                                else                            
373
 
                                        powerlevel[i] -= (16-HT20_pwrdiff);
374
 
                        }
375
 
                }
376
 
        }
377
 
        powerBase1 = powerlevel[0];     
378
 
        powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
379
 
        *MCSBase = powerBase1;
380
 
        
381
 
        RT_TRACE(COMP_POWER, " [MCS power base index = 0x%x]\n", powerBase1);
382
 
 
383
 
        pFinalPowerIndex[0] = powerlevel[0];
384
 
        pFinalPowerIndex[1] = powerlevel[1];
385
 
        switch(priv->EEPROMRegulatory)
386
 
        {
387
 
                case 3:
388
 
                        if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
389
 
                        {
390
 
                                pFinalPowerIndex[0] += priv->PwrGroupHT40[RF90_PATH_A][Channel-1];
391
 
                                pFinalPowerIndex[1] += priv->PwrGroupHT40[RF90_PATH_B][Channel-1];
392
 
                        }
393
 
                        else
394
 
                        {
395
 
                                pFinalPowerIndex[0] += priv->PwrGroupHT20[RF90_PATH_A][Channel-1];
396
 
                                pFinalPowerIndex[1] += priv->PwrGroupHT20[RF90_PATH_B][Channel-1];
397
 
                        }
398
 
                        break;
399
 
                default:
400
 
                        break;
401
 
        }
402
 
        if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
403
 
        {
404
 
                RT_TRACE(COMP_POWER, "40MHz finalPowerIndex (A / B) = 0x%x / 0x%x\n", 
405
 
                        pFinalPowerIndex[0], pFinalPowerIndex[1]);
406
 
        }
407
 
        else
408
 
        {
409
 
                RT_TRACE(COMP_POWER, "20MHz finalPowerIndex (A / B) = 0x%x / 0x%x\n", 
410
 
                        pFinalPowerIndex[0], pFinalPowerIndex[1]);
411
 
        }
412
 
}
413
 
 
414
 
void getTxPowerWriteValByRegulatory(
415
 
        struct net_device* dev,
416
 
        u8              Channel,
417
 
        u8              index,
418
 
        u32             powerBase0,
419
 
        u32             powerBase1,
420
 
        u32*    pOutWriteVal
421
 
        )
422
 
{
423
 
        struct r8192_priv *priv = rtllib_priv(dev);
424
 
        u8              i, chnlGroup, pwr_diff_limit[4];
425
 
        u32             writeVal, customer_limit;
426
 
        
427
 
        switch(priv->EEPROMRegulatory)
428
 
        {
429
 
                case 0: 
430
 
                        chnlGroup = 0;
431
 
                        RT_TRACE(COMP_POWER,"MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", 
432
 
                                chnlGroup, index, priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index]);
433
 
                        writeVal = priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index] + 
434
 
                                ((index<2)?powerBase0:powerBase1);
435
 
                        RT_TRACE(COMP_POWER,"RTK better performance, writeVal = 0x%x\n", writeVal);
436
 
                        break;
437
 
                case 1: 
438
 
                        if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
439
 
                        {
440
 
                                writeVal = ((index<2)?powerBase0:powerBase1);
441
 
                                RT_TRACE(COMP_POWER,"Realtek regulatory, 40MHz, writeVal = 0x%x\n", writeVal);
442
 
                        }
443
 
                        else
444
 
                        {
445
 
                                if(priv->pwrGroupCnt == 1)
446
 
                                        chnlGroup = 0;
447
 
                                if(priv->pwrGroupCnt >= 3)
448
 
                                {
449
 
                                        if(Channel <= 3)
450
 
                                                chnlGroup = 0;
451
 
                                        else if(Channel >= 4 && Channel <= 8)
452
 
                                                chnlGroup = 1;
453
 
                                        else if(Channel > 8)
454
 
                                                chnlGroup = 2;
455
 
                                        if(priv->pwrGroupCnt == 4)
456
 
                                                chnlGroup++;
457
 
                                }
458
 
                                RT_TRACE(COMP_POWER,"MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", 
459
 
                                chnlGroup, index, priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index]);
460
 
                                writeVal = priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index] + 
461
 
                                                ((index<2)?powerBase0:powerBase1);
462
 
                                RT_TRACE(COMP_POWER,"Realtek regulatory, 20MHz, writeVal = 0x%x\n", writeVal);
463
 
                        }
464
 
                        break;
465
 
                case 2: 
466
 
                        writeVal = ((index<2)?powerBase0:powerBase1);
467
 
                        RT_TRACE(COMP_POWER,"Better regulatory, writeVal = 0x%x\n", writeVal);
468
 
                        break;
469
 
                case 3: 
470
 
                        chnlGroup = 0;
471
 
                        RT_TRACE(COMP_POWER,"MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", 
472
 
                                chnlGroup, index, priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index]);
473
 
 
474
 
                        if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
475
 
                        {
476
 
                                RT_TRACE(COMP_POWER,"customer's limit, 40MHz = 0x%x\n", 
477
 
                                        priv->PwrGroupHT40[RF90_PATH_A][Channel-1]);
478
 
                        }
479
 
                        else
480
 
                        {
481
 
                                RT_TRACE(COMP_POWER,"customer's limit, 20MHz = 0x%x\n", 
482
 
                                        priv->PwrGroupHT20[RF90_PATH_A][Channel-1]);
483
 
                        }
484
 
                        for (i=0; i<4; i++)
485
 
                        {
486
 
                                pwr_diff_limit[i] = (u8)((priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index]&(0x7f<<(i*8)))>>(i*8));
487
 
                                if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
488
 
                                {
489
 
                                        if(pwr_diff_limit[i] > priv->PwrGroupHT40[RF90_PATH_A][Channel-1])
490
 
                                        {
491
 
                                                pwr_diff_limit[i] = priv->PwrGroupHT40[RF90_PATH_A][Channel-1];
492
 
                                        }
493
 
                                }
494
 
                                else
495
 
                                {
496
 
                                        if(pwr_diff_limit[i] > priv->PwrGroupHT20[RF90_PATH_A][Channel-1])
497
 
                                        {
498
 
                                                pwr_diff_limit[i] = priv->PwrGroupHT20[RF90_PATH_A][Channel-1];
499
 
                                        }
500
 
                                }
501
 
                        }
502
 
                        customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
503
 
                                                        (pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
504
 
                        RT_TRACE(COMP_POWER,"Customer's limit = 0x%x\n", customer_limit);
505
 
 
506
 
                        writeVal = customer_limit + ((index<2)?powerBase0:powerBase1);
507
 
                        RT_TRACE(COMP_POWER,"Customer, writeVal = 0x%x\n", writeVal);
508
 
                        break;
509
 
                default:
510
 
                        chnlGroup = 0;
511
 
                        writeVal = priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index] + 
512
 
                                ((index<2)?powerBase0:powerBase1);
513
 
                        RT_TRACE(COMP_POWER,"RTK better performance, writeVal = 0x%x\n", writeVal);
514
 
                        break;
515
 
        }
516
 
 
517
 
        if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
518
 
                writeVal = 0x10101010;
519
 
        else if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
520
 
                writeVal = 0x0;
521
 
 
522
 
        *pOutWriteVal = writeVal;
523
 
 
524
 
}
525
 
 
526
 
void setAntennaDiff(
527
 
        struct net_device* dev,
528
 
        u8*             pFinalPowerIndex
529
 
        )
530
 
{
531
 
        struct r8192_priv *priv = rtllib_priv(dev);
532
 
        char    ant_pwr_diff=0;
533
 
        u32     u4RegValue=0;
534
 
 
535
 
        if (priv->rf_type == RF_2T2R)
536
 
        {
537
 
                ant_pwr_diff = pFinalPowerIndex[1] - pFinalPowerIndex[0];
538
 
                
539
 
                if(ant_pwr_diff > 7)
540
 
                        ant_pwr_diff = 7;
541
 
                if(ant_pwr_diff < -8)
542
 
                        ant_pwr_diff = -8;
543
 
                RT_TRACE(COMP_POWER,"Antenna Diff from RF-B to RF-A = %d (0x%x)\n", 
544
 
                        ant_pwr_diff, ant_pwr_diff&0xf);
545
 
                ant_pwr_diff &= 0xf;
546
 
        }
547
 
        priv->AntennaTxPwDiff[2] = 0;
548
 
        priv->AntennaTxPwDiff[1] = 0;
549
 
        priv->AntennaTxPwDiff[0] = (u8)(ant_pwr_diff);          
550
 
 
551
 
        u4RegValue = (priv->AntennaTxPwDiff[2]<<8 | 
552
 
                                priv->AntennaTxPwDiff[1]<<4 | 
553
 
                                priv->AntennaTxPwDiff[0]        );
554
 
 
555
 
        rtl8192_setBBreg(dev, rFPGA0_TxGainStage, 
556
 
                (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
557
 
 
558
 
        RT_TRACE(COMP_POWER,"Write BCD-Diff(0x%x) = 0x%x\n", 
559
 
                rFPGA0_TxGainStage, u4RegValue);
560
 
}
561
 
 
562
 
void writeOFDMPowerReg(
563
 
        struct net_device* dev,
564
 
        u8              index,
565
 
        u32             Value
566
 
        )
567
 
{
568
 
        struct r8192_priv *priv = rtllib_priv(dev);
569
 
        u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
570
 
        u8 i, rfa_pwr[4];
571
 
        u8 rfa_lower_bound = 0, rfa_upper_bound = 0, rf_pwr_diff = 0;
572
 
        u32 writeVal=Value;
573
 
        if (priv->rf_type == RF_2T2R)
574
 
        {                       
575
 
                rf_pwr_diff = priv->AntennaTxPwDiff[0];
576
 
 
577
 
                if (rf_pwr_diff >= 8)           
578
 
                {       
579
 
                        rfa_lower_bound = 0x10-rf_pwr_diff;
580
 
                        RT_TRACE(COMP_POWER,"rfa_lower_bound= %d\n", rfa_lower_bound);
581
 
                }
582
 
                else
583
 
                {
584
 
                        rfa_upper_bound = RF6052_MAX_TX_PWR-rf_pwr_diff;
585
 
                        RT_TRACE(COMP_POWER,"rfa_upper_bound= %d\n", rfa_upper_bound);
586
 
                }                       
587
 
        }
588
 
 
589
 
        for (i=0; i<4; i++)
590
 
        {
591
 
                rfa_pwr[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
592
 
                if (rfa_pwr[i]  > RF6052_MAX_TX_PWR)
593
 
                        rfa_pwr[i]  = RF6052_MAX_TX_PWR;
594
 
 
595
 
                if (priv->rf_type == RF_2T2R)
596
 
                {
597
 
                        if (rf_pwr_diff >= 8)           
598
 
                        {       
599
 
                                if (rfa_pwr[i] <rfa_lower_bound)
600
 
                                {
601
 
                                        RT_TRACE(COMP_POWER,"Underflow");
602
 
                                        rfa_pwr[i] = rfa_lower_bound;
603
 
                                }
604
 
                        }
605
 
                        else if (rf_pwr_diff >= 1)      
606
 
                        {       
607
 
                                if (rfa_pwr[i] > rfa_upper_bound)
608
 
                                {
609
 
                                        RT_TRACE(COMP_POWER,"Overflow");
610
 
                                        rfa_pwr[i] = rfa_upper_bound;
611
 
                                }
612
 
                        }
613
 
                        RT_TRACE(COMP_POWER,"rfa_pwr[%d]=%x\n", i, rfa_pwr[i]);
614
 
                }
615
 
 
616
 
        }
617
 
 
618
 
        writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0];
619
 
 
620
 
        rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
621
 
        RT_TRACE(COMP_POWER,"Set 0x%x = %08x\n",RegOffset[index], writeVal);
622
 
}
623
 
 
624
 
/*-----------------------------------------------------------------------------
625
 
 * Function:    PHY_RF6052SetOFDMTxPower
626
 
 *
627
 
 * Overview:    For legacy and HY OFDM, we must read EEPROM TX power index for 
628
 
 *                      different channel and read original value in TX power register area from
629
 
 *                      0xe00. We increase offset and original value to be correct tx pwr.
630
 
 *
631
 
 * Input:       NONE
632
 
 *
633
 
 * Output:      NONE
634
 
 *
635
 
 * Return:      NONE
636
 
 *
637
 
 * Revised History:
638
 
 * When                 Who             Remark
639
 
 * 11/05/2008   MHC             Simulate 8192 series method.
640
 
 * 01/06/2009   MHC             1. Prevent Path B tx power overflow or underflow dure to
641
 
 *                                              A/B pwr difference or legacy/HT pwr diff.
642
 
 *                                              2. We concern with path B legacy/HT OFDM difference.
643
 
 * 01/22/2009   MHC             Support new EPRO format from SD3.
644
 
 *
645
 
 *---------------------------------------------------------------------------*/
646
 
extern  void 
647
 
PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8* pPowerLevel, u8 Channel)
648
 
{
649
 
        u32 writeVal, powerBase0, powerBase1;
650
 
        u8 index = 0;
651
 
        u8 finalPowerIndex[4];
652
 
 
653
 
        getPowerBase(dev, pPowerLevel, Channel, &powerBase0, &powerBase1, &finalPowerIndex[0]);
654
 
        setAntennaDiff(dev, &finalPowerIndex[0] );
655
 
        
656
 
        for(index=0; index<6; index++)
657
 
        {
658
 
                getTxPowerWriteValByRegulatory(dev, Channel, index, 
659
 
                        powerBase0, powerBase1, &writeVal);
660
 
 
661
 
                writeOFDMPowerReg(dev, index, writeVal);
662
 
        }
663
 
}
664
 
 
665
 
bool PHY_RF6052_Config(struct net_device* dev)
666
 
{
667
 
        struct r8192_priv                       *priv = rtllib_priv(dev);
668
 
        bool rtStatus = true;   
669
 
        u8 bRegHwParaFile = 1;
670
 
        
671
 
        if(priv->rf_type == RF_1T1R)
672
 
                priv->NumTotalRFPath = 1;
673
 
        else
674
 
        priv->NumTotalRFPath = 2;
675
 
 
676
 
        switch(bRegHwParaFile)
677
 
        {
678
 
                case 0:
679
 
                        phy_RF6052_Config_HardCode(dev);
680
 
                        break;
681
 
 
682
 
                case 1:
683
 
                        rtStatus = phy_RF6052_Config_ParaFile(dev);
684
 
                        break;
685
 
 
686
 
                case 2:
687
 
                        phy_RF6052_Config_HardCode(dev);
688
 
                        phy_RF6052_Config_ParaFile(dev);
689
 
                        break;
690
 
 
691
 
                default:
692
 
                        phy_RF6052_Config_HardCode(dev);
693
 
                        break;
694
 
        }
695
 
        return rtStatus;
696
 
                
697
 
}
698
 
 
699
 
void phy_RF6052_Config_HardCode(struct net_device* dev)
700
 
{
701
 
        
702
 
 
703
 
        
704
 
}
705
 
 
706
 
bool phy_RF6052_Config_ParaFile(struct net_device* dev)
707
 
{
708
 
        u32                     u4RegValue = 0;
709
 
        u8                      eRFPath;
710
 
        bool rtStatus = true;
711
 
        struct r8192_priv       *priv = rtllib_priv(dev);
712
 
        BB_REGISTER_DEFINITION_T        *pPhyReg;       
713
 
 
714
 
 
715
 
        for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
716
 
        {
717
 
 
718
 
                pPhyReg = &priv->PHYRegDef[eRFPath];
719
 
                
720
 
                switch(eRFPath)
721
 
                {
722
 
                case RF90_PATH_A:
723
 
                case RF90_PATH_C:
724
 
                        u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
725
 
                        break;
726
 
                case RF90_PATH_B :
727
 
                case RF90_PATH_D:
728
 
                        u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
729
 
                        break;
730
 
                }
731
 
 
732
 
                rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
733
 
                
734
 
                rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
735
 
 
736
 
                rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);  
737
 
                rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);     
738
 
 
739
 
 
740
 
                switch(eRFPath)
741
 
                {
742
 
                case RF90_PATH_A:
743
 
#if     RTL8190_Download_Firmware_From_Header
744
 
                        rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
745
 
#else
746
 
                        rtStatus = PHY_ConfigRFWithParaFile(dev, (char* )&szRadioAFile, (RF90_RADIO_PATH_E)eRFPath);
747
 
#endif
748
 
                        break;
749
 
                case RF90_PATH_B:
750
 
#if     RTL8190_Download_Firmware_From_Header
751
 
                        rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
752
 
#else
753
 
                        if(priv->rf_type == RF_2T2R_GREEN)
754
 
                                rtStatus = PHY_ConfigRFWithParaFile(dev, (char *)&szRadioBGMFile, (RF90_RADIO_PATH_E)eRFPath);
755
 
                        else
756
 
                                rtStatus = PHY_ConfigRFWithParaFile(dev, (char* )&szRadioBFile, (RF90_RADIO_PATH_E)eRFPath);
757
 
#endif
758
 
                        break;
759
 
                case RF90_PATH_C:
760
 
                        break;
761
 
                case RF90_PATH_D:
762
 
                        break;
763
 
                }
764
 
 
765
 
                switch(eRFPath)
766
 
                {
767
 
                case RF90_PATH_A:
768
 
                case RF90_PATH_C:
769
 
                        rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
770
 
                        break;
771
 
                case RF90_PATH_B :
772
 
                case RF90_PATH_D:
773
 
                        rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
774
 
                        break;
775
 
                }
776
 
 
777
 
                if(rtStatus != true){
778
 
                        printk("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
779
 
                        goto phy_RF6052_Config_ParaFile_Fail;
780
 
                }
781
 
 
782
 
        }
783
 
 
784
 
        RT_TRACE(COMP_INIT, "<---phy_RF6052_Config_ParaFile()\n");
785
 
        return rtStatus;
786
 
        
787
 
phy_RF6052_Config_ParaFile_Fail:        
788
 
        return rtStatus;
789
 
}
790
 
 
791
 
 
792
 
extern u32 PHY_RFShadowRead(
793
 
        struct net_device               * dev,
794
 
        RF90_RADIO_PATH_E       eRFPath,
795
 
        u32                                     Offset)
796
 
{
797
 
        return  RF_Shadow[eRFPath][Offset].Value;
798
 
        
799
 
}       /* PHY_RFShadowRead */
800
 
 
801
 
 
802
 
extern void PHY_RFShadowWrite(
803
 
        struct net_device               * dev,
804
 
        RF90_RADIO_PATH_E       eRFPath,
805
 
        u32                                     Offset,
806
 
        u32                                     Data)
807
 
{
808
 
        RF_Shadow[eRFPath][Offset].Value = (Data & bMask20Bits);
809
 
        RF_Shadow[eRFPath][Offset].Driver_Write = true;
810
 
        
811
 
}       /* PHY_RFShadowWrite */
812
 
 
813
 
 
814
 
extern bool PHY_RFShadowCompare(
815
 
        struct net_device               * dev,
816
 
        RF90_RADIO_PATH_E       eRFPath,
817
 
        u32                                     Offset)
818
 
{
819
 
        u32     reg;
820
 
        
821
 
        if (RF_Shadow[eRFPath][Offset].Compare == true)
822
 
        {
823
 
                reg = rtl8192_phy_QueryRFReg(dev, eRFPath, Offset, bMask20Bits);
824
 
                if (RF_Shadow[eRFPath][Offset].Value != reg)
825
 
                {
826
 
                        RF_Shadow[eRFPath][Offset].ErrorOrNot = true;
827
 
                        RT_TRACE(COMP_INIT, "PHY_RFShadowCompare RF-%d Addr%02xErr = %05x", eRFPath, Offset, reg);
828
 
                }
829
 
                else
830
 
                {
831
 
                        RT_TRACE(COMP_INIT, "PHY_RFShadowCompare RF-%d Addr%02x Err = %05x return false\n", eRFPath, Offset, reg);
832
 
                        RF_Shadow[eRFPath][Offset].ErrorOrNot = false;
833
 
                }
834
 
                return RF_Shadow[eRFPath][Offset].ErrorOrNot;
835
 
        }
836
 
        return false;
837
 
}       /* PHY_RFShadowCompare */
838
 
 
839
 
extern void PHY_RFShadowRecorver(
840
 
        struct net_device               * dev,
841
 
        RF90_RADIO_PATH_E       eRFPath,
842
 
        u32                                     Offset)
843
 
{
844
 
        if (RF_Shadow[eRFPath][Offset].ErrorOrNot == true)
845
 
        {
846
 
                if (RF_Shadow[eRFPath][Offset].Recorver == true)
847
 
                {
848
 
                        rtl8192_phy_SetRFReg(dev, eRFPath, Offset, bMask20Bits, RF_Shadow[eRFPath][Offset].Value);
849
 
                        RT_TRACE(COMP_INIT, "PHY_RFShadowRecorver RF-%d Addr%02x=%05x", 
850
 
                        eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value);
851
 
                }
852
 
        }
853
 
        
854
 
}       /* PHY_RFShadowRecorver */
855
 
 
856
 
 
857
 
extern void PHY_RFShadowCompareAll(struct net_device * dev)
858
 
{
859
 
        u32             eRFPath;
860
 
        u32             Offset;
861
 
 
862
 
        for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
863
 
        {
864
 
                for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
865
 
                {
866
 
                        PHY_RFShadowCompare(dev, (RF90_RADIO_PATH_E)eRFPath, Offset);
867
 
                }
868
 
        }
869
 
        
870
 
}       /* PHY_RFShadowCompareAll */
871
 
 
872
 
 
873
 
extern void PHY_RFShadowRecorverAll(struct net_device * dev)
874
 
{
875
 
        u32             eRFPath;
876
 
        u32             Offset;
877
 
 
878
 
        for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
879
 
        {
880
 
                for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
881
 
                {
882
 
                        PHY_RFShadowRecorver(dev, (RF90_RADIO_PATH_E)eRFPath, Offset);
883
 
                }
884
 
        }
885
 
        
886
 
}       /* PHY_RFShadowRecorverAll */
887
 
 
888
 
 
889
 
extern void PHY_RFShadowCompareFlagSet(
890
 
        struct net_device               * dev,
891
 
        RF90_RADIO_PATH_E       eRFPath,
892
 
        u32                                     Offset,
893
 
        u8                                      Type)
894
 
{
895
 
        RF_Shadow[eRFPath][Offset].Compare = Type;
896
 
                
897
 
}       /* PHY_RFShadowCompareFlagSet */
898
 
 
899
 
 
900
 
extern void PHY_RFShadowRecorverFlagSet(
901
 
        struct net_device               * dev,
902
 
        RF90_RADIO_PATH_E       eRFPath,
903
 
        u32                                     Offset,
904
 
        u8                                      Type)
905
 
{
906
 
        RF_Shadow[eRFPath][Offset].Recorver= Type;
907
 
                
908
 
}       /* PHY_RFShadowRecorverFlagSet */
909
 
 
910
 
 
911
 
extern void PHY_RFShadowCompareFlagSetAll(struct net_device  * dev)
912
 
{
913
 
        u32             eRFPath;
914
 
        u32             Offset;
915
 
 
916
 
        for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
917
 
        {
918
 
                for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
919
 
                {
920
 
                        if (Offset != 0x26 && Offset != 0x27)
921
 
                                PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, false);
922
 
                        else
923
 
                                PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, true);
924
 
                }
925
 
        }
926
 
                
927
 
}       /* PHY_RFShadowCompareFlagSetAll */
928
 
 
929
 
 
930
 
extern void PHY_RFShadowRecorverFlagSetAll(struct net_device  * dev)
931
 
{
932
 
        u32             eRFPath;
933
 
        u32             Offset;
934
 
 
935
 
        for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
936
 
        {
937
 
                for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
938
 
                {
939
 
                        if (Offset != 0x26 && Offset != 0x27)
940
 
                                PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, false);
941
 
                        else
942
 
                                PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, true);
943
 
                }
944
 
        }
945
 
                
946
 
}       /* PHY_RFShadowCompareFlagSetAll */
947
 
 
948
 
 
949
 
 
950
 
extern void PHY_RFShadowRefresh(struct net_device  * dev)
951
 
{
952
 
        u32             eRFPath;
953
 
        u32             Offset;
954
 
 
955
 
        for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
956
 
        {
957
 
                for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
958
 
                {
959
 
                        RF_Shadow[eRFPath][Offset].Value = 0;
960
 
                        RF_Shadow[eRFPath][Offset].Compare = false;
961
 
                        RF_Shadow[eRFPath][Offset].Recorver  = false;
962
 
                        RF_Shadow[eRFPath][Offset].ErrorOrNot = false;
963
 
                        RF_Shadow[eRFPath][Offset].Driver_Write = false;
964
 
                }
965
 
        }
966
 
        
967
 
}       /* PHY_RFShadowRead */
968
 
 
969
 
/* End of HalRf6052.c */
970
 
 
971
 
#endif