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Viewing changes to arch/mips/include/asm/mach-au1x00/au1000.h

  • Committer: Package Import Robot
  • Author(s): John Rigby, John Rigby
  • Date: 2011-09-26 10:44:23 UTC
  • Revision ID: package-import@ubuntu.com-20110926104423-3o58a3c1bj7x00rs
Tags: 3.0.0-1007.9
https://launchpad.net/bugs/826021
[ John Rigby ]

Enable crypto modules and remove crypto-modules from
exclude-module files
LP: #826021

Show diffs side-by-side

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Lines of Context:
arch/mips/include/asm/mach-au1x00/au1000.h
161
161
        return ALCHEMY_CPU_UNKNOWN;
162
162
}
163
163
 
 
164
/* return number of uarts on a given cputype */
 
165
static inline int alchemy_get_uarts(int type)
 
166
{
 
167
        switch (type) {
 
168
        case ALCHEMY_CPU_AU1000:
 
169
                return 4;
 
170
        case ALCHEMY_CPU_AU1500:
 
171
        case ALCHEMY_CPU_AU1200:
 
172
                return 2;
 
173
        case ALCHEMY_CPU_AU1100:
 
174
        case ALCHEMY_CPU_AU1550:
 
175
                return 3;
 
176
        }
 
177
        return 0;
 
178
}
 
179
 
 
180
/* enable an UART block if it isn't already */
 
181
static inline void alchemy_uart_enable(u32 uart_phys)
 
182
{
 
183
        void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
 
184
 
 
185
        /* reset, enable clock, deassert reset */
 
186
        if ((__raw_readl(addr + 0x100) & 3) != 3) {
 
187
                __raw_writel(0, addr + 0x100);
 
188
                wmb();
 
189
                __raw_writel(1, addr + 0x100);
 
190
                wmb();
 
191
        }
 
192
        __raw_writel(3, addr + 0x100);
 
193
        wmb();
 
194
}
 
195
 
 
196
static inline void alchemy_uart_disable(u32 uart_phys)
 
197
{
 
198
        void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
 
199
        __raw_writel(0, addr + 0x100);  /* UART_MOD_CNTRL */
 
200
        wmb();
 
201
}
 
202
 
164
203
static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
165
204
{
166
205
        void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
180
219
        wmb();
181
220
}
182
221
 
 
222
/* return number of ethernet MACs on a given cputype */
 
223
static inline int alchemy_get_macs(int type)
 
224
{
 
225
        switch (type) {
 
226
        case ALCHEMY_CPU_AU1000:
 
227
        case ALCHEMY_CPU_AU1500:
 
228
        case ALCHEMY_CPU_AU1550:
 
229
                return 2;
 
230
        case ALCHEMY_CPU_AU1100:
 
231
                return 1;
 
232
        }
 
233
        return 0;
 
234
}
 
235
 
183
236
/* arch/mips/au1000/common/clocks.c */
184
237
extern void set_au1x00_speed(unsigned int new_freq);
185
238
extern unsigned int get_au1x00_speed(void);
630
683
 
631
684
/*
632
685
 * Physical base addresses for integrated peripherals
 
686
 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
633
687
 */
634
688
 
 
689
#define AU1000_AC97_PHYS_ADDR           0x10000000 /* 012 */
 
690
#define AU1000_USBD_PHYS_ADDR           0x10200000 /* 0123 */
 
691
#define AU1000_IC0_PHYS_ADDR            0x10400000 /* 01234 */
 
692
#define AU1000_MAC0_PHYS_ADDR           0x10500000 /* 023 */
 
693
#define AU1000_MAC1_PHYS_ADDR           0x10510000 /* 023 */
 
694
#define AU1000_MACEN_PHYS_ADDR          0x10520000 /* 023 */
 
695
#define AU1100_SD0_PHYS_ADDR            0x10600000 /* 24 */
 
696
#define AU1100_SD1_PHYS_ADDR            0x10680000 /* 24 */
 
697
#define AU1000_I2S_PHYS_ADDR            0x11000000 /* 02 */
 
698
#define AU1500_MAC0_PHYS_ADDR           0x11500000 /* 1 */
 
699
#define AU1500_MAC1_PHYS_ADDR           0x11510000 /* 1 */
 
700
#define AU1500_MACEN_PHYS_ADDR          0x11520000 /* 1 */
 
701
#define AU1000_UART0_PHYS_ADDR          0x11100000 /* 01234 */
 
702
#define AU1000_UART1_PHYS_ADDR          0x11200000 /* 0234 */
 
703
#define AU1000_UART2_PHYS_ADDR          0x11300000 /* 0 */
 
704
#define AU1000_UART3_PHYS_ADDR          0x11400000 /* 0123 */
 
705
#define AU1500_GPIO2_PHYS_ADDR          0x11700000 /* 1234 */
 
706
#define AU1000_IC1_PHYS_ADDR            0x11800000 /* 01234 */
 
707
#define AU1000_SYS_PHYS_ADDR            0x11900000 /* 01234 */
 
708
#define AU1000_DMA_PHYS_ADDR            0x14002000 /* 012 */
 
709
#define AU1550_DBDMA_PHYS_ADDR          0x14002000 /* 34 */
 
710
#define AU1550_DBDMA_CONF_PHYS_ADDR     0x14003000 /* 34 */
 
711
#define AU1000_MACDMA0_PHYS_ADDR        0x14004000 /* 0123 */
 
712
#define AU1000_MACDMA1_PHYS_ADDR        0x14004200 /* 0123 */
 
713
 
 
714
 
635
715
#ifdef CONFIG_SOC_AU1000
636
716
#define MEM_PHYS_ADDR           0x14000000
637
717
#define STATIC_MEM_PHYS_ADDR    0x14001000
638
 
#define DMA0_PHYS_ADDR          0x14002000
639
 
#define DMA1_PHYS_ADDR          0x14002100
640
 
#define DMA2_PHYS_ADDR          0x14002200
641
 
#define DMA3_PHYS_ADDR          0x14002300
642
 
#define DMA4_PHYS_ADDR          0x14002400
643
 
#define DMA5_PHYS_ADDR          0x14002500
644
 
#define DMA6_PHYS_ADDR          0x14002600
645
 
#define DMA7_PHYS_ADDR          0x14002700
646
 
#define IC0_PHYS_ADDR           0x10400000
647
 
#define IC1_PHYS_ADDR           0x11800000
648
 
#define AC97_PHYS_ADDR          0x10000000
649
718
#define USBH_PHYS_ADDR          0x10100000
650
 
#define USBD_PHYS_ADDR          0x10200000
651
719
#define IRDA_PHYS_ADDR          0x10300000
652
 
#define MAC0_PHYS_ADDR          0x10500000
653
 
#define MAC1_PHYS_ADDR          0x10510000
654
 
#define MACEN_PHYS_ADDR         0x10520000
655
 
#define MACDMA0_PHYS_ADDR       0x14004000
656
 
#define MACDMA1_PHYS_ADDR       0x14004200
657
 
#define I2S_PHYS_ADDR           0x11000000
658
 
#define UART0_PHYS_ADDR         0x11100000
659
 
#define UART1_PHYS_ADDR         0x11200000
660
 
#define UART2_PHYS_ADDR         0x11300000
661
 
#define UART3_PHYS_ADDR         0x11400000
662
720
#define SSI0_PHYS_ADDR          0x11600000
663
721
#define SSI1_PHYS_ADDR          0x11680000
664
 
#define SYS_PHYS_ADDR           0x11900000
665
722
#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
666
723
#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
667
724
#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
672
729
#ifdef CONFIG_SOC_AU1500
673
730
#define MEM_PHYS_ADDR           0x14000000
674
731
#define STATIC_MEM_PHYS_ADDR    0x14001000
675
 
#define DMA0_PHYS_ADDR          0x14002000
676
 
#define DMA1_PHYS_ADDR          0x14002100
677
 
#define DMA2_PHYS_ADDR          0x14002200
678
 
#define DMA3_PHYS_ADDR          0x14002300
679
 
#define DMA4_PHYS_ADDR          0x14002400
680
 
#define DMA5_PHYS_ADDR          0x14002500
681
 
#define DMA6_PHYS_ADDR          0x14002600
682
 
#define DMA7_PHYS_ADDR          0x14002700
683
 
#define IC0_PHYS_ADDR           0x10400000
684
 
#define IC1_PHYS_ADDR           0x11800000
685
 
#define AC97_PHYS_ADDR          0x10000000
686
732
#define USBH_PHYS_ADDR          0x10100000
687
 
#define USBD_PHYS_ADDR          0x10200000
688
733
#define PCI_PHYS_ADDR           0x14005000
689
 
#define MAC0_PHYS_ADDR          0x11500000
690
 
#define MAC1_PHYS_ADDR          0x11510000
691
 
#define MACEN_PHYS_ADDR         0x11520000
692
 
#define MACDMA0_PHYS_ADDR       0x14004000
693
 
#define MACDMA1_PHYS_ADDR       0x14004200
694
 
#define I2S_PHYS_ADDR           0x11000000
695
 
#define UART0_PHYS_ADDR         0x11100000
696
 
#define UART3_PHYS_ADDR         0x11400000
697
 
#define GPIO2_PHYS_ADDR         0x11700000
698
 
#define SYS_PHYS_ADDR           0x11900000
699
734
#define PCI_MEM_PHYS_ADDR       0x400000000ULL
700
735
#define PCI_IO_PHYS_ADDR        0x500000000ULL
701
736
#define PCI_CONFIG0_PHYS_ADDR   0x600000000ULL
710
745
#ifdef CONFIG_SOC_AU1100
711
746
#define MEM_PHYS_ADDR           0x14000000
712
747
#define STATIC_MEM_PHYS_ADDR    0x14001000
713
 
#define DMA0_PHYS_ADDR          0x14002000
714
 
#define DMA1_PHYS_ADDR          0x14002100
715
 
#define DMA2_PHYS_ADDR          0x14002200
716
 
#define DMA3_PHYS_ADDR          0x14002300
717
 
#define DMA4_PHYS_ADDR          0x14002400
718
 
#define DMA5_PHYS_ADDR          0x14002500
719
 
#define DMA6_PHYS_ADDR          0x14002600
720
 
#define DMA7_PHYS_ADDR          0x14002700
721
 
#define IC0_PHYS_ADDR           0x10400000
722
 
#define SD0_PHYS_ADDR           0x10600000
723
 
#define SD1_PHYS_ADDR           0x10680000
724
 
#define IC1_PHYS_ADDR           0x11800000
725
 
#define AC97_PHYS_ADDR          0x10000000
726
748
#define USBH_PHYS_ADDR          0x10100000
727
 
#define USBD_PHYS_ADDR          0x10200000
728
749
#define IRDA_PHYS_ADDR          0x10300000
729
 
#define MAC0_PHYS_ADDR          0x10500000
730
 
#define MACEN_PHYS_ADDR         0x10520000
731
 
#define MACDMA0_PHYS_ADDR       0x14004000
732
 
#define MACDMA1_PHYS_ADDR       0x14004200
733
 
#define I2S_PHYS_ADDR           0x11000000
734
 
#define UART0_PHYS_ADDR         0x11100000
735
 
#define UART1_PHYS_ADDR         0x11200000
736
 
#define UART3_PHYS_ADDR         0x11400000
737
750
#define SSI0_PHYS_ADDR          0x11600000
738
751
#define SSI1_PHYS_ADDR          0x11680000
739
 
#define GPIO2_PHYS_ADDR         0x11700000
740
 
#define SYS_PHYS_ADDR           0x11900000
741
752
#define LCD_PHYS_ADDR           0x15000000
742
753
#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
743
754
#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
749
760
#ifdef CONFIG_SOC_AU1550
750
761
#define MEM_PHYS_ADDR           0x14000000
751
762
#define STATIC_MEM_PHYS_ADDR    0x14001000
752
 
#define IC0_PHYS_ADDR           0x10400000
753
 
#define IC1_PHYS_ADDR           0x11800000
754
763
#define USBH_PHYS_ADDR          0x14020000
755
 
#define USBD_PHYS_ADDR          0x10200000
756
764
#define PCI_PHYS_ADDR           0x14005000
757
 
#define MAC0_PHYS_ADDR          0x10500000
758
 
#define MAC1_PHYS_ADDR          0x10510000
759
 
#define MACEN_PHYS_ADDR         0x10520000
760
 
#define MACDMA0_PHYS_ADDR       0x14004000
761
 
#define MACDMA1_PHYS_ADDR       0x14004200
762
 
#define UART0_PHYS_ADDR         0x11100000
763
 
#define UART1_PHYS_ADDR         0x11200000
764
 
#define UART3_PHYS_ADDR         0x11400000
765
 
#define GPIO2_PHYS_ADDR         0x11700000
766
 
#define SYS_PHYS_ADDR           0x11900000
767
 
#define DDMA_PHYS_ADDR          0x14002000
768
765
#define PE_PHYS_ADDR            0x14008000
769
766
#define PSC0_PHYS_ADDR          0x11A00000
770
767
#define PSC1_PHYS_ADDR          0x11B00000
786
783
#define STATIC_MEM_PHYS_ADDR    0x14001000
787
784
#define AES_PHYS_ADDR           0x10300000
788
785
#define CIM_PHYS_ADDR           0x14004000
789
 
#define IC0_PHYS_ADDR           0x10400000
790
 
#define IC1_PHYS_ADDR           0x11800000
791
786
#define USBM_PHYS_ADDR          0x14020000
792
787
#define USBH_PHYS_ADDR          0x14020100
793
 
#define UART0_PHYS_ADDR         0x11100000
794
 
#define UART1_PHYS_ADDR         0x11200000
795
 
#define GPIO2_PHYS_ADDR         0x11700000
796
 
#define SYS_PHYS_ADDR           0x11900000
797
 
#define DDMA_PHYS_ADDR          0x14002000
798
788
#define PSC0_PHYS_ADDR          0x11A00000
799
789
#define PSC1_PHYS_ADDR          0x11B00000
800
 
#define SD0_PHYS_ADDR           0x10600000
801
 
#define SD1_PHYS_ADDR           0x10680000
802
790
#define LCD_PHYS_ADDR           0x15000000
803
791
#define SWCNT_PHYS_ADDR         0x1110010C
804
792
#define MAEFE_PHYS_ADDR         0x14012000
835
823
#endif
836
824
 
837
825
 
838
 
/* Interrupt Controller register offsets */
839
 
#define IC_CFG0RD               0x40
840
 
#define IC_CFG0SET              0x40
841
 
#define IC_CFG0CLR              0x44
842
 
#define IC_CFG1RD               0x48
843
 
#define IC_CFG1SET              0x48
844
 
#define IC_CFG1CLR              0x4C
845
 
#define IC_CFG2RD               0x50
846
 
#define IC_CFG2SET              0x50
847
 
#define IC_CFG2CLR              0x54
848
 
#define IC_REQ0INT              0x54
849
 
#define IC_SRCRD                0x58
850
 
#define IC_SRCSET               0x58
851
 
#define IC_SRCCLR               0x5C
852
 
#define IC_REQ1INT              0x5C
853
 
#define IC_ASSIGNRD             0x60
854
 
#define IC_ASSIGNSET            0x60
855
 
#define IC_ASSIGNCLR            0x64
856
 
#define IC_WAKERD               0x68
857
 
#define IC_WAKESET              0x68
858
 
#define IC_WAKECLR              0x6C
859
 
#define IC_MASKRD               0x70
860
 
#define IC_MASKSET              0x70
861
 
#define IC_MASKCLR              0x74
862
 
#define IC_RISINGRD             0x78
863
 
#define IC_RISINGCLR            0x78
864
 
#define IC_FALLINGRD            0x7C
865
 
#define IC_FALLINGCLR           0x7C
866
 
#define IC_TESTBIT              0x80
867
 
 
868
 
 
869
 
/* Interrupt Controller 0 */
870
 
#define IC0_CFG0RD              0xB0400040
871
 
#define IC0_CFG0SET             0xB0400040
872
 
#define IC0_CFG0CLR             0xB0400044
873
 
 
874
 
#define IC0_CFG1RD              0xB0400048
875
 
#define IC0_CFG1SET             0xB0400048
876
 
#define IC0_CFG1CLR             0xB040004C
877
 
 
878
 
#define IC0_CFG2RD              0xB0400050
879
 
#define IC0_CFG2SET             0xB0400050
880
 
#define IC0_CFG2CLR             0xB0400054
881
 
 
882
 
#define IC0_REQ0INT             0xB0400054
883
 
#define IC0_SRCRD               0xB0400058
884
 
#define IC0_SRCSET              0xB0400058
885
 
#define IC0_SRCCLR              0xB040005C
886
 
#define IC0_REQ1INT             0xB040005C
887
 
 
888
 
#define IC0_ASSIGNRD            0xB0400060
889
 
#define IC0_ASSIGNSET           0xB0400060
890
 
#define IC0_ASSIGNCLR           0xB0400064
891
 
 
892
 
#define IC0_WAKERD              0xB0400068
893
 
#define IC0_WAKESET             0xB0400068
894
 
#define IC0_WAKECLR             0xB040006C
895
 
 
896
 
#define IC0_MASKRD              0xB0400070
897
 
#define IC0_MASKSET             0xB0400070
898
 
#define IC0_MASKCLR             0xB0400074
899
 
 
900
 
#define IC0_RISINGRD            0xB0400078
901
 
#define IC0_RISINGCLR           0xB0400078
902
 
#define IC0_FALLINGRD           0xB040007C
903
 
#define IC0_FALLINGCLR          0xB040007C
904
 
 
905
 
#define IC0_TESTBIT             0xB0400080
906
 
 
907
 
/* Interrupt Controller 1 */
908
 
#define IC1_CFG0RD              0xB1800040
909
 
#define IC1_CFG0SET             0xB1800040
910
 
#define IC1_CFG0CLR             0xB1800044
911
 
 
912
 
#define IC1_CFG1RD              0xB1800048
913
 
#define IC1_CFG1SET             0xB1800048
914
 
#define IC1_CFG1CLR             0xB180004C
915
 
 
916
 
#define IC1_CFG2RD              0xB1800050
917
 
#define IC1_CFG2SET             0xB1800050
918
 
#define IC1_CFG2CLR             0xB1800054
919
 
 
920
 
#define IC1_REQ0INT             0xB1800054
921
 
#define IC1_SRCRD               0xB1800058
922
 
#define IC1_SRCSET              0xB1800058
923
 
#define IC1_SRCCLR              0xB180005C
924
 
#define IC1_REQ1INT             0xB180005C
925
 
 
926
 
#define IC1_ASSIGNRD            0xB1800060
927
 
#define IC1_ASSIGNSET           0xB1800060
928
 
#define IC1_ASSIGNCLR           0xB1800064
929
 
 
930
 
#define IC1_WAKERD              0xB1800068
931
 
#define IC1_WAKESET             0xB1800068
932
 
#define IC1_WAKECLR             0xB180006C
933
 
 
934
 
#define IC1_MASKRD              0xB1800070
935
 
#define IC1_MASKSET             0xB1800070
936
 
#define IC1_MASKCLR             0xB1800074
937
 
 
938
 
#define IC1_RISINGRD            0xB1800078
939
 
#define IC1_RISINGCLR           0xB1800078
940
 
#define IC1_FALLINGRD           0xB180007C
941
 
#define IC1_FALLINGCLR          0xB180007C
942
 
 
943
 
#define IC1_TESTBIT             0xB1800080
944
826
 
945
827
 
946
828
/* Au1000 */
947
829
#ifdef CONFIG_SOC_AU1000
948
830
 
949
 
#define UART0_ADDR              0xB1100000
950
 
#define UART3_ADDR              0xB1400000
951
 
 
952
831
#define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
953
832
#define USB_HOST_CONFIG         0xB017FFFC
954
833
#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
955
 
 
956
 
#define AU1000_ETH0_BASE        0xB0500000
957
 
#define AU1000_ETH1_BASE        0xB0510000
958
 
#define AU1000_MAC0_ENABLE      0xB0520000
959
 
#define AU1000_MAC1_ENABLE      0xB0520004
960
 
#define NUM_ETH_INTERFACES 2
961
834
#endif /* CONFIG_SOC_AU1000 */
962
835
 
963
836
/* Au1500 */
964
837
#ifdef CONFIG_SOC_AU1500
965
838
 
966
 
#define UART0_ADDR              0xB1100000
967
 
#define UART3_ADDR              0xB1400000
968
 
 
969
839
#define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
970
840
#define USB_HOST_CONFIG         0xB017fffc
971
841
#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
972
 
 
973
 
#define AU1500_ETH0_BASE        0xB1500000
974
 
#define AU1500_ETH1_BASE        0xB1510000
975
 
#define AU1500_MAC0_ENABLE      0xB1520000
976
 
#define AU1500_MAC1_ENABLE      0xB1520004
977
 
#define NUM_ETH_INTERFACES 2
978
842
#endif /* CONFIG_SOC_AU1500 */
979
843
 
980
844
/* Au1100 */
981
845
#ifdef CONFIG_SOC_AU1100
982
846
 
983
 
#define UART0_ADDR              0xB1100000
984
 
#define UART3_ADDR              0xB1400000
985
 
 
986
847
#define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
987
848
#define USB_HOST_CONFIG         0xB017FFFC
988
849
#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
989
 
 
990
 
#define AU1100_ETH0_BASE        0xB0500000
991
 
#define AU1100_MAC0_ENABLE      0xB0520000
992
 
#define NUM_ETH_INTERFACES 1
993
850
#endif /* CONFIG_SOC_AU1100 */
994
851
 
995
852
#ifdef CONFIG_SOC_AU1550
996
 
#define UART0_ADDR              0xB1100000
997
853
 
998
854
#define USB_OHCI_BASE           0x14020000      /* phys addr for ioremap */
999
855
#define USB_OHCI_LEN            0x00060000
1000
856
#define USB_HOST_CONFIG         0xB4027ffc
1001
857
#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
1002
 
 
1003
 
#define AU1550_ETH0_BASE        0xB0500000
1004
 
#define AU1550_ETH1_BASE        0xB0510000
1005
 
#define AU1550_MAC0_ENABLE      0xB0520000
1006
 
#define AU1550_MAC1_ENABLE      0xB0520004
1007
 
#define NUM_ETH_INTERFACES 2
1008
858
#endif /* CONFIG_SOC_AU1550 */
1009
859
 
1010
860
 
1011
861
#ifdef CONFIG_SOC_AU1200
1012
862
 
1013
 
#define UART0_ADDR              0xB1100000
1014
 
 
1015
863
#define USB_UOC_BASE            0x14020020
1016
864
#define USB_UOC_LEN             0x20
1017
865
#define USB_OHCI_BASE           0x14020100
1504
1352
#define SYS_PINFUNC_S1B         (1 << 2)
1505
1353
#endif
1506
1354
 
1507
 
#define SYS_TRIOUTRD            0xB1900100
1508
 
#define SYS_TRIOUTCLR           0xB1900100
1509
 
#define SYS_OUTPUTRD            0xB1900108
1510
 
#define SYS_OUTPUTSET           0xB1900108
1511
 
#define SYS_OUTPUTCLR           0xB190010C
1512
 
#define SYS_PINSTATERD          0xB1900110
1513
 
#define SYS_PININPUTEN          0xB1900110
1514
 
 
1515
 
/* GPIO2, Au1500, Au1550 only */
1516
 
#define GPIO2_BASE              0xB1700000
1517
 
#define GPIO2_DIR               (GPIO2_BASE + 0)
1518
 
#define GPIO2_OUTPUT            (GPIO2_BASE + 8)
1519
 
#define GPIO2_PINSTATE          (GPIO2_BASE + 0xC)
1520
 
#define GPIO2_INTENABLE         (GPIO2_BASE + 0x10)
1521
 
#define GPIO2_ENABLE            (GPIO2_BASE + 0x14)
1522
 
 
1523
1355
/* Power Management */
1524
1356
#define SYS_SCRATCH0            0xB1900018
1525
1357
#define SYS_SCRATCH1            0xB190001C
1635
1467
#  define AC97C_RS              (1 << 1)
1636
1468
#  define AC97C_CE              (1 << 0)
1637
1469
 
1638
 
/* Secure Digital (SD) Controller */
1639
 
#define SD0_XMIT_FIFO   0xB0600000
1640
 
#define SD0_RECV_FIFO   0xB0600004
1641
 
#define SD1_XMIT_FIFO   0xB0680000
1642
 
#define SD1_RECV_FIFO   0xB0680004
1643
 
 
1644
1470
#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1645
1471
/* Au1500 PCI Controller */
1646
1472
#define Au1500_CFG_BASE         0xB4005000      /* virtual, KSEG1 addr */