2
* (C) 2001-2004 Dave Jones. <davej@redhat.com>
3
* (C) 2002 Padraig Brady. <padraig@antefacto.com>
5
* Licensed under the terms of the GNU GPL License version 2.
6
* Based upon datasheets & sample CPUs kindly provided by VIA.
8
* VIA have currently 3 different versions of Longhaul.
9
* Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
10
* It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
11
* Version 2 of longhaul is backward compatible with v1, but adds
12
* LONGHAUL MSR for purpose of both frequency and voltage scaling.
13
* Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
14
* Version 3 of longhaul got renamed to Powersaver and redesigned
15
* to use only the POWERSAVER MSR at 0x110a.
16
* It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
17
* It's pretty much the same feature wise to longhaul v2, though
18
* there is provision for scaling FSB too, but this doesn't work
19
* too well in practice so we don't even try to use this.
21
* BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
24
#include <linux/kernel.h>
25
#include <linux/module.h>
26
#include <linux/moduleparam.h>
27
#include <linux/init.h>
28
#include <linux/cpufreq.h>
29
#include <linux/pci.h>
30
#include <linux/slab.h>
31
#include <linux/string.h>
32
#include <linux/delay.h>
33
#include <linux/timex.h>
35
#include <linux/acpi.h>
38
#include <acpi/processor.h>
42
#define PFX "longhaul: "
44
#define TYPE_LONGHAUL_V1 1
45
#define TYPE_LONGHAUL_V2 2
46
#define TYPE_POWERSAVER 3
52
#define CPU_NEHEMIAH 5
53
#define CPU_NEHEMIAH_C 6
56
#define USE_ACPI_C3 (1 << 1)
57
#define USE_NORTHBRIDGE (1 << 2)
60
static unsigned int numscales = 16;
61
static unsigned int fsb;
63
static const struct mV_pos *vrm_mV_table;
64
static const unsigned char *mV_vrm_table;
66
static unsigned int highest_speed, lowest_speed; /* kHz */
67
static unsigned int minmult, maxmult;
68
static int can_scale_voltage;
69
static struct acpi_processor *pr;
70
static struct acpi_processor_cx *cx;
71
static u32 acpi_regs_addr;
72
static u8 longhaul_flags;
73
static unsigned int longhaul_index;
75
/* Module parameters */
76
static int scale_voltage;
77
static int disable_acpi_c3;
78
static int revid_errata;
81
/* Clock ratios multiplied by 10 */
84
static int longhaul_version;
85
static struct cpufreq_frequency_table *longhaul_table;
87
static char speedbuffer[8];
89
static char *print_speed(int speed)
92
snprintf(speedbuffer, sizeof(speedbuffer), "%dMHz", speed);
97
snprintf(speedbuffer, sizeof(speedbuffer),
100
snprintf(speedbuffer, sizeof(speedbuffer),
101
"%d.%dGHz", speed/1000, (speed%1000)/100);
107
static unsigned int calc_speed(int mult)
118
static int longhaul_get_cpu_mult(void)
120
unsigned long invalue = 0, lo, hi;
122
rdmsr(MSR_IA32_EBL_CR_POWERON, lo, hi);
123
invalue = (lo & (1<<22|1<<23|1<<24|1<<25))>>22;
124
if (longhaul_version == TYPE_LONGHAUL_V2 ||
125
longhaul_version == TYPE_POWERSAVER) {
129
return eblcr[invalue];
132
/* For processor with BCR2 MSR */
134
static void do_longhaul1(unsigned int mults_index)
138
rdmsrl(MSR_VIA_BCR2, bcr2.val);
139
/* Enable software clock multiplier */
140
bcr2.bits.ESOFTBF = 1;
141
bcr2.bits.CLOCKMUL = mults_index & 0xff;
143
/* Sync to timer tick */
145
/* Change frequency on next halt or sleep */
146
wrmsrl(MSR_VIA_BCR2, bcr2.val);
147
/* Invoke transition */
148
ACPI_FLUSH_CPU_CACHE();
151
/* Disable software clock multiplier */
153
rdmsrl(MSR_VIA_BCR2, bcr2.val);
154
bcr2.bits.ESOFTBF = 0;
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wrmsrl(MSR_VIA_BCR2, bcr2.val);
158
/* For processor with Longhaul MSR */
160
static void do_powersaver(int cx_address, unsigned int mults_index,
163
union msr_longhaul longhaul;
166
rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
167
/* Setup new frequency */
169
longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
171
longhaul.bits.RevisionKey = 0;
172
longhaul.bits.SoftBusRatio = mults_index & 0xf;
173
longhaul.bits.SoftBusRatio4 = (mults_index & 0x10) >> 4;
174
/* Setup new voltage */
175
if (can_scale_voltage)
176
longhaul.bits.SoftVID = (mults_index >> 8) & 0x1f;
177
/* Sync to timer tick */
179
/* Raise voltage if necessary */
180
if (can_scale_voltage && dir) {
181
longhaul.bits.EnableSoftVID = 1;
182
wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
185
ACPI_FLUSH_CPU_CACHE();
188
ACPI_FLUSH_CPU_CACHE();
191
/* Dummy op - must do something useless after P_LVL3
193
t = inl(acpi_gbl_FADT.xpm_timer_block.address);
195
longhaul.bits.EnableSoftVID = 0;
196
wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
199
/* Change frequency on next halt or sleep */
200
longhaul.bits.EnableSoftBusRatio = 1;
201
wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
203
ACPI_FLUSH_CPU_CACHE();
206
ACPI_FLUSH_CPU_CACHE();
209
/* Dummy op - must do something useless after P_LVL3 read */
210
t = inl(acpi_gbl_FADT.xpm_timer_block.address);
212
/* Disable bus ratio bit */
213
longhaul.bits.EnableSoftBusRatio = 0;
214
wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
216
/* Reduce voltage if necessary */
217
if (can_scale_voltage && !dir) {
218
longhaul.bits.EnableSoftVID = 1;
219
wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
222
ACPI_FLUSH_CPU_CACHE();
225
ACPI_FLUSH_CPU_CACHE();
228
/* Dummy op - must do something useless after P_LVL3
230
t = inl(acpi_gbl_FADT.xpm_timer_block.address);
232
longhaul.bits.EnableSoftVID = 0;
233
wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
238
* longhaul_set_cpu_frequency()
239
* @mults_index : bitpattern of the new multiplier.
241
* Sets a new clock ratio.
244
static void longhaul_setstate(unsigned int table_index)
246
unsigned int mults_index;
248
struct cpufreq_freqs freqs;
250
unsigned int pic1_mask, pic2_mask;
252
u32 bm_timeout = 1000;
253
unsigned int dir = 0;
255
mults_index = longhaul_table[table_index].index;
256
/* Safety precautions */
257
mult = mults[mults_index & 0x1f];
260
speed = calc_speed(mult);
261
if ((speed > highest_speed) || (speed < lowest_speed))
263
/* Voltage transition before frequency transition? */
264
if (can_scale_voltage && longhaul_index < table_index)
267
freqs.old = calc_speed(longhaul_get_cpu_mult());
269
freqs.cpu = 0; /* longhaul.c is UP only driver */
271
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
273
pr_debug("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
274
fsb, mult/10, mult%10, print_speed(speed/1000));
277
local_irq_save(flags);
279
pic2_mask = inb(0xA1);
280
pic1_mask = inb(0x21); /* works on C3. save mask. */
281
outb(0xFF, 0xA1); /* Overkill */
282
outb(0xFE, 0x21); /* TMR0 only */
284
/* Wait while PCI bus is busy. */
285
if (acpi_regs_addr && (longhaul_flags & USE_NORTHBRIDGE
286
|| ((pr != NULL) && pr->flags.bm_control))) {
287
bm_status = inw(acpi_regs_addr);
289
while (bm_status && bm_timeout) {
290
outw(1 << 4, acpi_regs_addr);
292
bm_status = inw(acpi_regs_addr);
297
if (longhaul_flags & USE_NORTHBRIDGE) {
298
/* Disable AGP and PCI arbiters */
300
} else if ((pr != NULL) && pr->flags.bm_control) {
301
/* Disable bus master arbitration */
302
acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1);
304
switch (longhaul_version) {
307
* Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
308
* Software controlled multipliers only.
310
case TYPE_LONGHAUL_V1:
311
do_longhaul1(mults_index);
315
* Longhaul v2 appears in Samuel2 Steppings 1->7 [C5B] and Ezra [C5C]
317
* Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
318
* Nehemiah can do FSB scaling too, but this has never been proven
319
* to work in practice.
321
case TYPE_LONGHAUL_V2:
322
case TYPE_POWERSAVER:
323
if (longhaul_flags & USE_ACPI_C3) {
324
/* Don't allow wakeup */
325
acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
326
do_powersaver(cx->address, mults_index, dir);
328
do_powersaver(0, mults_index, dir);
333
if (longhaul_flags & USE_NORTHBRIDGE) {
334
/* Enable arbiters */
336
} else if ((pr != NULL) && pr->flags.bm_control) {
337
/* Enable bus master arbitration */
338
acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0);
340
outb(pic2_mask, 0xA1); /* restore mask */
341
outb(pic1_mask, 0x21);
343
local_irq_restore(flags);
346
freqs.new = calc_speed(longhaul_get_cpu_mult());
347
/* Check if requested frequency is set. */
348
if (unlikely(freqs.new != speed)) {
349
printk(KERN_INFO PFX "Failed to set requested frequency!\n");
350
/* Revision ID = 1 but processor is expecting revision key
351
* equal to 0. Jumpers at the bottom of processor will change
352
* multiplier and FSB, but will not change bits in Longhaul
353
* MSR nor enable voltage scaling. */
355
printk(KERN_INFO PFX "Enabling \"Ignore Revision ID\" "
361
/* Why ACPI C3 sometimes doesn't work is a mystery for me.
362
* But it does happen. Processor is entering ACPI C3 state,
363
* but it doesn't change frequency. I tried poking various
364
* bits in northbridge registers, but without success. */
365
if (longhaul_flags & USE_ACPI_C3) {
366
printk(KERN_INFO PFX "Disabling ACPI C3 support.\n");
367
longhaul_flags &= ~USE_ACPI_C3;
369
printk(KERN_INFO PFX "Disabling \"Ignore "
370
"Revision ID\" option.\n");
376
/* This shouldn't happen. Longhaul ver. 2 was reported not
377
* working on processors without voltage scaling, but with
378
* RevID = 1. RevID errata will make things right. Just
379
* to be 100% sure. */
380
if (longhaul_version == TYPE_LONGHAUL_V2) {
381
printk(KERN_INFO PFX "Switching to Longhaul ver. 1\n");
382
longhaul_version = TYPE_LONGHAUL_V1;
387
/* Report true CPU frequency */
388
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
391
printk(KERN_INFO PFX "Warning: Timeout while waiting for "
396
* Centaur decided to make life a little more tricky.
397
* Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
398
* Samuel2 and above have to try and guess what the FSB is.
399
* We do this by assuming we booted at maximum multiplier, and interpolate
400
* between that value multiplied by possible FSBs and cpu_mhz which
401
* was calculated at boot time. Really ugly, but no other way to do this.
406
static int guess_fsb(int mult)
408
int speed = cpu_khz / 1000;
410
int speeds[] = { 666, 1000, 1333, 2000 };
413
for (i = 0; i < 4; i++) {
414
f_max = ((speeds[i] * mult) + 50) / 100;
415
f_max += (ROUNDING / 2);
416
f_min = f_max - ROUNDING;
417
if ((speed <= f_max) && (speed >= f_min))
418
return speeds[i] / 10;
424
static int __cpuinit longhaul_get_ranges(void)
426
unsigned int i, j, k = 0;
430
/* Get current frequency */
431
mult = longhaul_get_cpu_mult();
433
printk(KERN_INFO PFX "Invalid (reserved) multiplier!\n");
436
fsb = guess_fsb(mult);
438
printk(KERN_INFO PFX "Invalid (reserved) FSB!\n");
441
/* Get max multiplier - as we always did.
442
* Longhaul MSR is useful only when voltage scaling is enabled.
443
* C3 is booting at max anyway. */
445
/* Get min multiplier */
458
pr_debug("MinMult:%d.%dx MaxMult:%d.%dx\n",
459
minmult/10, minmult%10, maxmult/10, maxmult%10);
461
highest_speed = calc_speed(maxmult);
462
lowest_speed = calc_speed(minmult);
463
pr_debug("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb,
464
print_speed(lowest_speed/1000),
465
print_speed(highest_speed/1000));
467
if (lowest_speed == highest_speed) {
468
printk(KERN_INFO PFX "highestspeed == lowest, aborting.\n");
471
if (lowest_speed > highest_speed) {
472
printk(KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
473
lowest_speed, highest_speed);
477
longhaul_table = kmalloc((numscales + 1) * sizeof(*longhaul_table),
482
for (j = 0; j < numscales; j++) {
486
if (ratio > maxmult || ratio < minmult)
488
longhaul_table[k].frequency = calc_speed(ratio);
489
longhaul_table[k].index = j;
493
kfree(longhaul_table);
497
for (j = 0; j < k - 1; j++) {
498
unsigned int min_f, min_i;
499
min_f = longhaul_table[j].frequency;
501
for (i = j + 1; i < k; i++) {
502
if (longhaul_table[i].frequency < min_f) {
503
min_f = longhaul_table[i].frequency;
508
swap(longhaul_table[j].frequency,
509
longhaul_table[min_i].frequency);
510
swap(longhaul_table[j].index,
511
longhaul_table[min_i].index);
515
longhaul_table[k].frequency = CPUFREQ_TABLE_END;
517
/* Find index we are running on */
518
for (j = 0; j < k; j++) {
519
if (mults[longhaul_table[j].index & 0x1f] == mult) {
528
static void __cpuinit longhaul_setup_voltagescaling(void)
530
union msr_longhaul longhaul;
531
struct mV_pos minvid, maxvid, vid;
532
unsigned int j, speed, pos, kHz_step, numvscales;
535
rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
536
if (!(longhaul.bits.RevisionID & 1)) {
537
printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
541
if (!longhaul.bits.VRMRev) {
542
printk(KERN_INFO PFX "VRM 8.5\n");
543
vrm_mV_table = &vrm85_mV[0];
544
mV_vrm_table = &mV_vrm85[0];
546
printk(KERN_INFO PFX "Mobile VRM\n");
547
if (cpu_model < CPU_NEHEMIAH)
549
vrm_mV_table = &mobilevrm_mV[0];
550
mV_vrm_table = &mV_mobilevrm[0];
553
minvid = vrm_mV_table[longhaul.bits.MinimumVID];
554
maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
556
if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
557
printk(KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
558
"Voltage scaling disabled.\n",
559
minvid.mV/1000, minvid.mV%1000,
560
maxvid.mV/1000, maxvid.mV%1000);
564
if (minvid.mV == maxvid.mV) {
565
printk(KERN_INFO PFX "Claims to support voltage scaling but "
566
"min & max are both %d.%03d. "
567
"Voltage scaling disabled\n",
568
maxvid.mV/1000, maxvid.mV%1000);
572
/* How many voltage steps*/
573
numvscales = maxvid.pos - minvid.pos + 1;
577
"%d possible voltage scales\n",
578
maxvid.mV/1000, maxvid.mV%1000,
579
minvid.mV/1000, minvid.mV%1000,
582
/* Calculate max frequency at min voltage */
583
j = longhaul.bits.MinMHzBR;
584
if (longhaul.bits.MinMHzBR4)
586
min_vid_speed = eblcr[j];
587
if (min_vid_speed == -1)
589
switch (longhaul.bits.MinMHzFSB) {
591
min_vid_speed *= 13333;
594
min_vid_speed *= 10000;
597
min_vid_speed *= 6666;
603
if (min_vid_speed >= highest_speed)
605
/* Calculate kHz for one voltage step */
606
kHz_step = (highest_speed - min_vid_speed) / numvscales;
609
while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
610
speed = longhaul_table[j].frequency;
611
if (speed > min_vid_speed)
612
pos = (speed - min_vid_speed) / kHz_step + minvid.pos;
615
longhaul_table[j].index |= mV_vrm_table[pos] << 8;
616
vid = vrm_mV_table[mV_vrm_table[pos]];
617
printk(KERN_INFO PFX "f: %d kHz, index: %d, vid: %d mV\n",
622
can_scale_voltage = 1;
623
printk(KERN_INFO PFX "Voltage scaling enabled.\n");
627
static int longhaul_verify(struct cpufreq_policy *policy)
629
return cpufreq_frequency_table_verify(policy, longhaul_table);
633
static int longhaul_target(struct cpufreq_policy *policy,
634
unsigned int target_freq, unsigned int relation)
636
unsigned int table_index = 0;
638
unsigned int dir = 0;
641
if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq,
642
relation, &table_index))
645
/* Don't set same frequency again */
646
if (longhaul_index == table_index)
649
if (!can_scale_voltage)
650
longhaul_setstate(table_index);
652
/* On test system voltage transitions exceeding single
653
* step up or down were turning motherboard off. Both
654
* "ondemand" and "userspace" are unsafe. C7 is doing
655
* this in hardware, C3 is old and we need to do this
658
current_vid = (longhaul_table[longhaul_index].index >> 8);
660
if (table_index > longhaul_index)
662
while (i != table_index) {
663
vid = (longhaul_table[i].index >> 8) & 0x1f;
664
if (vid != current_vid) {
665
longhaul_setstate(i);
674
longhaul_setstate(table_index);
676
longhaul_index = table_index;
681
static unsigned int longhaul_get(unsigned int cpu)
685
return calc_speed(longhaul_get_cpu_mult());
688
static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
690
void *context, void **return_value)
692
struct acpi_device *d;
694
if (acpi_bus_get_device(obj_handle, &d))
697
*return_value = acpi_driver_data(d);
701
/* VIA don't support PM2 reg, but have something similar */
702
static int enable_arbiter_disable(void)
709
/* Find PLE133 host bridge */
711
dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0,
713
/* Find PM133/VT8605 host bridge */
715
dev = pci_get_device(PCI_VENDOR_ID_VIA,
716
PCI_DEVICE_ID_VIA_8605_0, NULL);
717
/* Find CLE266 host bridge */
720
dev = pci_get_device(PCI_VENDOR_ID_VIA,
721
PCI_DEVICE_ID_VIA_862X_0, NULL);
722
/* Find CN400 V-Link host bridge */
724
dev = pci_get_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
727
/* Enable access to port 0x22 */
728
pci_read_config_byte(dev, reg, &pci_cmd);
729
if (!(pci_cmd & 1<<7)) {
731
pci_write_config_byte(dev, reg, pci_cmd);
732
pci_read_config_byte(dev, reg, &pci_cmd);
733
if (!(pci_cmd & 1<<7)) {
735
"Can't enable access to port 0x22.\n");
745
static int longhaul_setup_southbridge(void)
750
/* Find VT8235 southbridge */
751
dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL);
753
/* Find VT8237 southbridge */
754
dev = pci_get_device(PCI_VENDOR_ID_VIA,
755
PCI_DEVICE_ID_VIA_8237, NULL);
757
/* Set transition time to max */
758
pci_read_config_byte(dev, 0xec, &pci_cmd);
759
pci_cmd &= ~(1 << 2);
760
pci_write_config_byte(dev, 0xec, pci_cmd);
761
pci_read_config_byte(dev, 0xe4, &pci_cmd);
762
pci_cmd &= ~(1 << 7);
763
pci_write_config_byte(dev, 0xe4, pci_cmd);
764
pci_read_config_byte(dev, 0xe5, &pci_cmd);
766
pci_write_config_byte(dev, 0xe5, pci_cmd);
767
/* Get address of ACPI registers block*/
768
pci_read_config_byte(dev, 0x81, &pci_cmd);
769
if (pci_cmd & 1 << 7) {
770
pci_read_config_dword(dev, 0x88, &acpi_regs_addr);
771
acpi_regs_addr &= 0xff00;
772
printk(KERN_INFO PFX "ACPI I/O at 0x%x\n",
782
static int __cpuinit longhaul_cpu_init(struct cpufreq_policy *policy)
784
struct cpuinfo_x86 *c = &cpu_data(0);
785
char *cpuname = NULL;
789
/* Check what we have on this motherboard */
790
switch (c->x86_model) {
792
cpu_model = CPU_SAMUEL;
793
cpuname = "C3 'Samuel' [C5A]";
794
longhaul_version = TYPE_LONGHAUL_V1;
795
memcpy(mults, samuel1_mults, sizeof(samuel1_mults));
796
memcpy(eblcr, samuel1_eblcr, sizeof(samuel1_eblcr));
800
switch (c->x86_mask) {
802
longhaul_version = TYPE_LONGHAUL_V1;
803
cpu_model = CPU_SAMUEL2;
804
cpuname = "C3 'Samuel 2' [C5B]";
805
/* Note, this is not a typo, early Samuel2's had
807
memcpy(mults, samuel1_mults, sizeof(samuel1_mults));
808
memcpy(eblcr, samuel2_eblcr, sizeof(samuel2_eblcr));
811
longhaul_version = TYPE_LONGHAUL_V2;
812
if (c->x86_mask < 8) {
813
cpu_model = CPU_SAMUEL2;
814
cpuname = "C3 'Samuel 2' [C5B]";
816
cpu_model = CPU_EZRA;
817
cpuname = "C3 'Ezra' [C5C]";
819
memcpy(mults, ezra_mults, sizeof(ezra_mults));
820
memcpy(eblcr, ezra_eblcr, sizeof(ezra_eblcr));
826
cpu_model = CPU_EZRA_T;
827
cpuname = "C3 'Ezra-T' [C5M]";
828
longhaul_version = TYPE_POWERSAVER;
830
memcpy(mults, ezrat_mults, sizeof(ezrat_mults));
831
memcpy(eblcr, ezrat_eblcr, sizeof(ezrat_eblcr));
835
longhaul_version = TYPE_POWERSAVER;
837
memcpy(mults, nehemiah_mults, sizeof(nehemiah_mults));
838
memcpy(eblcr, nehemiah_eblcr, sizeof(nehemiah_eblcr));
839
switch (c->x86_mask) {
841
cpu_model = CPU_NEHEMIAH;
842
cpuname = "C3 'Nehemiah A' [C5XLOE]";
845
cpu_model = CPU_NEHEMIAH;
846
cpuname = "C3 'Nehemiah B' [C5XLOH]";
849
cpu_model = CPU_NEHEMIAH_C;
850
cpuname = "C3 'Nehemiah C' [C5P]";
859
/* Check Longhaul ver. 2 */
860
if (longhaul_version == TYPE_LONGHAUL_V2) {
861
rdmsr(MSR_VIA_LONGHAUL, lo, hi);
862
if (lo == 0 && hi == 0)
863
/* Looks like MSR isn't present */
864
longhaul_version = TYPE_LONGHAUL_V1;
867
printk(KERN_INFO PFX "VIA %s CPU detected. ", cpuname);
868
switch (longhaul_version) {
869
case TYPE_LONGHAUL_V1:
870
case TYPE_LONGHAUL_V2:
871
printk(KERN_CONT "Longhaul v%d supported.\n", longhaul_version);
873
case TYPE_POWERSAVER:
874
printk(KERN_CONT "Powersaver supported.\n");
879
longhaul_setup_southbridge();
881
/* Find ACPI data for processor */
882
acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
883
ACPI_UINT32_MAX, &longhaul_walk_callback, NULL,
886
/* Check ACPI support for C3 state */
887
if (pr != NULL && longhaul_version == TYPE_POWERSAVER) {
888
cx = &pr->power.states[ACPI_STATE_C3];
889
if (cx->address > 0 && cx->latency <= 1000)
890
longhaul_flags |= USE_ACPI_C3;
892
/* Disable if it isn't working */
894
longhaul_flags &= ~USE_ACPI_C3;
895
/* Check if northbridge is friendly */
896
if (enable_arbiter_disable())
897
longhaul_flags |= USE_NORTHBRIDGE;
899
/* Check ACPI support for bus master arbiter disable */
900
if (!(longhaul_flags & USE_ACPI_C3
901
|| longhaul_flags & USE_NORTHBRIDGE)
902
&& ((pr == NULL) || !(pr->flags.bm_control))) {
904
"No ACPI support. Unsupported northbridge.\n");
908
if (longhaul_flags & USE_NORTHBRIDGE)
909
printk(KERN_INFO PFX "Using northbridge support.\n");
910
if (longhaul_flags & USE_ACPI_C3)
911
printk(KERN_INFO PFX "Using ACPI support.\n");
913
ret = longhaul_get_ranges();
917
if ((longhaul_version != TYPE_LONGHAUL_V1) && (scale_voltage != 0))
918
longhaul_setup_voltagescaling();
920
policy->cpuinfo.transition_latency = 200000; /* nsec */
921
policy->cur = calc_speed(longhaul_get_cpu_mult());
923
ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
927
cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
932
static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
934
cpufreq_frequency_table_put_attr(policy->cpu);
938
static struct freq_attr *longhaul_attr[] = {
939
&cpufreq_freq_attr_scaling_available_freqs,
943
static struct cpufreq_driver longhaul_driver = {
944
.verify = longhaul_verify,
945
.target = longhaul_target,
947
.init = longhaul_cpu_init,
948
.exit = __devexit_p(longhaul_cpu_exit),
950
.owner = THIS_MODULE,
951
.attr = longhaul_attr,
955
static int __init longhaul_init(void)
957
struct cpuinfo_x86 *c = &cpu_data(0);
959
if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
963
if (num_online_cpus() > 1) {
964
printk(KERN_ERR PFX "More than 1 CPU detected, "
965
"longhaul disabled.\n");
969
#ifdef CONFIG_X86_IO_APIC
971
printk(KERN_ERR PFX "APIC detected. Longhaul is currently "
972
"broken in this configuration.\n");
976
switch (c->x86_model) {
978
return cpufreq_register_driver(&longhaul_driver);
980
printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
989
static void __exit longhaul_exit(void)
993
for (i = 0; i < numscales; i++) {
994
if (mults[i] == maxmult) {
995
longhaul_setstate(i);
1000
cpufreq_unregister_driver(&longhaul_driver);
1001
kfree(longhaul_table);
1004
/* Even if BIOS is exporting ACPI C3 state, and it is used
1005
* with success when CPU is idle, this state doesn't
1006
* trigger frequency transition in some cases. */
1007
module_param(disable_acpi_c3, int, 0644);
1008
MODULE_PARM_DESC(disable_acpi_c3, "Don't use ACPI C3 support");
1009
/* Change CPU voltage with frequency. Very useful to save
1010
* power, but most VIA C3 processors aren't supporting it. */
1011
module_param(scale_voltage, int, 0644);
1012
MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
1013
/* Force revision key to 0 for processors which doesn't
1014
* support voltage scaling, but are introducing itself as
1016
module_param(revid_errata, int, 0644);
1017
MODULE_PARM_DESC(revid_errata, "Ignore CPU Revision ID");
1019
MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1020
MODULE_DESCRIPTION("Longhaul driver for VIA Cyrix processors.");
1021
MODULE_LICENSE("GPL");
1023
late_initcall(longhaul_init);
1024
module_exit(longhaul_exit);
added
removed
arch/x86/kernel/cpu/cpufreq/longhaul.c
