33
33
#define SGTL5000_DAP_REG_OFFSET 0x0100
34
34
#define SGTL5000_MAX_REG_OFFSET 0x013A
36
/* default value of sgtl5000 registers except DAP */
37
static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET >> 1] = {
38
0xa011, /* 0x0000, CHIP_ID. 11 stand for revison 17 */
39
0x0000, /* 0x0002, CHIP_DIG_POWER. */
40
0x0008, /* 0x0004, CHIP_CKL_CTRL */
41
0x0010, /* 0x0006, CHIP_I2S_CTRL */
42
0x0000, /* 0x0008, reserved */
43
0x0008, /* 0x000A, CHIP_SSS_CTRL */
44
0x0000, /* 0x000C, reserved */
45
0x020c, /* 0x000E, CHIP_ADCDAC_CTRL */
46
0x3c3c, /* 0x0010, CHIP_DAC_VOL */
47
0x0000, /* 0x0012, reserved */
48
0x015f, /* 0x0014, CHIP_PAD_STRENGTH */
49
0x0000, /* 0x0016, reserved */
50
0x0000, /* 0x0018, reserved */
51
0x0000, /* 0x001A, reserved */
52
0x0000, /* 0x001E, reserved */
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0x0000, /* 0x0020, CHIP_ANA_ADC_CTRL */
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0x1818, /* 0x0022, CHIP_ANA_HP_CTRL */
55
0x0111, /* 0x0024, CHIP_ANN_CTRL */
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0x0000, /* 0x0026, CHIP_LINREG_CTRL */
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0x0000, /* 0x0028, CHIP_REF_CTRL */
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0x0000, /* 0x002A, CHIP_MIC_CTRL */
59
0x0000, /* 0x002C, CHIP_LINE_OUT_CTRL */
60
0x0404, /* 0x002E, CHIP_LINE_OUT_VOL */
61
0x7060, /* 0x0030, CHIP_ANA_POWER */
62
0x5000, /* 0x0032, CHIP_PLL_CTRL */
63
0x0000, /* 0x0034, CHIP_CLK_TOP_CTRL */
64
0x0000, /* 0x0036, CHIP_ANA_STATUS */
65
0x0000, /* 0x0038, reserved */
66
0x0000, /* 0x003A, CHIP_ANA_TEST2 */
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0x0000, /* 0x003C, CHIP_SHORT_CTRL */
68
0x0000, /* reserved */
71
/* default value of dap registers */
72
static const u16 sgtl5000_dap_regs[] = {
73
0x0000, /* 0x0100, DAP_CONTROL */
74
0x0000, /* 0x0102, DAP_PEQ */
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0x0040, /* 0x0104, DAP_BASS_ENHANCE */
76
0x051f, /* 0x0106, DAP_BASS_ENHANCE_CTRL */
77
0x0000, /* 0x0108, DAP_AUDIO_EQ */
78
0x0040, /* 0x010A, DAP_SGTL_SURROUND */
79
0x0000, /* 0x010C, DAP_FILTER_COEF_ACCESS */
80
0x0000, /* 0x010E, DAP_COEF_WR_B0_MSB */
81
0x0000, /* 0x0110, DAP_COEF_WR_B0_LSB */
82
0x0000, /* 0x0112, reserved */
83
0x0000, /* 0x0114, reserved */
84
0x002f, /* 0x0116, DAP_AUDIO_EQ_BASS_BAND0 */
85
0x002f, /* 0x0118, DAP_AUDIO_EQ_BAND0 */
86
0x002f, /* 0x011A, DAP_AUDIO_EQ_BAND2 */
87
0x002f, /* 0x011C, DAP_AUDIO_EQ_BAND3 */
88
0x002f, /* 0x011E, DAP_AUDIO_EQ_TREBLE_BAND4 */
89
0x8000, /* 0x0120, DAP_MAIN_CHAN */
90
0x0000, /* 0x0122, DAP_MIX_CHAN */
91
0x0510, /* 0x0124, DAP_AVC_CTRL */
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0x1473, /* 0x0126, DAP_AVC_THRESHOLD */
93
0x0028, /* 0x0128, DAP_AVC_ATTACK */
94
0x0050, /* 0x012A, DAP_AVC_DECAY */
95
0x0000, /* 0x012C, DAP_COEF_WR_B1_MSB */
96
0x0000, /* 0x012E, DAP_COEF_WR_B1_LSB */
97
0x0000, /* 0x0130, DAP_COEF_WR_B2_MSB */
98
0x0000, /* 0x0132, DAP_COEF_WR_B2_LSB */
99
0x0000, /* 0x0134, DAP_COEF_WR_A1_MSB */
100
0x0000, /* 0x0136, DAP_COEF_WR_A1_LSB */
101
0x0000, /* 0x0138, DAP_COEF_WR_A2_MSB */
102
0x0000, /* 0x013A, DAP_COEF_WR_A2_LSB */
36
/* default value of sgtl5000 registers */
37
static const u16 sgtl5000_regs[SGTL5000_MAX_REG_OFFSET] = {
38
[SGTL5000_CHIP_CLK_CTRL] = 0x0008,
39
[SGTL5000_CHIP_I2S_CTRL] = 0x0010,
40
[SGTL5000_CHIP_SSS_CTRL] = 0x0008,
41
[SGTL5000_CHIP_DAC_VOL] = 0x3c3c,
42
[SGTL5000_CHIP_PAD_STRENGTH] = 0x015f,
43
[SGTL5000_CHIP_ANA_HP_CTRL] = 0x1818,
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[SGTL5000_CHIP_ANA_CTRL] = 0x0111,
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[SGTL5000_CHIP_LINE_OUT_VOL] = 0x0404,
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[SGTL5000_CHIP_ANA_POWER] = 0x7060,
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[SGTL5000_CHIP_PLL_CTRL] = 0x5000,
48
[SGTL5000_DAP_BASS_ENHANCE] = 0x0040,
49
[SGTL5000_DAP_BASS_ENHANCE_CTRL] = 0x051f,
50
[SGTL5000_DAP_SURROUND] = 0x0040,
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[SGTL5000_DAP_EQ_BASS_BAND0] = 0x002f,
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[SGTL5000_DAP_EQ_BASS_BAND1] = 0x002f,
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[SGTL5000_DAP_EQ_BASS_BAND2] = 0x002f,
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[SGTL5000_DAP_EQ_BASS_BAND3] = 0x002f,
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[SGTL5000_DAP_EQ_BASS_BAND4] = 0x002f,
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[SGTL5000_DAP_MAIN_CHAN] = 0x8000,
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[SGTL5000_DAP_AVC_CTRL] = 0x0510,
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[SGTL5000_DAP_AVC_THRESHOLD] = 0x1473,
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[SGTL5000_DAP_AVC_ATTACK] = 0x0028,
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[SGTL5000_DAP_AVC_DECAY] = 0x0050,
105
63
/* regulator supplies for sgtl5000, VDDD is an optional external supply */
1037
993
reg == SGTL5000_CHIP_CLK_CTRL)
1040
snd_soc_write(codec, reg, cache[i]);
996
snd_soc_write(codec, reg, cache[reg]);
1043
999
/* restore dap registers */
1044
for (i = SGTL5000_DAP_REG_OFFSET >> 1;
1045
i < SGTL5000_MAX_REG_OFFSET >> 1; i++) {
1048
snd_soc_write(codec, reg, cache[i]);
1000
for (reg = SGTL5000_DAP_REG_OFFSET; reg < SGTL5000_MAX_REG_OFFSET; reg += 2)
1001
snd_soc_write(codec, reg, cache[reg]);
1052
1004
* restore power and other regs according
1053
1005
* to set_power() and set_clock()
1055
1007
snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL,
1056
cache[SGTL5000_CHIP_LINREG_CTRL >> 1]);
1008
cache[SGTL5000_CHIP_LINREG_CTRL]);
1058
1010
snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER,
1059
cache[SGTL5000_CHIP_ANA_POWER >> 1]);
1011
cache[SGTL5000_CHIP_ANA_POWER]);
1061
1013
snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL,
1062
cache[SGTL5000_CHIP_CLK_CTRL >> 1]);
1014
cache[SGTL5000_CHIP_CLK_CTRL]);
1064
1016
snd_soc_write(codec, SGTL5000_CHIP_REF_CTRL,
1065
cache[SGTL5000_CHIP_REF_CTRL >> 1]);
1017
cache[SGTL5000_CHIP_REF_CTRL]);
1067
1019
snd_soc_write(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1068
cache[SGTL5000_CHIP_LINE_OUT_CTRL >> 1]);
1020
cache[SGTL5000_CHIP_LINE_OUT_CTRL]);