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Viewing changes to drivers/gpu/drm/radeon/atombios_crtc.c

  • Committer: Package Import Robot
  • Author(s): John Rigby, John Rigby
  • Date: 2011-09-26 10:44:23 UTC
  • Revision ID: package-import@ubuntu.com-20110926104423-3o58a3c1bj7x00rs
Tags: 3.0.0-1007.9
https://launchpad.net/bugs/826021
[ John Rigby ]

Enable crypto modules and remove crypto-modules from
exclude-module files
LP: #826021

Show diffs side-by-side

added added

removed removed

Lines of Context:
drivers/gpu/drm/radeon/atombios_crtc.c
420
420
 
421
421
        if (ASIC_IS_DCE5(rdev)) {
422
422
                args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
423
 
                args.v3.ucSpreadSpectrumType = ss->type;
 
423
                args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
424
424
                switch (pll_id) {
425
425
                case ATOM_PPLL1:
426
426
                        args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
440
440
                case ATOM_PPLL_INVALID:
441
441
                        return;
442
442
                }
443
 
                args.v2.ucEnable = enable;
 
443
                args.v3.ucEnable = enable;
 
444
                if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
 
445
                        args.v3.ucEnable = ATOM_DISABLE;
444
446
        } else if (ASIC_IS_DCE4(rdev)) {
445
447
                args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
446
 
                args.v2.ucSpreadSpectrumType = ss->type;
 
448
                args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
447
449
                switch (pll_id) {
448
450
                case ATOM_PPLL1:
449
451
                        args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
464
466
                        return;
465
467
                }
466
468
                args.v2.ucEnable = enable;
 
469
                if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
 
470
                        args.v2.ucEnable = ATOM_DISABLE;
467
471
        } else if (ASIC_IS_DCE3(rdev)) {
468
472
                args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
469
 
                args.v1.ucSpreadSpectrumType = ss->type;
 
473
                args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
470
474
                args.v1.ucSpreadSpectrumStep = ss->step;
471
475
                args.v1.ucSpreadSpectrumDelay = ss->delay;
472
476
                args.v1.ucSpreadSpectrumRange = ss->range;
473
477
                args.v1.ucPpll = pll_id;
474
478
                args.v1.ucEnable = enable;
475
479
        } else if (ASIC_IS_AVIVO(rdev)) {
476
 
                if (enable == ATOM_DISABLE) {
 
480
                if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
 
481
                    (ss->type & ATOM_EXTERNAL_SS_MASK)) {
477
482
                        atombios_disable_ss(crtc);
478
483
                        return;
479
484
                }
480
485
                args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
481
 
                args.lvds_ss_2.ucSpreadSpectrumType = ss->type;
 
486
                args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
482
487
                args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
483
488
                args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
484
489
                args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
485
490
                args.lvds_ss_2.ucEnable = enable;
486
491
        } else {
487
 
                if (enable == ATOM_DISABLE) {
 
492
                if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
 
493
                    (ss->type & ATOM_EXTERNAL_SS_MASK)) {
488
494
                        atombios_disable_ss(crtc);
489
495
                        return;
490
496
                }
491
497
                args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
492
 
                args.lvds_ss.ucSpreadSpectrumType = ss->type;
 
498
                args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
493
499
                args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
494
500
                args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
495
501
                args.lvds_ss.ucEnable = enable;
512
518
        struct radeon_device *rdev = dev->dev_private;
513
519
        struct drm_encoder *encoder = NULL;
514
520
        struct radeon_encoder *radeon_encoder = NULL;
 
521
        struct drm_connector *connector = NULL;
515
522
        u32 adjusted_clock = mode->clock;
516
523
        int encoder_mode = 0;
517
524
        u32 dp_clock = mode->clock;
546
553
        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
547
554
                if (encoder->crtc == crtc) {
548
555
                        radeon_encoder = to_radeon_encoder(encoder);
 
556
                        connector = radeon_get_connector_for_encoder(encoder);
 
557
                        if (connector)
 
558
                                bpc = connector->display_info.bpc;
549
559
                        encoder_mode = atombios_get_encoder_mode(encoder);
550
 
                        if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
551
 
                                struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 
560
                        if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 
561
                            radeon_encoder_is_dp_bridge(encoder)) {
552
562
                                if (connector) {
553
563
                                        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
554
564
                                        struct radeon_connector_atom_dig *dig_connector =
612
622
                                args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
613
623
                                args.v1.ucTransmitterID = radeon_encoder->encoder_id;
614
624
                                args.v1.ucEncodeMode = encoder_mode;
615
 
                                if (ss_enabled)
 
625
                                if (ss_enabled && ss->percentage)
616
626
                                        args.v1.ucConfig |=
617
627
                                                ADJUST_DISPLAY_CONFIG_SS_ENABLE;
618
628
 
625
635
                                args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
626
636
                                args.v3.sInput.ucEncodeMode = encoder_mode;
627
637
                                args.v3.sInput.ucDispPllConfig = 0;
628
 
                                if (ss_enabled)
 
638
                                if (ss_enabled && ss->percentage)
629
639
                                        args.v3.sInput.ucDispPllConfig |=
630
640
                                                DISPPLL_CONFIG_SS_ENABLE;
631
 
                                if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 
641
                                if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) ||
 
642
                                    radeon_encoder_is_dp_bridge(encoder)) {
632
643
                                        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
633
644
                                        if (encoder_mode == ATOM_ENCODER_MODE_DP) {
634
645
                                                args.v3.sInput.ucDispPllConfig |=
660
671
                                                                DISPPLL_CONFIG_DUAL_LINK;
661
672
                                        }
662
673
                                }
 
674
                                if (radeon_encoder_is_dp_bridge(encoder)) {
 
675
                                        struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
 
676
                                        struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
 
677
                                        args.v3.sInput.ucExtTransmitterID = ext_radeon_encoder->encoder_id;
 
678
                                } else
 
679
                                        args.v3.sInput.ucExtTransmitterID = 0;
 
680
 
663
681
                                atom_execute_table(rdev->mode_info.atom_context,
664
682
                                                   index, (uint32_t *)&args);
665
683
                                adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
754
772
                                      u32 ref_div,
755
773
                                      u32 fb_div,
756
774
                                      u32 frac_fb_div,
757
 
                                      u32 post_div)
 
775
                                      u32 post_div,
 
776
                                      int bpc,
 
777
                                      bool ss_enabled,
 
778
                                      struct radeon_atom_ss *ss)
758
779
{
759
780
        struct drm_device *dev = crtc->dev;
760
781
        struct radeon_device *rdev = dev->dev_private;
801
822
                        args.v3.ucPostDiv = post_div;
802
823
                        args.v3.ucPpll = pll_id;
803
824
                        args.v3.ucMiscInfo = (pll_id << 2);
 
825
                        if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 
826
                                args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
804
827
                        args.v3.ucTransmitterId = encoder_id;
805
828
                        args.v3.ucEncoderMode = encoder_mode;
806
829
                        break;
812
835
                        args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
813
836
                        args.v5.ucPostDiv = post_div;
814
837
                        args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 
838
                        if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 
839
                                args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
 
840
                        switch (bpc) {
 
841
                        case 8:
 
842
                        default:
 
843
                                args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
 
844
                                break;
 
845
                        case 10:
 
846
                                args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
 
847
                                break;
 
848
                        }
815
849
                        args.v5.ucTransmitterID = encoder_id;
816
850
                        args.v5.ucEncoderMode = encoder_mode;
817
851
                        args.v5.ucPpll = pll_id;
824
858
                        args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
825
859
                        args.v6.ucPostDiv = post_div;
826
860
                        args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
 
861
                        if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 
862
                                args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
 
863
                        switch (bpc) {
 
864
                        case 8:
 
865
                        default:
 
866
                                args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
 
867
                                break;
 
868
                        case 10:
 
869
                                args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
 
870
                                break;
 
871
                        case 12:
 
872
                                args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
 
873
                                break;
 
874
                        case 16:
 
875
                                args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
 
876
                                break;
 
877
                        }
827
878
                        args.v6.ucTransmitterID = encoder_id;
828
879
                        args.v6.ucEncoderMode = encoder_mode;
829
880
                        args.v6.ucPpll = pll_id;
855
906
        int encoder_mode = 0;
856
907
        struct radeon_atom_ss ss;
857
908
        bool ss_enabled = false;
 
909
        int bpc = 8;
858
910
 
859
911
        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
860
912
                if (encoder->crtc == crtc) {
891
943
                struct radeon_connector_atom_dig *dig_connector =
892
944
                        radeon_connector->con_priv;
893
945
                int dp_clock;
 
946
                bpc = connector->display_info.bpc;
894
947
 
895
948
                switch (encoder_mode) {
896
949
                case ATOM_ENCODER_MODE_DP:
897
950
                        /* DP/eDP */
898
951
                        dp_clock = dig_connector->dp_clock / 10;
899
 
                        if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
900
 
                                if (ASIC_IS_DCE4(rdev))
901
 
                                        ss_enabled =
902
 
                                                radeon_atombios_get_asic_ss_info(rdev, &ss,
903
 
                                                                                 dig->lcd_ss_id,
904
 
                                                                                 dp_clock);
905
 
                                else
 
952
                        if (ASIC_IS_DCE4(rdev))
 
953
                                ss_enabled =
 
954
                                        radeon_atombios_get_asic_ss_info(rdev, &ss,
 
955
                                                                         ASIC_INTERNAL_SS_ON_DP,
 
956
                                                                         dp_clock);
 
957
                        else {
 
958
                                if (dp_clock == 16200) {
906
959
                                        ss_enabled =
907
960
                                                radeon_atombios_get_ppll_ss_info(rdev, &ss,
908
 
                                                                                 dig->lcd_ss_id);
909
 
                        } else {
910
 
                                if (ASIC_IS_DCE4(rdev))
911
 
                                        ss_enabled =
912
 
                                                radeon_atombios_get_asic_ss_info(rdev, &ss,
913
 
                                                                                 ASIC_INTERNAL_SS_ON_DP,
914
 
                                                                                 dp_clock);
915
 
                                else {
916
 
                                        if (dp_clock == 16200) {
917
 
                                                ss_enabled =
918
 
                                                        radeon_atombios_get_ppll_ss_info(rdev, &ss,
919
 
                                                                                         ATOM_DP_SS_ID2);
920
 
                                                if (!ss_enabled)
921
 
                                                        ss_enabled =
922
 
                                                                radeon_atombios_get_ppll_ss_info(rdev, &ss,
923
 
                                                                                                 ATOM_DP_SS_ID1);
924
 
                                        } else
 
961
                                                                                 ATOM_DP_SS_ID2);
 
962
                                        if (!ss_enabled)
925
963
                                                ss_enabled =
926
964
                                                        radeon_atombios_get_ppll_ss_info(rdev, &ss,
927
965
                                                                                         ATOM_DP_SS_ID1);
928
 
                                }
 
966
                                } else
 
967
                                        ss_enabled =
 
968
                                                radeon_atombios_get_ppll_ss_info(rdev, &ss,
 
969
                                                                                 ATOM_DP_SS_ID1);
929
970
                        }
930
971
                        break;
931
972
                case ATOM_ENCODER_MODE_LVDS:
974
1015
 
975
1016
        atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
976
1017
                                  encoder_mode, radeon_encoder->encoder_id, mode->clock,
977
 
                                  ref_div, fb_div, frac_fb_div, post_div);
 
1018
                                  ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
978
1019
 
979
1020
        if (ss_enabled) {
980
1021
                /* calculate ss amount and step size */
982
1023
                        u32 step_size;
983
1024
                        u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
984
1025
                        ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
985
 
                        ss.amount |= ((amount - (ss.amount * 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
 
1026
                        ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
986
1027
                                ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
987
1028
                        if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
988
1029
                                step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
1011
1052
        uint64_t fb_location;
1012
1053
        uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1013
1054
        u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1014
 
        u32 tmp;
 
1055
        u32 tmp, viewport_w, viewport_h;
1015
1056
        int r;
1016
1057
 
1017
1058
        /* no fb bound */
1137
1178
        y &= ~1;
1138
1179
        WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1139
1180
               (x << 16) | y);
 
1181
        viewport_w = crtc->mode.hdisplay;
 
1182
        viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1140
1183
        WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1141
 
               (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
 
1184
               (viewport_w << 16) | viewport_h);
1142
1185
 
1143
1186
        /* pageflip setup */
1144
1187
        /* make sure flip is at vb rather than hb */
1179
1222
        uint64_t fb_location;
1180
1223
        uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1181
1224
        u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1182
 
        u32 tmp;
 
1225
        u32 tmp, viewport_w, viewport_h;
1183
1226
        int r;
1184
1227
 
1185
1228
        /* no fb bound */
1304
1347
        y &= ~1;
1305
1348
        WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1306
1349
               (x << 16) | y);
 
1350
        viewport_w = crtc->mode.hdisplay;
 
1351
        viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1307
1352
        WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1308
 
               (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
 
1353
               (viewport_w << 16) | viewport_h);
1309
1354
 
1310
1355
        /* pageflip setup */
1311
1356
        /* make sure flip is at vb rather than hb */
1395
1440
        uint32_t pll_in_use = 0;
1396
1441
 
1397
1442
        if (ASIC_IS_DCE4(rdev)) {
1398
 
                /* if crtc is driving DP and we have an ext clock, use that */
1399
1443
                list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1400
1444
                        if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
 
1445
                                /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
 
1446
                                 * depending on the asic:
 
1447
                                 * DCE4: PPLL or ext clock
 
1448
                                 * DCE5: DCPLL or ext clock
 
1449
                                 *
 
1450
                                 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
 
1451
                                 * PPLL/DCPLL programming and only program the DP DTO for the
 
1452
                                 * crtc virtual pixel clock.
 
1453
                                 */
1401
1454
                                if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1402
 
                                        if (rdev->clock.dp_extclk)
 
1455
                                        if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
1403
1456
                                                return ATOM_PPLL_INVALID;
1404
1457
                                }
1405
1458
                        }
1515
1568
static void atombios_crtc_disable(struct drm_crtc *crtc)
1516
1569
{
1517
1570
        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 
1571
        struct radeon_atom_ss ss;
 
1572
 
1518
1573
        atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1519
1574
 
1520
1575
        switch (radeon_crtc->pll_id) {
1522
1577
        case ATOM_PPLL2:
1523
1578
                /* disable the ppll */
1524
1579
                atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1525
 
                                          0, 0, ATOM_DISABLE, 0, 0, 0, 0);
 
1580
                                          0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1526
1581
                break;
1527
1582
        default:
1528
1583
                break;